JPH08316196A - Fabrication method of semiconductor device - Google Patents

Abstract

PURPOSE: To provide a fabrication method of a semiconductor device wherein a workpiece substrate such as a semiconductor water is accurately and uniformly treated with a solution, and visual observation of treatment situation or selective treatment of the same is ensured. CONSTITUTION: When a workpiece substrate 2 is treatment with a solution by holding a treatment solution 3 between a flat plate member 4 and the substrate 2, a treatment speed is controlled with the weight of the flat plate member 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device,
The present invention relates to a method for manufacturing a semiconductor device involving solution processing, such as a cleaning step, an etching step, or a semiconductor substrate evaluation step using etching.

[0002]

2. Description of the Related Art Conventionally, in a process involving solution processing such as a cleaning process, an etching process, or a semiconductor substrate evaluation process using etching, a plurality of semiconductor wafers are stored in a carrier and the entire carrier is processed. The semiconductor wafer has been cleaned and etched by being immersed in the liquid.

As another method, the surface of the semiconductor wafer has been cleaned by spraying a cleaning liquid onto the semiconductor wafer using a spray. However, these cleaning methods or etching methods require a large amount of cleaning liquid or etching liquid to be used, which has been a cause of increasing the manufacturing cost.

In order to improve such a drawback, the present inventor makes a semiconductor substrate and a flat plate member made of ceramics or the like face each other, and a small amount of an etching liquid or a cleaning liquid is sandwiched in the space between the semiconductor substrate and the flat plate member for processing. Therefore, it is proposed that the amount of the processing liquid used is significantly reduced (Japanese Patent Laid-Open No. 7-8).
6232).

FIG. 8 is an explanatory view of a solution processing step using a conventional flat plate member. A substrate 2 to be processed such as a silicon semiconductor wafer is placed on a processing base 1 and the processed substrate 2 is processed. A processing liquid 3 such as an etching liquid is dropped on the surface of the substrate 2.

Then, a flat plate member 4 made of ceramics having a size similar to that of the substrate 2 to be processed is placed on the substrate 2, and the treatment liquid 3 is sandwiched between the substrate 2 to be treated and allowed to stand for a predetermined period of time, so that etching or the like is prevented. Solution processing was performed.

[0007]

However, in such a processing method, when a reaction product, particularly a gaseous reaction product, is generated in the processing step, the generated gas causes a gas in the plane of the substrate to be processed to be processed. There are problems that the progress of uniform reaction is hindered and that the processing speed differs depending on the flat plate member.

Further, in general, since the flat plate member used in this processing step is an opaque member such as ceramics, the reaction situation cannot be visually observed and grasped, so that there is a problem in confirming the end time of the reaction. .

Further, since the flat plate member has a size similar to that of the substrate to be processed, the processing liquid sandwiched between them also covers the entire surface of the substrate to be processed. The selected area could not be selected without masking.

Therefore, according to the present invention, the structure of the flat plate member,
Alternatively, by devising the material, the purpose is to perform a solution treatment on a substrate to be treated such as a semiconductor wafer with high accuracy and uniformity, and at the same time, enable visual observation of the treatment situation or selective treatment. With the goal.

[0011]

FIG. 1 is an explanatory view of the principle configuration of the present invention, and means for solving the problems in the present application will be described with reference to FIG. In addition, in FIG.
It is sectional drawing which shows an etching process schematically.

FIG. 1 (1) The present invention relates to a method of manufacturing a semiconductor device in which a substrate 2 to be processed is solution-processed using a flat plate member 4, and a treatment liquid 3 is interposed between the flat plate member 4 and the substrate 2 to be processed. The processing speed is controlled by the weight of the flat plate member 4 when the substrate 2 to be processed is sandwiched between. The reference numeral 1 in the figure is
It is a processing base.

(2) Further, according to the present invention, in the method of manufacturing a semiconductor device in which the substrate 2 to be processed is solution-processed using the flat plate member 4, the processing liquid 3 is interposed between the flat plate member 4 and the substrate 2 to be processed. When the substrate 2 to be processed is sandwiched and processed, the substrate 2 to be processed 2
It is characterized by giving vibration to.

(3) Further, according to the present invention, in the method of manufacturing a semiconductor device in which the substrate 2 to be processed is solution-processed using the flat plate member 4, the processing liquid 3 is interposed between the flat plate member 4 and the substrate 2 to be processed. The substrate 2 to be processed is sandwiched between the flat plate member 4 and
The surface facing the substrate 2 to be processed has a convex shape.

(4) Further, according to the present invention, in the method of manufacturing a semiconductor device in which the substrate 2 to be processed is solution-processed using the flat plate member 4, the processing liquid 3 is interposed between the flat plate member 4 and the substrate 2 to be processed. The substrate 2 to be processed is sandwiched between the flat plate member 4 and
The radial grooves are provided on the surface facing the substrate 2 to be processed.

(5) Further, according to the present invention, in the method of manufacturing a semiconductor device in which the substrate 2 to be processed is solution-processed by using the flat plate member 4, the processing liquid 3 is interposed between the flat plate member 4 and the substrate 2 to be processed. The substrate 2 to be processed is sandwiched between the flat plate member 4 and
Is composed of a transparent member.

(6) Further, according to the present invention, in the method of manufacturing a semiconductor device in which the substrate 2 to be processed is solution-treated by using the flat plate member 4, the processing liquid 3 is interposed between the flat plate member 4 and the substrate 2 to be processed. When the substrate 2 to be processed is sandwiched, the size of the flat plate member 4 is made smaller than the size of the substrate 2 to be processed, and a partial region of the substrate 2 to be processed is selectively processed. .

(7) Further, the present invention is characterized in that in any one of the above (1) to (6), the solution treatment is a washing treatment.

(8) Further, the present invention is characterized in that, in any one of the above (1) to (6), the solution treatment is an etching treatment.

(9) Further, the present invention is characterized in that in the above (8), the etching process is an etching process for evaluating the substrate 2 to be processed.

[0021]

When the processing liquid is sandwiched between the flat plate member 4 and the substrate 2 to be processed, the processing speed depends on the weight of the flat plate member 4. By adjusting, the processing speed can be controlled accurately.

When the processing liquid 3 is processed by sandwiching the processing liquid 3 between the flat plate member 4 and the processing substrate 2, the processing liquid 3 is agitated by vibrating the processing substrate 2. As a result, uniform processing within the surface of the substrate 2 to be processed becomes possible.

Further, the processing liquid 3 is sandwiched between the flat plate member 4 and the substrate 2 to be processed, and the surface of the flat plate member 4 facing the substrate 3 is made convex.
Since the gaseous reaction product generated in the processing step can be removed to the outside of the processing liquid 3, it is possible to perform uniform processing within the surface of the substrate 2 to be processed.

The processing liquid 3 is sandwiched between the flat plate member 4 and the substrate 2 to be processed, and a radial groove is provided on the surface of the flat plate member 4 facing the substrate 2 to be processed. As a result, the gas reaction product generated in the processing step can be removed to the outside of the processing liquid 3 through the groove, so that uniform processing within the surface of the substrate 2 to be processed becomes possible.

The processing liquid 3 is sandwiched between the flat plate member 4 and the substrate 2 to be processed, and the flat plate member 4 is made of a transparent material so that the reaction state can be visually observed. It can be monitored and the end point of etching and the like can be easily determined.

Further, when the processing liquid 3 is sandwiched between the flat plate member 4 and the substrate 2 to be processed, the size of the flat plate member 4 is made smaller than the size of the substrate 2 to be processed. As a result, selective processing of a partial region of the substrate 2 to be processed becomes possible without a mask.

Further, according to the present invention, by the solution treatment under the above various conditions, a cleaning treatment, an etching treatment with high accuracy and a small amount of the treatment liquid 3 used, or an etching for evaluating the substrate 2 to be treated. Processing becomes possible.

[0028]

First, the manufacturing process of the first embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 2A, a diameter of 150 m is set as a substrate to be processed on the processing base 1.
A semiconductor substrate 5 of m (6 inches) is placed, and 1 g of an etching solution 6 of HF: HNO ₃ : H ₂ O = 1: 1: 2 (volume ratio) is dropped on the surface of the semiconductor substrate 5, and then, The ceramic substrate 7 having the same size as the semiconductor substrate 5 is covered, and the etching solution 6 is sandwiched between the semiconductor substrate 5 and left for a predetermined time to perform an etching process.

See FIG. 2B. FIG. 2B shows the measurement results of the etching rate when the weight of the ceramic substrate 7 is changed during the etching process. As is clear from the figure, When the weight of the ceramic substrate 7 is 15 g, the etching rate is 275 nm / min. Further, the weight of the ceramic substrate 7 is 6 g and the measurement result is 200 nm.
/ Min and 201 nm / min.

From this measurement result, it is understood that the etching rate increases as the weight of the ceramic substrate 7 increases, and that the etching rate is the same and does not vary when the weight is the same.

Therefore, when such an etching process is performed, the etching amount of the semiconductor substrate 5 can be accurately controlled by adjusting the weight of the ceramic substrate 7.

Next, a second embodiment of the present invention will be described with reference to FIG. First, a semiconductor substrate 5 having a diameter of 4 inches is placed on a vibration oscillator 8 having a frequency of 10 MHz, and HF: HNO ₃ : H ₂ O = 1 on the surface of the semiconductor substrate 5. 1: 2 (capacity ratio)
1 g of the etching solution 6 of is then dropped, and then the semiconductor substrate 5
After the ceramic substrate 7 having a size of about 6 g and a weight of 6 g is covered and the etching liquid 6 is sandwiched between the substrate 5 and the semiconductor substrate 5, the vibration oscillator 8 vibrates with an amplitude of 1 μm and an acceleration of 1 gal or more. Is applied to the semiconductor substrate 5 for a predetermined period of time to perform etching processing.

See FIG. 3B. FIG. 3B shows the measurement results regarding the variation of the in-plane etching rate with and without vibration during the etching process, which is clear from the figure. As described above, when the vibration is applied, the variation of the in-plane etch rate is 3% in relative standard deviation (RSD), and the relative standard deviation of the variation of the in-plane etch rate when the vibration is not applied. The uniformity of the in-plane etching rate is significantly improved compared to (RSD) of 15%.

Therefore, even if a gas reaction product or the like is generated in the central portion of the semiconductor substrate 5 by vibrating the semiconductor substrate 5 during the etching process, the etching liquid 6 is agitated and the same on each region of the surface of the semiconductor substrate 5. Since the etching liquid 6 comes into contact with the condition, the in-plane etching rate can be made uniform.

Next, a third embodiment of the present invention will be described with reference to FIG. See FIG. 4A. First, the semiconductor substrate 5 having a diameter of 6 inches is provided on the processing base 1.
Is placed on the surface of the semiconductor substrate 5, and HF: HNO ₃ :
1 g of the etching solution 6 with H ₂ O = 1: 1: 2 (volume ratio)
Then, the etching liquid 6 is dropped and then covered with a ceramic substrate 9 having a size similar to that of the semiconductor substrate 5, a weight of 15 g, and a warp so that the surface facing the semiconductor substrate 5 is convex. After being sandwiched between the semiconductor substrate 5 and the semiconductor substrate 5, it is left for a predetermined time to perform an etching process. In this case,
The warp d of the peripheral portion with respect to the flat surface is 0.1 mm, and the surface facing the semiconductor substrate 5 is a convex warp having a gentle slope.

See FIG. 4B. FIG. 4B shows variations in the in-plane etch rate when the warped ceramic substrate 9 is used during etching and when the non-warped ceramic substrate 7 is used. As shown in the figure, the relative standard deviation (RSD) of the variation of the in-plane etching rate when the warped ceramic substrate 9 is used is 7%, while the warpage is shown. Relative standard deviation of variations in in-plane etch rate (R
SD) is 15%, and the uniformity of the in-plane etching rate is improved.

This is because by providing the ceramic substrate 9 with a warp, even if a gas reaction product or the like is generated in the central portion of the semiconductor substrate 5, the etching liquid 6 is nonuniformly pushed by the ceramic substrate 9 Since reaction products and the like are pushed out to the peripheral portion and eliminated, the etching liquid 6 under substantially the same conditions is applied to each region of the surface of the semiconductor substrate 5.
Are in contact with each other, and the in-plane etching rate can be made uniform.

If the warp of the ceramics substrate 9 becomes too large, the thickness of the etching solution 6 in contact with the surface of the semiconductor substrate 5 will be too large, and uneven etching will be carried out. The degree is 1
The range of 0 to 0.1 mm is suitable when converted to a 6 mm wafer of 50 mm.

Next, a fourth embodiment of the present invention will be described with reference to FIG. Note that FIG. 5B shows the surface of the ceramic substrate facing the semiconductor substrate. 5A and 5B. First, a semiconductor substrate 5 having a diameter of 4 inches is provided on the processing base 1.
Is placed on the surface of the semiconductor substrate 5, and HF: HNO ₃ :
1 g of the etching solution 6 with H ₂ O = 1: 1: 2 (volume ratio)
Then, the etching solution 6 is dropped onto the ceramic substrate 7 having a size similar to that of the semiconductor substrate 5, a weight of 6 g, and a radial groove 10 provided on the surface facing the semiconductor substrate 5. After being sandwiched between the semiconductor substrate 5 and the semiconductor substrate 5, it is left for a predetermined time to perform an etching process. The number of radial grooves 10 in this case is 12, and the depth thereof is 0.2 mm.
The width is 3 mm.

See FIG. 5C. FIG. 5C shows in-plane etching when using the ceramic substrate 7 provided with the groove 10 in the etching process and when using the ceramic substrate 7 having no groove. FIG. 4 shows the measurement results regarding the variation of the etching rate, and as is clear from the figure, the relative standard deviation (R) of the variation of the in-plane etching rate when the ceramic substrate 7 provided with the groove 10 is used.
SD) is 4%, whereas the relative standard deviation (RSD) of variations in the in-plane etching rate is 15% when the ceramic substrate 7 having no groove is used, and the in-plane etching rate is uniform. Has improved.

This is because by providing the groove 10 in the ceramic substrate 7, even if a gas reaction product or the like is generated in the central portion of the semiconductor substrate 5, the etching liquid 6 is pushed by the ceramic substrate 7 to generate the gas reaction product. Since an object or the like is pushed out to the peripheral portion along the groove 10 and eliminated, each region of the surface of the semiconductor substrate 5 comes into contact with the etching solution 6 under substantially the same condition, and the in-plane etching rate is made uniform. be able to.

The number of grooves 10 in this case is 3 to 100.
The range of the book is suitable, and the width of the groove is 5 mm or less,
Moreover, the depth of the groove is preferably 0.3 mm or less.

Next, a fifth embodiment of the present invention will be described with reference to FIG. See FIG. 6. First, the semiconductor substrate 5 having the SiO ₂ film 11 formed on the surface thereof is placed on the processing base 1, and a 5% HF solution is placed on the SiO ₂ film 11 provided on the surface of the semiconductor substrate 5. Dropping, and then the transparent substrate 1 having the same size as the semiconductor substrate 5.
After being covered with 2, the etching solution 6 is sandwiched between the etching solution 6 and the semiconductor substrate 5, and then left for a predetermined time to perform an etching treatment of the SiO ₂ film 11.

In this case, the transparent substrate 12 is a sapphire substrate or a CVD-SiC substrate. The latter CVD-SiC substrate is a carbon substrate having a 100 μm-order SiC film formed by the CVD method. After depositing, the carbon substrate was baked and removed, leaving only the SiC deposited film.

As described above, when the transparent substrate 12 is used instead of the ceramic substrate 7, the etching end point of the SiO ₂ film 11 can be visually observed by observing it from the upper portion of the transparent substrate 12, and therefore it is more than necessary. The etching process can be completed without taking the processing time of.

Next, a sixth embodiment of the present invention will be described with reference to FIG. 7A and 7B. First, the semiconductor substrate 5 is placed on the processing base 1, and HF: HNO ₃ : H ₂ O is placed on a predetermined region of the surface of the semiconductor substrate 5.
= 1: 1: 2 (capacity ratio), a small amount of the etching solution 6 is dropped, and then the microceramic substrate 13 having an area smaller than the area of the semiconductor substrate 5 is covered to etch the etching solution 6
After being sandwiched between the semiconductor substrate 5 and the semiconductor substrate 5, it is left for a predetermined time to perform an etching process.

In this case, since the etching treatment is selectively performed only in the region covered with the fine ceramics substrate 13, it is possible to perform selective etching without a mask, that is, without selectively providing an etching mask or the like. The selective etching treatment area can be determined depending on the size of the fine ceramics substrate 13.

In the first to sixth embodiments, conditions such as weight, vibration, warpage, groove, transparency, and area are independently controlled to control the etching rate and the in-plane etching rate. Although the uniformity was controlled, the reaction state was visually discriminated, or the selection process was performed, these conditions may be mutually imposed.

For example, the technical idea of controlling the etching rate by the weight of the ceramic substrate 7 of the first embodiment can be applied to the second to sixth embodiments as it is, and thereby the etching rate can be controlled accurately. With good control, it is possible to control the uniformity of the in-plane etching rate, visually determine the reaction status, or perform selection processing.

Further, the technical idea of controlling the uniformity of the in-plane etching rate by applying the vibration of the second embodiment can be applied to the third to sixth embodiments as it is. The uniformity of the in-plane etching rate can be further improved, and the reaction state can be visually discriminated or the selective treatment can be performed in a state where the uniformity of the in-plane etching rate is improved.

Further, the technical idea of the other embodiments can be diverted to the other embodiments, and two or more technical ideas may be combined. In that case, the total sum is obtained. A synergistic or synergistic effect can be obtained.

In each of the above-mentioned embodiments, the silicon semiconductor etching process or the SiO ₂ film etching process is described, but the present invention is not limited to such an etching process. The present invention is also applied to an etching process step for evaluating the impurity concentration of a substrate, a cleaning process step, or the like.

When applied to the etching process for evaluating the impurity concentration of the substrate, the etching solution 6 after the etching process is recovered and the components contained in the etching solution 6 are analyzed. The characteristics of the semiconductor substrate 5 are evaluated by measuring the impurity concentration or the impurity concentration distribution in the thickness direction.

In the case of the sixth embodiment, the in-plane impurity concentration distribution of the semiconductor substrate 5 can be measured, or the impurity concentration of the semiconductor substrate 5 can be selectively etched in a small area. Can be monitored by.

Further, although the above-described embodiments are described as the etching process of the silicon semiconductor or the etching process of the SiO ₂ film provided on the silicon substrate, the process is limited to the manufacturing process of such a semiconductor device. However, it is applied to an insulating substrate such as sapphire or an etching process of a ferroelectric used for an optical IC.

[0057]

According to the present invention, when the substrate to be processed is solution-processed with a small amount of the processing solution by using the flat plate member, the structure of the flat plate member is devised or the vibration is applied to improve the processing accuracy. Can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a principle configuration of the present invention.

FIG. 2 is an explanatory diagram of a first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of a third embodiment of the present invention.

FIG. 5 is an explanatory diagram of a fourth embodiment of the present invention.

FIG. 6 is an explanatory diagram of a fifth embodiment of the present invention.

FIG. 7 is an explanatory diagram of a sixth embodiment of the present invention.

FIG. 8 is an explanatory diagram of a conventional solution processing step.

[Explanation of symbols]

1 Processing Base 2 Processing Substrate 3 Processing Liquid 4 Flat Plate Member 5 Semiconductor Substrate 6 Etching Liquid 7 Ceramics Substrate 8 Vibration Oscillator 9 Warped Ceramics Substrate 10 Groove 11 SiO ₂ Film 12 Transparent Substrate 13 Micro Ceramics Substrate

Claims (9)

[Claims] 1. A method of manufacturing a semiconductor device in which a substrate to be processed is solution-processed using a flat plate member, when a processing liquid is sandwiched between the plate member and the substrate to be processed, the substrate to be processed is processed. A method of manufacturing a semiconductor device, wherein the processing speed is controlled by the weight of the flat plate member. 2. A method of manufacturing a semiconductor device in which a substrate to be processed is solution-processed using a flat plate member, when a processing liquid is sandwiched between the flat plate member and the substrate to be processed, the substrate to be processed is processed. A method of manufacturing a semiconductor device, characterized in that vibration is applied to the substrate to be processed. 3. A method of manufacturing a semiconductor device in which a substrate to be processed is solution-processed using a flat plate member, the processing liquid is sandwiched between the flat plate member and the substrate to be processed, and the substrate to be processed is processed, A method of manufacturing a semiconductor device, wherein a surface of the flat plate member facing the substrate to be processed is made convex. 4. A method of manufacturing a semiconductor device in which a substrate to be processed is solution-processed using a flat plate member, and a processing liquid is sandwiched between the flat plate member and the substrate to be processed, and the substrate to be processed is processed. A method of manufacturing a semiconductor device, wherein radial grooves are provided on a surface of the flat plate member facing the substrate to be processed. 5. A method of manufacturing a semiconductor device in which a substrate to be processed is solution-processed using a flat plate member, the processing liquid is sandwiched between the flat plate member and the substrate to be processed, and the target substrate is processed. A method of manufacturing a semiconductor device, wherein the flat plate member is formed of a transparent member. 6. A method of manufacturing a semiconductor device, in which a substrate to be processed is solution-processed using a flat plate member, when a processing liquid is sandwiched between the flat plate member and the substrate to be processed, the substrate to be processed is processed. A method of manufacturing a semiconductor device, wherein the size of the flat plate member is smaller than the size of the substrate to be processed, and a partial region of the substrate to be processed is selectively processed. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the solution treatment is a cleaning treatment. 8. The method of manufacturing a semiconductor device according to claim 1, wherein the solution treatment is etching treatment. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the etching process is an etching process for evaluating a substrate to be processed.