JPH08316158A - Semiconductor wafer boat - Google Patents

Semiconductor wafer boat

Info

Publication number
JPH08316158A
JPH08316158A JP13735895A JP13735895A JPH08316158A JP H08316158 A JPH08316158 A JP H08316158A JP 13735895 A JP13735895 A JP 13735895A JP 13735895 A JP13735895 A JP 13735895A JP H08316158 A JPH08316158 A JP H08316158A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
semiconductor
wafer
wafer boat
support plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13735895A
Other languages
Japanese (ja)
Inventor
Yasushi Nishimoto
康 西本
Norio Masuda
則雄 益田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Coorstek KK
Original Assignee
Toshiba Ceramics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Ceramics Co Ltd filed Critical Toshiba Ceramics Co Ltd
Priority to JP13735895A priority Critical patent/JPH08316158A/en
Publication of JPH08316158A publication Critical patent/JPH08316158A/en
Pending legal-status Critical Current

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  • Packaging Frangible Articles (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE: To provide a semiconductor wafer boat, wherein dummy wafers, whose thicknesses become thicker stepwise toward upper and lower supporting plates, are mounted on both upper and lower side parts of the semiconductor wafer boat so that the drastic temperature change does not affect the semiconductor wafer. CONSTITUTION: In a semiconductor wafer boat 40 in which semiconductor wafers to be heat-treated are placed, an upper supporting plate 41 and a lower supporting plate 42 and a plurality of supporting posts 43, whose upper and lower end parts are fixed to the upper supporting plate 41 and the lower supporting plate 42 by a means such as welding, adhesion or the like, are provided. Then, the following parts are contained at the intermediate parts of the supporting posts 43. Semiconductor-wafer inserting grooves 44 are formed at regular intervals for placing the semiconductor wafers 1. Dummy-wafer inserting grooves 45 and 46 are formed so that each groove width becomes wider stepwise from both end part of the semiconductor-wafer inserting groove 44 toward the upper supporting plate 41 and the lower supporting plate 42 at both upper and lower end parts of the supporting post 43.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体ウエ−ハの熱処理
工程において用いられる半導体ウエ−ハボートに関し、
特に多数の半導体ウエ−ハを熱処理炉内で均一に処理す
るための半導体ウエ−ハボートに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer boat used in a heat treatment process of a semiconductor wafer,
In particular, the present invention relates to a semiconductor wafer boat for uniformly processing a large number of semiconductor wafers in a heat treatment furnace.

【0002】[0002]

【従来の技術】半導体ウエ−ハの製造では、酸化・拡散
・等の処理のために半導体ウエ−ハの熱処理が行われて
いる。この半導体ウエ−ハの熱処理は、まず石英あるい
は炭化珪素等からなる半導体ウエ−ハボートに等間隔に
形成された半導体ウェ−ハ挿入溝に半導体ウエ−ハを載
置し、この半導体ウエ−ハボートを縦型または横型の熱
処理炉内に投入するとともに、熱処理炉内に設置された
燃焼装置に燃料ガス(例えば、水素ガス)および酸素ガ
スを外部より供給して燃焼せしめ、それによって発生し
た燃焼ガス(例えば水蒸気)を前記半導体ウエ−ハに供
給することにより行なわれる。
2. Description of the Related Art In the manufacture of semiconductor wafers, heat treatment of semiconductor wafers is carried out for treatments such as oxidation and diffusion. In the heat treatment of this semiconductor wafer, first, the semiconductor wafer is placed in the semiconductor wafer insertion grooves formed at equal intervals in the semiconductor wafer boat made of quartz or silicon carbide, and the semiconductor wafer boat is mounted. The fuel gas (for example, hydrogen gas) and oxygen gas are supplied from the outside to a combustion apparatus installed in the vertical or horizontal heat treatment furnace to burn them, and the combustion gas generated thereby ( For example, water vapor is supplied to the semiconductor wafer.

【0003】ところで、半導体ウエ−ハの厚さは約60
0μmと非常に薄く、しかもその熱容量は小さい。その
ため、半導体ウエ−ハボートの半導体ウェ−ハ挿入溝に
半導体ウエ−ハを載置して、炉への出入れを行うと、炉
入れ・炉出し時における急激な温度変化が、半導体ウエ
−ハボートに載置された半導体ウエ−ハ、特に半導体ウ
エ−ハボートの上下両端部の半導体ウエ−ハに生じ、こ
れに起因して半導体ウエ−ハに割れやスリップが発生し
て製品の歩留まりが低下することがあった。
By the way, the thickness of the semiconductor wafer is about 60.
It is as thin as 0 μm and its heat capacity is small. Therefore, when the semiconductor wafer is placed in the semiconductor wafer insertion groove of the semiconductor wafer boat and is put in and out of the furnace, a sudden temperature change at the time of putting in and out of the furnace causes a semiconductor wafer boat. Occurs on the semiconductor wafer placed on the semiconductor wafer, especially on the semiconductor wafers at the upper and lower ends of the semiconductor wafer boat, and as a result, the semiconductor wafer is cracked or slips to reduce the yield of products. There was an occasion.

【0004】そこで、近年では上述した課題を改善する
ために、図3に示すように、上方支持プレート51、下
方支持プレート52、および複数本の支柱53とからな
る半導体ウエ−ハボート50の中間部に熱処理を行う多
数の半導体ウエ−ハ55を等間隔に載置するとともに、
前記半導体ウエ−ハボ−ト50の両端部(上方端部側、
下方端部)に前記半導体ウエ−ハ55と同一材料、同一
形状寸法を有するいわゆるダミーウエ−ハ56を数枚〜
数十枚載置して、熱処理が行なわれている。即ち、半導
体ウエ−ハボート50の両端部に生じる急激な温度変化
が中間部に載置された半導体ウエ−ハ55に直接影響し
ないようにし、半導体ウエ−ハ55の割れやスリップの
発生を防止しようとするものである。
Therefore, in recent years, in order to improve the above-mentioned problems, as shown in FIG. 3, an intermediate portion of a semiconductor wafer boat 50 including an upper support plate 51, a lower support plate 52, and a plurality of columns 53. A large number of semiconductor wafers 55 to be heat treated are placed at equal intervals, and
Both ends of the semiconductor wafer board 50 (upper end side,
Several sheets of so-called dummy wafers 56 having the same material and the same shape and dimensions as those of the semiconductor wafer 55 are provided at the lower end portion.
Dozens of them are placed and heat treatment is performed. That is, abrupt temperature changes occurring at both ends of the semiconductor wafer boat 50 are prevented from directly affecting the semiconductor wafer 55 placed in the middle portion, and cracks and slips of the semiconductor wafer 55 are prevented. It is what

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上述し
たように半導体ウエ−ハボ−トの両端部にダミーウエ−
ハを載置して急激な温度変化が作用しないようにした場
合であっても、前記ダミーウエ−ハは半導体ウエ−ハと
同一材料、同一形状寸法であるため、半導体ウエ−ハと
同様に熱容量が小く、急激な温度変化が中間部に配置さ
れた半導体ウエ−ハの両端部(上端部、下端部)に位置
する半導体ウエ−ハに影響を与え、前記半導体ウエ−ハ
に割れやスリップが生じることがあった。
However, as described above, dummy wafers are formed on both ends of the semiconductor wafer.
Even when the wafer is placed so that a sudden temperature change does not act, since the dummy wafer is made of the same material and has the same shape and dimension as the semiconductor wafer, the dummy wafer has the same heat capacity as the semiconductor wafer. Small, abrupt temperature changes affect the semiconductor wafers located at both ends (upper end and lower end) of the semiconductor wafer arranged in the middle part, and the semiconductor wafer is cracked or slips. May occur.

【0006】これを解決するためには、ダミーウエ−ハ
を相当枚数を載置し、半導体ウエ−ハボートの炉入れ・
炉出し時における急激な温度変化が半導体ウエ−ハに影
響を与えないようにすれば良いが、相当枚数のダミーウ
エ−ハを半導体ウエ−ハボートに載置すると、半導体ウ
エ−ハの熱処理枚数が大幅に制限され、生産性が大幅に
低下するという課題があった。
In order to solve this, a considerable number of dummy wafers are placed, and the semiconductor wafer boat is put in a furnace.
It is sufficient to prevent the sudden temperature change during the furnace removal from affecting the semiconductor wafer.However, if a considerable number of dummy wafers are placed on the semiconductor wafer boat, the number of heat-treated semiconductor wafers will be significantly increased. However, there was a problem that productivity was drastically reduced.

【0007】本発明は、上述した技術的課題を解決する
ためになされたものであり、半導体ウエ−ハボートの上
下両側部に、上下方支持プレ−トに向って段階的に厚さ
が厚くなるダミーウエ−ハを載置して急激な温度変化が
前記半導体ウエ−ハに影響しないようにした半導体ウエ
−ハボートを提供することを目的とするものである。
The present invention has been made in order to solve the above-mentioned technical problems, and the thickness of the semiconductor wafer boat is gradually increased toward the upper and lower support plates on both upper and lower sides thereof. An object of the present invention is to provide a semiconductor wafer boat on which a dummy wafer is placed so that a sudden temperature change does not affect the semiconductor wafer.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に、本発明による半導体ウエ−ハボートは、熱処理がな
される半導体ウエ−ハを載置する半導体ウエ−ハボート
において、上方支持プレートおよび下方支持プレート
と、前記上方支持プレートおよび下方支持プレートに上
下端部が溶着、接着等の手段によって一体的に固着され
た複数の支柱と、前記支柱の中間部に半導体ウエ−ハを
載置するために等間隔に形成された半導体ウエ−ハ挿入
溝と、前記支柱の上下両側部において前記半導体ウエ−
ハ挿入溝の両端部から半導体ウエ−ハボートの上方支持
プレートおよび下方支持プレートに向かって溝幅が段階
的に広くなるように形成されたダミーウエ−ハ挿入溝と
を含むことを特徴とする。
In order to achieve the above object, a semiconductor wafer boat according to the present invention is provided with an upper support plate and a lower support in a semiconductor wafer boat on which a semiconductor wafer to be heat treated is placed. A plate, a plurality of support posts whose upper and lower end portions are integrally fixed to the upper support plate and the lower support plate by means of welding, adhesion, etc., and for mounting a semiconductor wafer on an intermediate portion of the support columns. The semiconductor wafer insertion grooves formed at equal intervals, and the semiconductor wafer at the upper and lower sides of the pillar.
The dummy wafer insertion groove is formed so that the groove width is gradually increased from both ends of the wafer insertion groove toward the upper support plate and the lower support plate of the semiconductor wafer boat.

【0009】[0009]

【作用】このような構成によって、本発明にかかる半導
体ウエ−ハボートでは、熱処理がなされる半導体ウエ−
ハを半導体ウエ−ハボートの中間部に載置すると共に、
載置した前記半導体ウエ−ハ両端部から半導体ウエ−ハ
ボートの上方支持プレートおよび下方支持プレートに向
かって段階的に幅広になるよう形成された溝に、段階的
に厚さが厚くなるダミーウエ−ハを載置したため、半導
体ウエ−ハボートの両端部(上下方支持プレ−ト)に近
いほどダミーウエ−ハの熱容量が大きくすることができ
る。
With such a structure, in the semiconductor wafer boat according to the present invention, the semiconductor wafer to be heat-treated
Place the ha in the middle of the semiconductor wafer boat,
A dummy wafer whose thickness gradually increases in a groove formed so as to gradually widen from the both ends of the mounted semiconductor wafer toward the upper support plate and the lower support plate of the semiconductor wafer boat. Since the semiconductor wafer is mounted, the heat capacity of the dummy wafer can be increased as it is closer to both ends (upper and lower support plates) of the semiconductor wafer boat.

【0010】したがって、半導体ウエ−ハを熱処理する
際、半導体ウエ−ハボートの炉入れ・炉出し時における
急激な温度変化が半導体ウエ−ハボートの中間部に載置
した半導体ウエ−ハに直接影響せず、なだらかな温度勾
配で加熱・冷却されるため、半導体ウエ−ハの温度変化
が均一化され、割れやスリップの発生を防止することが
できる。
Therefore, when heat-treating a semiconductor wafer, a rapid temperature change during the loading and unloading of the semiconductor wafer boat directly affects the semiconductor wafer mounted in the middle part of the semiconductor wafer boat. Instead, the semiconductor wafer is heated and cooled with a gentle temperature gradient, so that the temperature change of the semiconductor wafer is made uniform and cracks and slips can be prevented from occurring.

【0011】[0011]

【実施例】以下本発明の実施例を図面に基づいて詳細に
説明する。図1は、本発明に係る半導体ウエ−ハボート
を示す正面図、図2は半導体ウエ−ハを熱処理する縦型
熱処理炉の構成を示す縦断面図である。
Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a front view showing a semiconductor wafer boat according to the present invention, and FIG. 2 is a vertical sectional view showing the structure of a vertical heat treatment furnace for heat-treating a semiconductor wafer.

【0012】図において、縦型熱処理炉20は、例えば
特開平2−273918号公報に示されるように、熱処
理が施される多数の半導体ウエ−ハ1を同時に処理する
ための炉芯管装置21と、前記炉芯管装置21の周囲に
適宜の間隔を保持して均熱領域を確保するために配設さ
れた均熱管22と、前記均熱管22の周囲に配設された
加熱部材23と、前記加熱部材23の周囲に配設された
断熱管24と、前記炉芯管装置21を保持するためのハ
ウジング25と、前記炉芯管装置21の包有された炉芯
管本体21aの開口端部に対して直接に当接される炉蓋
本体26aを有する炉蓋26とを備えている。
In the figure, a vertical heat treatment furnace 20 has a furnace core tube device 21 for simultaneously processing a large number of semiconductor wafers 1 to be heat-treated, as shown in, for example, Japanese Unexamined Patent Publication No. 2-273918. A soaking tube 22 arranged to maintain an appropriate space around the furnace core tube device 21 to secure a soaking area, and a heating member 23 arranged around the soaking tube 22. An adiabatic pipe 24 arranged around the heating member 23, a housing 25 for holding the furnace core tube device 21, and an opening of the furnace core tube body 21a in which the furnace core tube device 21 is included. And a furnace lid 26 having a furnace lid body 26a that directly abuts against the end portion.

【0013】上記炉芯管装置21には、内部空間に形成
された均熱領域で半導体ウエ−ハ1を熱処理するための
炉芯管本体21aと、内部に水素などの燃料ガスおよび
酸素ガスをそれぞれ供給するためのガス供給管27a、
27bと、燃料ガスを燃焼せしめて燃焼ガスを発生する
ための燃焼装置28と、燃焼装置28で発生された燃焼
ガスを半導体ウエ−ハの処理ガスとして炉芯管本体21
aの頂部より内部空間に向けて供給するための燃焼ガス
供給管29と、使用済の燃焼ガスを外部へ排出するため
のガス排出管30とを備えている。
In the furnace core tube device 21, a furnace core tube main body 21a for heat-treating the semiconductor wafer 1 in a soaking region formed in the internal space, and a fuel gas such as hydrogen and an oxygen gas are internally provided. A gas supply pipe 27a for supplying each,
27b, a combustor 28 for combusting a fuel gas to generate a combustion gas, and the combustion gas generated by the combustor 28 as a processing gas for a semiconductor wafer.
A combustion gas supply pipe 29 for supplying the internal space from the top of a and a gas discharge pipe 30 for discharging the used combustion gas to the outside are provided.

【0014】また、上記炉芯管本体21a内における炉
蓋本体26aの上面には、保温筒31が配設されてお
り、この保温筒31の上面に熱処理が施される多数の半
導体ウエ−ハ1を載置した半導体ウエ−ハボート40が
設置されるようになっている。そして、前記保温筒31
上に設置された半導体ウエ−ハボート40が、駆動装置
(図示せず)から駆動部材33を介して炉蓋移動部材と
一体に移動して、炉入れ・炉出しが行われることによ
り、多数の半導体ウエ−ハ1が炉芯管装置21内で熱処
理されるように構成されている。
A heat insulating cylinder 31 is arranged on the upper surface of the furnace lid main body 26a in the furnace core tube main body 21a, and a large number of semiconductor wafers to be heat-treated on the upper surface of the heat insulating cylinder 31 are provided. A semiconductor wafer boat 40 on which 1 is mounted is installed. Then, the heat retaining cylinder 31
The semiconductor wafer boat 40 installed above moves integrally from the driving device (not shown) through the driving member 33 with the furnace lid moving member to carry out furnace loading / unloading, and The semiconductor wafer 1 is configured to be heat-treated in the furnace core tube device 21.

【0015】次に、前記半導体ウエ−ハボート40につ
いて、図1に基づいて詳述する。図に示すように、前記
半導体ウエ−ハボート40は石英あるいは炭化珪素から
なり、上方支持プレート41、下方支持プレート42、
および複数本の支柱43とによって構成されている。前
記上方支持プレート41および下方支持プレート42に
は、ウエ−ハ挿入側の片側半分を除いた半円側(180
度に相当する)に等間隔に配置された支柱43の上下端
部が溶着、接着等の手段によって一体的に固着されてい
る。そして、前記複数本の支柱43の中間部には、熱処
理を行う半導体ウエ−ハ1が水平状態に載置するための
ウエ−ハ挿入溝44が上下方向に等間隔に、多数形成さ
れている。
Next, the semiconductor wafer boat 40 will be described in detail with reference to FIG. As shown in the figure, the semiconductor wafer boat 40 is made of quartz or silicon carbide, and has an upper support plate 41, a lower support plate 42,
And a plurality of columns 43. The upper support plate 41 and the lower support plate 42 have semi-circular sides (180
The upper and lower ends of the columns 43 arranged at equal intervals (corresponding to the degree) are integrally fixed by means such as welding or adhesion. A plurality of wafer insertion grooves 44 for horizontally mounting the semiconductor wafer 1 to be heat-treated are formed at equal intervals in the vertical direction on the intermediate portion of the plurality of columns 43. .

【0016】また、前記ウエ−ハ挿入溝44の上下両端
部より支柱43の上下両端部(半導体ウエ−ハボート4
0の上下方支持プレ−ト41、42)に向かって段階的
に溝幅が広くなるダミーウエ−ハ挿入溝45-1、45-2
・・・45-nおよび46-1、46-2・・・46-nが等間
隔に、複数個形成されている。このダミーウエ−ハ挿入
溝45-1、45-2・・・45-nおよび46-1、46-2
・・46-nは、熱処理を行う半導体ウエ−ハと同一厚さ
から段階的に厚さが厚くなるダミーウエ−ハ2-1、2-2
・・・2-nを水平状態に載置するためのものである。
尚、ダミーウエ−ハ挿入溝45-1と46-1、45-2と4
-2、・・・45-nと46-nとは同一の溝の幅を有し、
同一の厚さを有するダミーウエ−ハを載置できるように
なされている。
Further, from the upper and lower end portions of the wafer insertion groove 44 to the upper and lower end portions of the support column 43 (semiconductor wafer boat 4
0 of the upper and lower side supporting pre - Damiue stepwise groove width toward the bets 41, 42) widens - Ha insertion groove 45 -1, 45 -2
... 45 -n and 46 -1 , 46 -2 ... 46 -n are formed at equal intervals. The Damiue - Ha insertion groove 45 -1, 45 -2 ··· 45 -n and 46 -1, 46 -2 ·
.. 46 -n are dummy wafers 2 -1 , 2 -2 whose thickness gradually increases from the same thickness as the semiconductor wafer to be heat-treated
... for mounting 2 -n in a horizontal state.
In addition, dummy wafer insertion grooves 45 -1 and 46 -1 , 45 -2 and 4
6 -2 , ... 45 -n and 46 -n have the same groove width,
A dummy wafer having the same thickness can be placed.

【0017】次に、直径6インチ、厚さ600μmの半
導体ウエ−ハを用いて、熱処理するした場合のスリップ
の発生について説明する。まず、実施例として、半導体
ウエ−ハボート40の中間部には、溝幅700μm、溝
ピッチ5mm間隔で形成されたウエ−ハ挿入溝44に半
導体ウエ−ハを100枚を水平状態に載置する。
Next, the occurrence of slip when heat-treated using a semiconductor wafer having a diameter of 6 inches and a thickness of 600 μm will be described. First, as an example, 100 semiconductor wafers are placed horizontally in a wafer insertion groove 44 formed with a groove width of 700 μm and a groove pitch of 5 mm at an intermediate portion of the semiconductor wafer boat 40. .

【0018】また、半導体ウエ−ハボート40のダミー
ウエ−ハ挿入溝45-1、45-2・・・45-nおよび46
-1、46-2・・・46-nの溝幅は半導体ウエ−ハ挿入溝
44の端部から上下方支持プレ−ト41、42に向かっ
てそれぞれ700μm、800μm・・・1600μm
と100μmずつ広くなるように形成し、このダミーウ
エ−ハ挿入溝45-1、45-2・・・45-10 および46
-1、46-2・・・46-10 に厚さが600μm、700
μm・・・1500μmと100μmずつ段階的に厚く
なる10枚のダミーウエ−ハ2-1、2-2・・・2-10
を、載置した。この関係を示すと次の表1のようにな
る。
Further, the semiconductor weather - Damiue of Haboto 40 - Ha insertion groove 45 -1, 45 -2 ··· 45 -n and 46
-1 , 46 -2 ... 46 -n have groove widths of 700 μm, 800 μm ... 1600 μm from the end of the semiconductor wafer insertion groove 44 toward the upper and lower support plates 41, 42, respectively.
And the dummy wafer insertion grooves 45 -1 , 45 -2 ... 45 -10 and 46.
-1 , 46 -2 ... 46 -10 with a thickness of 600 μm, 700
10 dummy wafers 2 −1 , 2 -2・ ・ ・ 2 -10 , which gradually increase in thickness by 100 μm and 1500 μm
Was placed. This relationship is shown in Table 1 below.

【0019】[0019]

【表1】 [Table 1]

【0020】上記表1から明らかなように、ダミーウエ
−ハ2は炉芯管本体21aの炉奥側(上方支持プレ−ト
側)から順次厚さが薄くなり、10枚目のダミーウエ−
ハ2は半導体ウエ−ハ1と同一厚さとなり、続いて半導
体ウエ−ハ1を100枚載置した後、ダミーウエ−ハ2
は炉芯管本体21aの炉口側(下支持プレ−ト側)へ順
次厚さが厚くなるようになされている。
As is clear from Table 1, the thickness of the dummy wafer 2 is gradually reduced from the furnace inner side (upper support plate side) of the furnace core tube body 21a, and the tenth dummy wafer 2 is obtained.
The wafer 2 has the same thickness as the semiconductor wafer 1, and subsequently 100 semiconductor wafers 1 are placed, and then the dummy wafer 2
The thickness is gradually increased toward the furnace port side (lower support plate side) of the furnace core body 21a.

【0021】そして、炉入れ温度は800。C、炉入れ
速度は5cm/分とし、炉出し温度は800。C、炉出
し速度は2cm/分として、熱処理温度1150。Cで
2時間の熱処理を行った。
The furnace temperature is 800. C, the furnace introduction speed is 5 cm / min, and the furnace discharge temperature is 800. C, the furnace removal rate is 2 cm / min, and the heat treatment temperature is 1150. Heat treatment was performed for 2 hours at C.

【0022】また、比較例として半導体ウェ−ハ1と同
一形状寸法(直径6インチ、厚さ600μm)のダミー
ウエ−ハ2を上下側部にそれぞれ10枚載置し、実施例
と同様半導体ウエ−ハ1を100枚載置し、同一の熱処
理条件で熱処理を行った。その結果を表2に示す。尚、
下記表では、半導体ウェ−ハを上方支持プレ−ト側から
1枚目、2枚目…100枚目として、それぞれの半導体
ウェ−ハに発生したスリップの長さを表示し、またスリ
ップの発生が認められなかった場合には「なし」と表示
した。
As a comparative example, ten dummy wafers 2 having the same shape and dimensions (diameter 6 inches, thickness 600 μm) as the semiconductor wafer 1 are placed on the upper and lower sides, respectively, and the semiconductor wafer is the same as the embodiment. 100 pieces of C1 were placed and heat-treated under the same heat-treatment conditions. The results are shown in Table 2. still,
In the table below, the semiconductor wafers are shown as the first, second, and 100th semiconductor wafers from the upper support plate side, and the lengths of the slips generated in the respective semiconductor wafers are displayed and the occurrence of the slips is also shown. When no was observed, it was displayed as “none”.

【0023】[0023]

【表2】 [Table 2]

【0024】上記表2に示すように、本実施例にあって
は、半導体ウエ−ハ1の両端部に割れやスリップの発生
が全くみられなかった。これに対して、比較例では上下
方支持プレ−トに近接した3〜4枚の半導体ウエ−ハ1
にスリップの発生が認められた。即ち、実施例にあって
は半導体ウエ−ハボート40の炉内投入時に、炉奥側
(上方支持プレ−ト側)の熱容量の大きいダミーウエ−
ハ2から熱せられるため、半導体ウエ−ハボート内40
での半導体ウエ−ハ1の温度変化がより均一かされ、半
導体ウエ−ハ1自身の急激な温度上昇を防止することが
できる。
As shown in Table 2 above, in this embodiment, neither cracks nor slips were found at both ends of the semiconductor wafer 1. On the other hand, in the comparative example, three to four semiconductor wafers 1 close to the upper and lower support plates are used.
Occurrence of slip was observed in the. That is, in the embodiment, when the semiconductor wafer boat 40 is charged into the furnace, a dummy wafer having a large heat capacity on the furnace back side (upper support plate side).
Since it is heated by the wafer 2, the inside of the semiconductor wafer boat 40
The temperature change of the semiconductor wafer 1 can be made more uniform, and a rapid temperature rise of the semiconductor wafer 1 itself can be prevented.

【0025】また、炉出し時には、より厚さのあるダミ
ーウエ−ハ2から冷却が始まるが、ダミーウエ−ハ2の
熱容量が段階的に変化するために、半導体ウエ−ハボー
ト40内での半導体ウエ−ハ1の冷却温度の均一化が図
られ、半導体ウエ−ハの急冷却を防止することができ
る。よって、半導体ウエ−ハ1の急激な温度変化を防止
することができ、これに起因する割れやスリップを防止
することが可能になる。
Further, at the time of unloading the furnace, cooling starts from the thicker dummy wafer 2, but since the heat capacity of the dummy wafer 2 changes stepwise, the semiconductor wafer in the semiconductor wafer boat 40 is changed. The cooling temperature of the wafer 1 can be made uniform, and rapid cooling of the semiconductor wafer can be prevented. Therefore, it is possible to prevent a rapid temperature change of the semiconductor wafer 1, and it is possible to prevent cracks and slips due to this.

【0026】尚、本発明による実施例において、ダミー
ウエ−ハの厚さ、厚さ変化量および使用枚数、ダミーウ
エ−ハの載置間隔等は、熱処理が施される半導体ウエ−
ハや半導体ウエ−ハボートの炉入れ・炉出し時の温度等
により変化するものであり、半導体ウエ−ハによって適
正な熱処理条件に設定することができる。また、本発明
の実施例では、半導体ウエ−ハの大口径化に伴い、直径
が6インチ以上の半導体ウエ−ハを熱処理するための縦型
熱処理炉を使用した場合について説明したが、特にこれ
に限定するものではなく、直径が6インチ 以下の半導体ウ
エ−ハを熱処理する横型熱処理炉にも適用することがで
きる。
In the embodiment according to the present invention, the thickness of the dummy wafer, the amount of change in thickness, the number of used wafers, the mounting interval of the dummy wafers, etc. are set to the semiconductor wafer to be heat-treated.
It depends on the temperature of the wafer and the semiconductor wafer boat when the boat is put in and out of the furnace, and the heat treatment conditions can be set appropriately depending on the semiconductor wafer. Further, in the embodiment of the present invention, the case of using the vertical heat treatment furnace for heat-treating a semiconductor wafer having a diameter of 6 inches or more has been described with the increase in diameter of the semiconductor wafer. However, the present invention can be applied to a horizontal heat treatment furnace for heat treating a semiconductor wafer having a diameter of 6 inches or less.

【0027】[0027]

【発明の効果】以上詳細に説明したように、本発明によ
る半導体ウエ−ハボートは、上方支持プレートおよび下
方支持プレートに上下端部が溶着、接着等の手段によっ
て一体的に固着された支柱の中間部に半導体ウエ−ハを
載置するために半導体ウエ−ハ挿入溝が等間隔に形成さ
れ、また前記支柱の上下両側部において前記半導体ウエ
−ハ挿入溝の両端部から半導体ウエ−ハボートの上方支
持プレートおよび下方支持プレートに向かって溝幅が段
階的に広くなるようにダミーウエ−ハ挿入溝が形成さ
れ、前記ダミーウエ−ハ挿入溝に段階的に厚さが厚くな
るダミーウエ−ハを載置したため、上下方支持プレ−ト
に近づくほどダミーウエ−ハの熱容量が大きく、また熱
処理を施す半導体ウエ−ハの両端部に近づくほど熱容量
を小さくすることができる。
As described above in detail, in the semiconductor wafer boat according to the present invention, the upper and lower end portions of the upper and lower support plates are integrally fixed to each other by means of welding, bonding, etc. Semiconductor wafer insertion grooves are formed at equal intervals for mounting the semiconductor wafer on the upper part, and the upper and lower sides of the semiconductor wafer insertion groove are located above and below the semiconductor wafer insertion groove on both upper and lower sides of the pillar. The dummy wafer insertion groove is formed so that the groove width gradually increases toward the support plate and the lower support plate, and the dummy wafer whose thickness gradually increases is placed in the dummy wafer insertion groove. The heat capacity of the dummy wafer may be increased as it gets closer to the upper and lower support plates, and the heat capacity may be made smaller as it gets closer to both ends of the semiconductor wafer to be heat-treated. Kill.

【0028】したがって、本発明にかかる半導体ウエ−
ハボートでは、ウエ−ハボートの炉入れ・炉出し時にお
ける急激な温度変化が半導体ウエ−ハに直接影響せず、
半導体ウエ−ハはなだらかな温度勾配で加熱・冷却され
るため、熱処理を施す半導体ウエ−ハの温度変化が均一
化され、割れやスリップの発生を防止することができる
という効果を奏するものである。
Therefore, the semiconductor wafer according to the present invention
In the boat, the rapid temperature change during the loading and unloading of the wafer boat does not directly affect the semiconductor wafer,
Since the semiconductor wafer is heated / cooled with a gentle temperature gradient, the temperature change of the semiconductor wafer subjected to the heat treatment is made uniform, and it is possible to prevent the occurrence of cracks and slips. .

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体ウエ−ハボートを示す正面
図である。
FIG. 1 is a front view showing a semiconductor wafer boat according to the present invention.

【図2】半導体ウエ−ハを熱処理する縦型熱処理炉の構
成を示す縦断面図である。
FIG. 2 is a vertical cross-sectional view showing the configuration of a vertical heat treatment furnace for heat-treating a semiconductor wafer.

【図3】従来構造の半導体ウエ−ハボートを示す正面図
である。
FIG. 3 is a front view showing a semiconductor wafer boat having a conventional structure.

【符号の説明】[Explanation of symbols]

1 半導体ウエ−ハ 20 縦型熱処理炉 21 炉芯管装置 40 半導体ウエ−ハボート 41 上方支持プレート 42 下方支持プレート 43 支柱 44 ウエ−ハ挿入溝 45-n ダミーウエ−ハ挿入溝 46-n ダミーウエ−ハ挿入溝 1 Semiconductor Wafer 20 Vertical Heat Treatment Furnace 21 Furnace Core Tube Device 40 Semiconductor Wafer Boat 41 Upper Support Plate 42 Lower Support Plate 43 Strut 44 Wafer Insertion Groove 45-n Dummy Wafer Insertion Groove 46-n Dummy Wafer Insertion groove

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 熱処理がなされる半導体ウエ−ハを載置
する半導体ウエ−ハボートにおいて、 上方支持プレートおよび下方支持プレートと、前記上方
支持プレートおよび下方支持プレートに上下端部が溶
着、接着等の手段によって一体的に固着された複数の支
柱と、前記支柱の中間部に半導体ウエ−ハを載置するた
めに等間隔に形成された半導体ウエ−ハ挿入溝と、前記
支柱の上下両側部において前記半導体ウエ−ハ挿入溝の
両端部から半導体ウエ−ハボートの上方支持プレートお
よび下方支持プレートに向かって溝幅が段階的に広くな
るように形成されたダミーウエ−ハ挿入溝とを含むこと
を特徴とする半導体ウエ−ハボート。
1. A semiconductor wafer boat on which a semiconductor wafer to be heat-treated is mounted, wherein an upper support plate and a lower support plate and upper and lower end portions of the upper support plate and the lower support plate are welded or bonded. A plurality of stanchions integrally fixed by means, semiconductor wafer insertion grooves formed at equal intervals for mounting a semiconductor wafer in the middle of the stanchions, and upper and lower sides of the stanchion. A dummy wafer insertion groove formed so that the groove width gradually increases from both ends of the semiconductor wafer insertion groove toward the upper support plate and the lower support plate of the semiconductor wafer boat. Semiconductor wafer boat.
JP13735895A 1995-05-11 1995-05-11 Semiconductor wafer boat Pending JPH08316158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13735895A JPH08316158A (en) 1995-05-11 1995-05-11 Semiconductor wafer boat

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13735895A JPH08316158A (en) 1995-05-11 1995-05-11 Semiconductor wafer boat

Publications (1)

Publication Number Publication Date
JPH08316158A true JPH08316158A (en) 1996-11-29

Family

ID=15196800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13735895A Pending JPH08316158A (en) 1995-05-11 1995-05-11 Semiconductor wafer boat

Country Status (1)

Country Link
JP (1) JPH08316158A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6276592B1 (en) 1998-11-30 2001-08-21 Sico Jena Gmbh Quarzschmelze Process for the production of a holding device for semiconductor disks and holding device produced by this process
US6464445B2 (en) * 2000-12-19 2002-10-15 Infineon Technologies Richmond, Lp System and method for improved throughput of semiconductor wafer processing
JP2006032386A (en) * 2004-07-12 2006-02-02 Hitachi Kokusai Electric Inc Thermal treatment equipment
KR100564545B1 (en) * 1999-03-11 2006-03-28 삼성전자주식회사 boat used in thin film deposition apparatus
JP2007134518A (en) * 2005-11-10 2007-05-31 Hitachi Kokusai Electric Inc Heat treatment apparatus
JP2013069985A (en) * 2011-09-26 2013-04-18 Fuji Electric Co Ltd Method of manufacturing semiconductor device
CN106030778A (en) * 2013-12-20 2016-10-12 山特森光伏Ag Wafer boat
CN113465393A (en) * 2021-05-31 2021-10-01 河北恒博新材料科技股份有限公司 Novel IGZO atmosphere preheats fritting furnace

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6276592B1 (en) 1998-11-30 2001-08-21 Sico Jena Gmbh Quarzschmelze Process for the production of a holding device for semiconductor disks and holding device produced by this process
KR100564545B1 (en) * 1999-03-11 2006-03-28 삼성전자주식회사 boat used in thin film deposition apparatus
US6464445B2 (en) * 2000-12-19 2002-10-15 Infineon Technologies Richmond, Lp System and method for improved throughput of semiconductor wafer processing
JP2006032386A (en) * 2004-07-12 2006-02-02 Hitachi Kokusai Electric Inc Thermal treatment equipment
JP4700300B2 (en) * 2004-07-12 2011-06-15 株式会社日立国際電気 Heat treatment equipment
JP2007134518A (en) * 2005-11-10 2007-05-31 Hitachi Kokusai Electric Inc Heat treatment apparatus
JP2013069985A (en) * 2011-09-26 2013-04-18 Fuji Electric Co Ltd Method of manufacturing semiconductor device
CN106030778A (en) * 2013-12-20 2016-10-12 山特森光伏Ag Wafer boat
CN113465393A (en) * 2021-05-31 2021-10-01 河北恒博新材料科技股份有限公司 Novel IGZO atmosphere preheats fritting furnace

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