JPH08315592A - Read only memory - Google Patents

Abstract

PURPOSE: To suppress fluctuation in the level of a bit line while preventing the access time from increasing even if the parasitic capacity is high by connecting the bit line with a constant current source. CONSTITUTION: When an N channel MOD transistor (NTR) constituting a memory cell 1 is selected, while being connected at one end thereof with a positive polarity power supply, by a word line WL, a current flows from a terminal 4 through a bit line BL into a constant current supply ISS. Consequently, the voltage drop across a load 3 is decreased and the output node Tout goes to H. When the NTR is selected, with one end thereof being opened, by the word line ML, the output node Tout goes to L. Since a constant current flows constantly from the memory cell 1 or a transistor Q1 into the bit line BL, the level of bit line BL does not fluctuate even if a different data is fed from the memory cell 1. Consequently, fast operation is realized even if the parasitic capacity of bit line BL is high.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory,
In particular, it relates to a read circuit of a read-only memory.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing the structure of a conventional read-only memory M4.

The read-only memory M4 is a memory cell 1
And word lines WL (i) and (i =
0, 1, ...), a bit line BL for transmitting read data from the memory cell 1, and a read circuit 14. The read circuit 14 includes a bit line load 2 and an N-type channel MO.
S-transistor Q1 "and load 3 of transistor Q1"
, A positive power source Vcc, and an output node Tout.

In the read-only memory M4, a voltage corresponding to the read content is generated in the load 2 of the bit line BL.
N-type channel MOS transistor, P-type channel MOS
The memory cell 1 can be configured by any of the transistors, and when an N-type channel MOS transistor is applied to the memory cell 1, the memory cell 1 can be formed, for example, as shown in FIG. ) Either of the states.

The state shown in FIG. 5A is a state in which one end of the N-type channel MOS transistor constituting the memory cell 1 is connected to the positive power source, and the memory cell 1 is shown in FIG.
When the memory cell 1 is selected by the word line WL (i) in the state shown in (1), a current starts flowing from the terminal 4. This current flows into the load 2 via the bit line BL and generates a counter electromotive force across the load 2. By setting the circuit constant so that this electromotive force becomes sufficiently larger than the threshold voltage of the transistor Q1 ″, the transistor Q1 ″ can be controlled to be in a strong conductive state. As a result, a current flows through the load 3 and the transistor Q1 ″, a large voltage drop occurs across the load 3, and the output node Tout becomes low level.

In the state shown in FIG. 5B, one end of the N-type channel MOS transistor forming the memory cell 1 is in the open state, and when the memory cell 1 is in the state shown in FIG. When the cell 1 is selected by the word line WL (i), current does not flow out from the terminal 4, and naturally, no counter electromotive force is generated across the load 2. Although depending on the configuration of the load 2, the level of the bit line BL becomes sufficiently low (eg, ground level),
It becomes lower than the threshold voltage of the transistor Q1 ″.
The transistor Q1 ″ becomes non-conductive or close thereto, and the output node Tout becomes High level.

The memory cell 1 may be in the state shown in FIG. 5 (3) instead of the state shown in FIG. 5 (2). That is, the memory cell 1 may have a combination of the state of FIG. 5A and the state of FIG. 5B, and the state of FIG. 5A and the state of FIG. You may make it combine with. Even if such a combination of states is taken, the function equivalent to the above can be realized.

In the read-only memory M4, P
When the memory cell 1 is constituted by the type channel MOS transistor, the state of FIG. 5 (4) may be combined with the state of FIG. 5 (5), and the state of FIG. 5 (4) may be combined with the state of FIG. 5 (6). It is also possible to take a combination with the above state, and in this case, the function equivalent to the above can be realized.

[0009]

In the conventional read-only memory M4, the bit line BL has a parasitic capacitance, and this parasitic capacitance is charged and discharged during the read operation. Therefore, according to the magnitude of the parasitic capacitance, Access time becomes longer. Further, since the parasitic capacitance of the bit line BL increases as the number of memory cells connected to the bit line BL increases, there is a problem that the access time remarkably increases especially in a large capacity memory.

Further, in the above-mentioned conventional example, there are two current paths, that is, a current path from the memory cell 1 to the ground via the load 2 and a current path from the load 3 to the ground directly via the transistor Q1 ". However, there is a problem that the power consumption is large.

Further, when the current flows from the memory cell 1 to the ground, the read circuit 14 outputs a low level and the through current increases, and conversely, when the current does not flow from the memory cell 1 to the ground, Since the read circuit 14 outputs the high level and the through current decreases, there is a problem that the power consumption greatly changes depending on the stored content of the memory cell 1.

It is an object of the present invention to provide a read-only memory which has high speed and low power consumption.

[0013]

According to the present invention, a MOS transistor, a load connected between the drain of the MOS transistor and a power supply, and a source connected between the MOS transistor and ground are connected. A read circuit is configured by the constant current source, and a bit line for transmitting a read signal from the memory cell is connected to a connection point between the source of the MOS transistor and the constant current source.

[0014]

According to the present invention, since the bit line is connected to the input or output terminal of the constant current source, the level variation of the bit line is reduced and the access time is not lengthened even if the parasitic capacitance is large. Since there is no load on the bit line, it is possible to prevent the generation of power consumption corresponding to the amount of current passing through the load on the bit line, and further, the current flowing from the memory cell to the ground and the current flowing from the MOS transistor to the ground. Since the current flows through the constant current source, even if the current flows from the memory cell to the ground, the current passing through the read circuit is always constant, and the power consumption does not change greatly depending on the stored contents. .

[0015]

1 is a circuit diagram showing a read-only memory M1 according to a first embodiment of the present invention.

This read-only memory M1 includes a memory cell 1, word lines WL (i) for transmitting a selection signal to a circuit node 5 of the memory cell 1, (i = 0, 1, ...) And a circuit of the memory cell 1. It has a bit line BL for transmitting data read from the node 4 and a read circuit 11.

The read circuit 11 includes an N-type channel MOS transistor Q1, a load 3 of the transistor Q1, a positive power source Vcc, a positive constant current source Iss, and an output node T.
have out and. The arrow in FIG. 1 indicates the direction of the current of the constant current source Iss, which flows from the power supply Vcc to the ground.

The gate electrode of the transistor Q1 has a constant reference voltage V _R so as to keep the transistor Q1 conductive.
It is connected to the. The constant current source Iss may be realized by a transistor operating in the saturation region, and
Instead of the transistor, a high resistance may be used to realize the constant current source Iss.

When an N-type channel MOS transistor is applied as the memory cell 1, for example, the state shown in FIG. 5 (1) or (2) is taken according to the stored contents. Instead of the state shown in FIG. 2B, the state shown in FIG. 3C may be adopted. Alternatively, a P-type channel MOS transistor may be used as the memory cell 1. In this case, for example, FIG.
Alternatively, the state shown in (5) is taken. Instead of the state shown in FIG. 5 (5), the state shown in FIG. 6 (6) may be adopted.

Next, the operation of the read-only memory M1 will be described.

The state shown in FIG. 5A is the N-type channel M.
When one end of the OS transistor is connected to the positive power supply Vcc and the memory cell 1 is in the state shown in FIG. 5A, the memory cell 1 is selected by the word line WL (i). Then, a current starts to flow from the terminal 4. This current flows into the constant current source Iss via the bit line BL, and in this case, the current flowing into the constant current source Iss is constant, so that the current passing through the load 3 and the transistor Q1 decreases. As a result, the voltage drop of the load 3 becomes small,
The output node Tout rises in level and outputs a high level.

The state shown in FIG. 5B is the N-type channel M.
When one end of the OS transistor is in the open state and the memory cell 1 is in the state shown in FIG. 5B, when the memory cell 1 is selected by the word line WL (i), current does not flow out from the terminal 4. It won't happen. In this case, all the current flowing into the constant current source Iss is the load 3 and the transistor Q.
Load 3 as it is supplied by the current passing through
A large voltage drop occurs in the load 3, and the output node Tout drops in level and outputs a low level.

By the way, in the read-only memory M1, the MO constituting the memory cell 1 or the read circuit 11 is formed.
A constant current is always supplied from the S transistor Q1 to the bit line B.
It flows into L. That is, even if the read data from the memory cell 1 is different, the level of the bit line BL does not change, so that the high speed operation can be performed even if the parasitic capacitance of the bit line BL becomes large. Further, in the read-only memory M1, the current flowing is constant (Iss) even if the read data changes, and the fluctuation in power consumption is small.

In the read-only memory M1,
The memory cell 1 may be in the states shown in FIGS. 5 (4) and 5 (5) instead of the states shown in FIGS. 5 (1) and 5 (2). The cell 1 can be realized by a P-type channel MOS transistor, and the same effect as the above can be obtained.

The memory cell 1 may have the state shown in FIG. 5 (3) instead of the state shown in FIG. 5 (2). Instead of the state shown in FIG. 5 (5). To
You may make it take the state shown in FIG.5 (6). Figure 5
Since one end of the memory cell 1 in the states shown in (3) and (6) is connected to the ground, when the memory cell having this structure is selected by the word line WL (i), it is changed from the bit line BL. Current flows into the memory cell 1,
This current is supplied to the power source V via the load 3 and the transistor Q1.
Since it is supplied from cc, a larger voltage drop is obtained across the load 3.

One end of the memory cell 1 in the state shown in FIGS. 5 (3) and (6) is connected to the ground, and when the memory cell 1 is selected by the word line WL (i), the bit line BL changes from the bit line BL. Although a current flows into the memory cell 1, a large amount of current does not flow as in the conventional example, so that the power consumption does not greatly vary depending on the stored contents.

The read circuit 11 includes a MOS transistor, a load connected between the drain of the MOS transistor and the power supply, and a constant current source connected between the source of the MOS transistor and the ground. It is an example of a read circuit including. In addition, the bit line BL is
It is an example of a bit line that connects the source of the MOS transistor and the connection point of the constant current source.

FIG. 2 is a circuit diagram showing a read-only memory M2 which is a second embodiment of the present invention.

The read-only memory M2 is a memory cell 1 '.
A word line WL (i) for transmitting a selection signal to the circuit node 5 of the memory cell 1 ', a bit line BL for transmitting read data from the memory cell 1', and a read circuit 12. The read circuit 12 has a P-type channel MOS transistor Q1 ′, a load 3 of the transistor Q1 ′, a negative power source −Vcc, a negative constant current source −Iss, and an output node Tout. The arrow in FIG. 2 indicates the direction of the constant current source -Iss, and a current flows from ground to -Vcc.

The transistor Q1 'gate electrodes of the transistors Q1' is connected to a constant reference voltage V _R 'to keep the conductive state.

The configuration of the memory cell 1'corresponds to the state of the memory cell 1 in the read-only memory M1 as shown in FIG.
It is shown in (1) to (6). The memory cell 1'can be realized by either a P-type channel MOS transistor or an N-type channel MOS transistor.

The operation of the read-only memory M2 is the same as that of the read-only memory M1 except for the direction of the current.

FIG. 3 is a circuit diagram showing a read-only memory M3 which is a third embodiment of the present invention.

This read-only memory M3 is different from the read-only memory M1 in that instead of supplying a fixed reference voltage V _R to the gate electrode of the transistor Q1, an additional circuit 20 is provided.
Is provided.

The additional circuit 20 detects a change in the potential of the source of the transistor Q1 (change in the potential of the bit line BL), and outputs a signal of a change in the potential opposite to that of the source as the reference voltage V.
It is a circuit to apply as _R , and it is diode-connected N
Type channel MOS transistor Q2 and P type channel M
The transistor Q3 has an OS transistor Q3, and the source of the transistor Q3 is connected to the positive power source Vcc.

That is, the read-only memory M3 serves as an additional circuit 20 of the read circuit 13 and is an M in the read circuit 13.
It has a means for detecting a potential change of the source of the OS transistor Q1 and applying a signal of the opposite phase to the gate electrode of the transistor Q1.

Next, the operation of the read-only memory M3 will be described.

When the level of the bit line BL is slightly lowered, the gate-source voltage of the transistor Q3 increases and the conduction resistance of the transistor Q3 decreases. As a result, the current flowing through the transistor Q2 increases,
The level of the reference voltage V _R rises. Conversely, the bit line BL
When the level of the reference voltage V _R rises, the level of the reference voltage V _R decreases due to the operation opposite to the above operation.

Therefore, in the read-only memory M3, even if the level on the bit line BL changes slightly, the gate-source voltage of the transistor Q1 changes greatly, and the amplitude of the bit line BL is suppressed more. . Therefore, in the read-only memory M3, the level change of the bit line BL is smaller, and the speed of reading the contents of the memory cell 1 to the output node Tout is higher than that of the read-only memory M1.

As with the read-only memory M3, the additional circuit 20 may be provided in the read-only memory M2. That is, in the read-only memory M2, instead of supplying the fixed reference voltage V _R ′ to the gate electrode of the transistor Q1 ′, the change in the potential of the source of the transistor Q1 ′ (change in the potential of the bit line BL) is detected and this source is detected. A fourth embodiment of the present invention can be configured by applying a signal for performing a potential change in a phase opposite to that of the third embodiment as the reference voltage V _R ′. The same effect as that of the embodiment can be obtained.

[0041]

According to the present invention, even if the parasitic capacitance of the bit line is large, the content of the memory cell can be read at high speed and low power.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a read-only memory M1 that is a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a read-only memory M2 that is a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a read-only memory M3 that is a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional read-only memory M4.

FIG. 5 is a diagram showing a state example of memory cells in the read-only memories M1 and M3.

FIG. 6 is a diagram showing a state of a memory cell in the read-only memory M2.

[Explanation of symbols]

 M1, M2, M3 ... Read-only memory, 1, 1 '... Memory cell, 3 ... Load, 4, 5 ... Circuit node, 11, 12, 13 ... Read circuit, 20 ... Addition circuit, Q1 ... N-type channel MOS transistor , Q1 '... P type channel MOS transistor, Iss ... Positive constant current source, -Iss ... Negative constant current source, BL ... Bit line, WL ... Word line, Q1 ... N type channel MOS transistor, Q1' ... P-type channel MOS transistor, Vcc ... Positive power source, -Vcc ... Negative power source, Tout ... Output node.

Claims (2)

[Claims] 1. A memory cell; a bit line for transmitting a read signal from the memory cell; a MOS transistor; a load connected between the drain of the MOS transistor and a power supply; and a source of the MOS transistor. A read circuit including a constant current source connected between the constant current source and the ground, and the bit line is connected to a connection point between the source of the MOS transistor and the constant current source. Read-only memory characterized by. 2. A memory cell; a bit line for transmitting a read signal from the memory cell; a MOS transistor; a load connected between the drain of the MOS transistor and a power supply; and a source of the MOS transistor. A read circuit including a constant current source connected between the ground and a ground; a change in the potential of the source of the MOS transistor is detected, and a signal having a phase opposite to the change in the potential is detected by the MO signal.
A read-only memory, wherein: the bit line is connected to a connection point between the source of the MOS transistor and the constant current source.