JPH08314775A - File memory device - Google Patents

Abstract

PURPOSE: To save the effective data in a garbage collection processing object area and to increase the speed of data transfer for compaction of ineffective sectors in the pertinent area. CONSTITUTION: Data to be the garbage collection processing object is read out from a flash memory 5, and parallely, this data is supplied to a microcomputer 3 and made to be able to be written in a RAM in parallel with this read, and thereby, read and write of garbage collection processing object data are realized in the same memory cycle. Garbage collection processing object data is taken into the microcomputer, too, and sector management information included in this data is referred to perform the processing for compaction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a file memory device,
Further, the present invention relates to a technique for speeding up file writing to a file memory device, for example, a technique effectively applied to a garbage collection process of a memory card using an electrically rewritable flash memory.

[0002]

2. Description of the Related Art As a file memory device for storing file data in sector units, for example, there is a flash memory card using a flash memory. The above flash memory is Electrically Erasable and
Programmable read only memory (hereinafter simply referred to as E
Like EPROM), it can be electrically erased and written, and in that case, it has a function of electrically erasing the memory blocks collectively. Further, each memory block has a capacity of a plurality of sectors or more, and therefore one memory block includes a plurality of sectors. That is,
The unit of rewriting is made larger than the unit of sector. When rewriting the data in the flash memory, the data must be erased in block units prior to the rewriting.

When writing data in the flash memory, data erasing prior to that is performed in memory block units, and therefore all sectors of the memory block to which the sector is used for writing must be invalid. Data cannot be erased. Therefore, an invalid sector belonging to a memory block in which valid sectors and invalid sectors are mixed cannot be used for writing. The increase in the number of memory blocks as described above reduces the usage efficiency of the storage area of the flash memory. When there are no writable free sectors in the flash memory, it becomes impossible to write new data or rewrite existing data. Therefore, when writing the sector data, a garbage collection process is performed to increase the free area by filling the memory block including the invalid sector with valid data before batch erasing.

As described above, data erasing of the flash memory is performed in block units. Therefore, in order to erase the data of the block including the valid sector, it is necessary to move the data of the valid sector stored in the block to another storage area to evacuate. Although it is possible to reserve a specific area of the flash memory and use it as a temporary evacuation destination of the valid sector, the flash memory requires a significantly long time to erase and write data. Moving data is time consuming and not a good idea. Further, in the above flash memory, the characteristics of the memory cell are deteriorated by the high electric field applied to the memory cell at the time of erasing and writing data, so that there is a limit to the number of times data can be rewritten. Therefore, in order to suppress an increase in the number of times data is rewritten in the flash memory, it is desirable to provide a work area in the memory card and use the work area for temporarily holding data.

As the work area, for example, a pseudo static random access memory (hereinafter referred to simply as PSR) is used.
AM)) can be used. The PSRAM has an area for temporarily storing the data of the file in the flash memory, and for example, during the garbage collection process of the flash memory, the data of the file is transferred to the area in blocks from the flash memory. It Data is collectively erased from the block to which the data has been transferred to the PSRAM. After the batch erasing of the block is completed, unnecessary data can be erased by transferring and writing only the valid sector to the flash memory from the data stored in the PSRAM. This creates a writable free sector,
It becomes possible to write data to the flash memory again.

As an example of a document describing a memory card which is an example of a file memory system using a flash memory, "Nikkei Electronics No. 566" issued by Nikkei BP (October 26, 1992).
There are the 86th and 87th terms of.

[0007]

However, in the prior art, the present inventors have found that the following problems exist in transferring data from the flash memory to the PSRAM in the garbage collection process. It was

When data is transferred from the flash memory to the PSRAM, the writing process of the PSRAM is performed after the data reading process of the flash memory is completed. That is, the control microcomputer incorporated in the flash memory card executes a load command (read command from memory) to read data from the flash memory, and then executes a store command (write command to memory). Write the data to PSRAM. At the time of writing, the validity of the sector is determined in advance, and if it is invalid, the writing is not performed, whereby compaction is realized. However, the microcomputer has to execute the store and load instructions each time one data is transferred from the flash memory to the PSRAM, and cannot efficiently transfer the data from the flash memory to the PSRAM. This prolongs the time required for the garbage collection process.
Such a garbage collection process is performed when the host system instructs the memory card to write data, and when the flash memory mounted on the memory card does not have sufficient free sectors. Therefore, data cannot be written until the garbage collection process is completed. Therefore, the garbage collection process affects the processing capacity of the entire system, resulting in a decrease in throughput.

An object of the present invention is to perform data transfer inside a file memory device in a garbage collection process, that is, data transfer for saving valid data in a region subject to garbage collection and compacting invalid sectors in the region. , Is to be able to speed up. Another object of the present invention is to provide a file memory device capable of realizing high-speed processing for an external sector data write request.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the file memory device stores a file data in units of sectors and electrically erases data in units of memory blocks having a storage capacity of a plurality of sectors, and a nonvolatile semiconductor memory (5). Buffer (40) for storing valid data existing in the memory block of the memory block of the flexible semiconductor memory and a write buffer (41) for temporarily storing the write data when a write instruction is given from the outside. A volatile semiconductor memory (4), a microcomputer (3) capable of accessing the non-volatile semiconductor memory and the volatile semiconductor memory, and the non-volatile semiconductor memory, the volatile semiconductor memory and the microcomputer. Shared data bus (DB S) and parallel access control means for enabling the read data to be written to the volatile semiconductor memory in parallel with the data read operation by the microcomputer for the nonvolatile semiconductor memory that is the target of the garbage collection process. 2) and are provided. It is also possible to employ magnetic storage means instead of the non-volatile semiconductor memory (5).

The parallel access control means generates a write control signal for the volatile semiconductor memory when the microcomputer reads the sector data of the memory block to be garbage collected from the non-volatile semiconductor memory, and the volatile semiconductor memory. The memory controller (6) may generate a write control signal for the nonvolatile semiconductor memory when the microcomputer reads the sector data saved in the garbage buffer and compacted.

A lower address bus (ABUS-L) to which a lower address signal for addressing in one sector is applied from the microcomputer and an upper address bus (ABUS-H) to which an upper address signal is applied from the microcomputer are provided. The lower address bus is commonly connected to both the nonvolatile memory and the volatile semiconductor memory together with the microcomputer, and the upper address signal input terminal of the nonvolatile semiconductor memory is coupled to the dedicated nonvolatile memory upper address bus (FABUS-H). The upper address signal input terminal of the volatile semiconductor memory is coupled to a dedicated volatile memory upper address bus (PABUS-H), and the parallel access control means is a sector of the memory block targeted for the garbage collection process. Data is micro A file bank register (23) that supplies a required upper address to the volatile memory upper address bus when read and accessed from the nonvolatile semiconductor memory by a computer, and saved and compacted in a garbage buffer of the volatile semiconductor memory. A write bank register (24) may be further provided for supplying a required upper address to the nonvolatile memory upper address bus when sector data is read and accessed by the microcomputer.

The file memory device can be an IC card or a memory card. At this time, an interface unit (2) that receives a command to be executed by the microcomputer from the host device (10) and exchanges data with the host device is sent to the data bus.
0) are combined.

[0016]

According to the above means, in the garbage collection process, the data to be processed is read from the non-volatile semiconductor memory, the read data is supplied to the microcomputer in parallel with the volatile semiconductor memory. Since it is writable, the write operation of reading the data targeted for the garbage collection process from the nonvolatile semiconductor memory and saving it in the volatile semiconductor memory can be realized in the same memory cycle.

Since the data targeted for the garbage collection process can also be fetched by the macro computer, the microcomputer accesses the memory while updating the address until the file end information of the data to be saved in the volatile semiconductor memory is detected. The transfer control can be performed by repeating the operation. Further, since the data targeted for the garbage collection process can also be fetched by the macro computer, when such data includes sector management information indicating the validity of the sector, the microcomputer does not operate in the same memory cycle. At, the control information for compaction is obtained, and the process for compaction can also be performed.

Compared to a microcomputer in which a load instruction and a store instruction are repeatedly executed to transfer data one by one from a nonvolatile semiconductor memory to a volatile semiconductor memory via the microcomputer, the nonvolatile semiconductor memory is more volatile. The data transfer of the memory block to the semiconductor memory is accelerated, and the sector data can be written at high speed to the file memory device.

[0019]

1 is a block diagram of a data processing system to which a flash memory card (hereinafter also simply referred to as a memory card) 1 according to an embodiment of the present invention is applied. 1
Reference numeral 0 denotes a host device such as a workstation or a personal computer system, in which a system bus 14 is shared by a host CPU 11, a main memory 12 and an interface controller 13 which are shown as representatives.
The flash memory card 1 is detachably connected to the interface controller 13, although not particularly limited thereto. Although not particularly limited, the memory card 1 shown in the figure has an interface adapted to the JEIDA memory card interface, and is replaced by a magnetic storage device such as a hard disk device or a flexible disk device, and an auxiliary storage device of a computer. A file memory device that can be used as The memory card 1 is
Card controller 2, microcomputer 3, PS
The RAM 4 and the flash memory 5 are provided.

The flash memory 5 is a nonvolatile semiconductor memory device that can be electrically rewritten in block units.
For example, memory cells composed of insulated gate field effect transistors having a two-layer gate structure are arranged in a matrix. The control gates of the transistors forming the memory cells are connected to corresponding word lines (not shown), the drains of the transistors are connected to corresponding data lines (not shown), and the sources of the transistors are not shown in common for each block. Each is connected to the source line. The operation of writing data to the memory cell in the flash memory 5 is realized by, for example, applying a high voltage to the control gate and the drain and injecting electrons from the drain side to the floating gate by, for example, avalanche injection. By this write operation, the threshold voltage of the transistor of the memory cell seen from the control gate is made higher than that of the erased memory cell in which the write operation is not performed. On the other hand, the erase operation is realized, for example, by applying a high voltage to the source and extracting electrons from the floating gate to the source side by the tunnel phenomenon. Therefore, a plurality of memory cells connected to the same source line serve as a memory block as a batch erase unit. By the erase operation, the threshold voltage of the transistor of the memory cell seen from the control gate is lowered. The batch erase unit is not limited to the block of memory cells common to the source lines. The configuration or range of the memory block in the batch erase unit differs depending on the application format of the rewrite voltage.

The flash memory 5 stores file data in sector units. For example, the sector is 512 B (byte) in consideration of compatibility with the magnetic storage device. Further, the memory block as a batch erase unit in the flash memory is set to 16 KB, which is larger than the capacity of one sector. Since the microcomputer 3 operates the data in the flash memory 5 in units of sectors, the file information for indicating in which sector the data specified by the file name exists and the memory address of each memory block in which each sector is located. And sector management information for indicating whether or not valid data exists in each sector is stored in the flash memory together with the data.

When rewriting the data stored in the flash memory 5, it is necessary to erase the existing data before writing the desired data. Since the erase unit is a memory block unit such as 16 KB, when the block includes a valid sector, it is necessary to save the data of such valid sector prior to erasing. The PSRAM 4 is used as a save area for the garbage buffer 40 in the garbage collection process. When the host device 10 requests writing to the memory card 1, the PSRAM 4 is used as a write buffer 41 for temporarily holding the data requested to be written.

FIG. 1 shows a detailed block diagram of a flash memory card 1 according to an embodiment of the present invention. The card controller 2 is connected to the interface controller 13 of the host device 10 via the interface unit 20. The interface unit 20 includes a command register 200 in which commands are written from the host device 10, a data register 201 for temporarily storing data exchanged with the host device 10, and an internal state of the flash memory card 1 from the host device 10 side. The status register 202 is made readable.

The interface unit 20 is a data bus DBU.
It is coupled to the microcomputer 3, PSRAM 4, and flash memory 5 via S. The microcomputer 3 executes the command written in the command register 200. PSRAM4 along with the command execution
An address signal for accessing the flash memory 5 is generated by the microcomputer 3. The upper address bus ABUS-H and the lower address bus ABUS-L are coupled to the address output terminals of the microcomputer 3. Here, the lower address bus ABUS-L has the number of bits required to address the inside of the memory area for one sector. Specifically, since one sector is 512B, it is 9 bits in byte address conversion. The 10th bit or more is allocated to the upper address bus ABUS-H. Therefore, the upper address supplied to the upper address bus ABUS-H can be regarded as an address designating a sector in the flash memory 5.

The lower address bus ABUS-L is PSRA
It is commonly connected to M4 and the lower address input terminals of the flash memory 5. The upper address bus ABUS-H is connected to one input terminal of the selectors 21 and 22. The output of the write bank register 23 whose input is connected to the data bus DBUS is connected to the other input terminal of the selector 21,
The other input terminal of the selector 22 has a data bus DBUS
The output of the file bank register 24, whose input is connected to, is given. The output of the selector 21 is connected to the address bus FABUS-H dedicated to the address signal supply to the upper address input terminal of the flash memory 5, and the output of the selector 22 is the address signal supply to the upper address input terminal of the PSRAM 4. Is connected to an address bus PABUS-H dedicated to

The memory controller 6 has access control signals such as an address strobe signal AS, a write signal WR, and a read signal RD output from the microcomputer 3,
The value of the upper address bus ABUS-H, the data saving and compaction instruction signal φ1 in the garbage collection processing, and the compacted data are written back together with another write data to the sector of the memory bank targeted for the garbage collection processing. In response to the processing instruction signal φ2 and the like, an access control signal for the PSRAM 4 and the flash memory 5 is generated. In FIG. 1, a chip select signal C is used as such an access control signal.
S1 and CS2 and write enable signals WE1 and WE2 are representatively shown. The memory controller 6 controls the application of a high voltage when rewriting the flash memory 5.

FIG. 3 shows a control mode for the flash memory 5 and the PSRAM 4 using the write bank register 23 and the file bank register 24.
When data saving and compaction are instructed by the control signal φ1 during the garbage collection processing, the microcomputer 3 saves the data of the memory bank to be the garbage collection processing target in the garbage buffer 40 of the PSRAM 4. Read access control is performed. At this time, the memory controller 6 outputs an access control signal for enabling the read operation of the flash memory 5 with CE2 = H (chip selection) and WE2 = L (read operation instruction) for each memory read access cycle by the microcomputer 3. , Again, CE1 =
An access control signal that enables the write operation of the PSRAM 4 is output with H (chip selection) and WE1 = H (write operation instruction). At this time, the upper address of the data storage area on the garbage buffer 40 in which the data is saved is stored in the data bus DBUS by the microcomputer 3 in advance.
It is set in the file bank register 24 via. As described above, the upper address is regarded as an address designating an area corresponding to the storage area of one sector. In this state, the flash memory 5 by the microcomputer 3
Read access is started. For example, as shown in FIG. 3, when the upper address AHd is output to the upper address bus ABUS-H, the lower address bus ABUS-
When the address is output to L, predetermined sector data having the upper address AHd on the flash memory 5 as the start address is read, and the read data is stored in the PSRAM 4
The upper address AHi (previously set in the file bank register 24) is written in the area having the head address. The sector data thus read is also supplied to the microcomputer 3 via the data bus DBUS. The microcomputer 3 checks the predetermined data supplied thereby, for example, the sector management information indicating whether the sector data is valid or not, and determines whether or not the sector is a compaction target sector. When it is detected that the sector is an invalid sector, it is not necessary to continue the data read operation for the sector thereafter. When accessing the sector following the invalid sector, the microcomputer sets the value of the file bank register 24 to the same value as the previous value. When it is detected that the sector is a valid sector, the lower address is sequentially updated and the data read operation is continued until the file end flag is detected. When accessing the next sector after the valid sector, the microcomputer increments the value of the file bank register 24 by +1.
Update. As a result, the valid sector data headed by the upper addresses AHa and AHd illustrated in FIG. 3 have invalid sector data in the areas between them (areas headed by the upper addresses AHb and AHc, respectively). However, it is transferred to the continuous area having the upper addresses AHh and AHi on the PSRAM 5, respectively. Therefore, the data in one memory block, which is a batch erase unit, is stored in the PSRAM 4 with valid sector data packed therein. In the above processing, the selector 22 selects the output of the file bank register 24 under the control of the memory controller 6, and the selector 21 under the control of the memory controller 6.
Select the value of BUS-H.

After the compaction for the invalid area is realized, when the writing process to the flash memory is instructed by the control signal φ2, the microcomputer 3 flushes the compacted valid sector data on the garbage buffer 40. Access control is performed to write back to the memory block on the memory 5 which is the target of the garbage collection process. In synchronization with this, the memory controller 6 sets an access control signal that enables the flash memory 5 to perform a write operation with CE2 = H (chip selection) and WE2 = H (write operation instruction) for each memory access cycle by the microcomputer 3. , CE1 = H (chip selection), WE1 =
As L (read operation instruction), an access control signal that enables the PSRAM 4 to read is output. At this time, the microcomputer 3 previously sets the upper address of the data storage area to be written back from the garbage buffer 40 to the flash memory 5 in the write bank register 23 via the data bus DBUS. As described above, the upper address is regarded as an address designating an area corresponding to the storage area of one sector. In this state, the read access of the PSRAM 4 by the microcomputer 3 is started. For example, as shown in FIG. 3, when an address is output to the lower address bus ABUS-L while the upper address AHi is output to the upper address bus ABUS-H, the upper address AHi on the PSRAM 4 is set as the start address. Predetermined sector data is read, and the read data is stored in the upper address AH on the flash memory 5.
It is written in the area having the start address of b (set in the write bank register 23 in advance). As a result, valid sector data is packed in the memory block targeted for the garbage collection process, and a free area is secured. When writing back an effective sector, another sector data temporarily stored in the write buffer 41 in response to a write instruction from the host device 10 can be newly written in the empty area. In the above process, the selector 22 selects the value of the upper address bus ABUS-H under the control of the memory controller 6, and the selector 21 selects the output of the write bank register 23 under the control of the memory controller 6.

FIG. 4 shows an example of the timing when the data read from the flash memory 5 is supplied in parallel to the microcomputer 3 and the PSRAM 4. In the figure, the access control signals AS, CE1, WE1, CE2 are shown in negative logic. One memory access cycle shown in the figure shows a cycle for one lower address.

FIG. 5 shows a state of data compacted by the garbage collection process. In the figure, V = 1 means that the sector data is valid. V = 0 means invalid.
As for the data of the memory block subject to the garbage collection process, only valid data is saved in the PSRAM 4. After that, the memory collection target memory block of the flash memory 5 is collectively erased, and after erasing, the valid sector data saved in the PSRAM 4 is written back to the memory block of the flash memory 5. Further, since a vacant area indicated by hatching is secured, data writing is performed in this vacant area in order to respond to the write request from the host device 10 which is the cause of the garbage collection process.

FIG. 6 shows a flowchart of the write operation inside the memory card when the garbage collection process occurs when the sector data is requested to be written from the host device side. When writing the file data (sector data) to the memory card, the host device 10 issues a file write command (S1) and transfers the write data (S2). The write command is set in the command register 200, and the write data is sequentially loaded in the data register 210.
When the command is written, the interface unit 20 notifies the microcomputer 3 of it by an interrupt or the like. The microcomputer 3 first stores the write data sequentially transferred to the data register 201 in the write buffer 42 of the PSRAM 4 (S1).
0). Further, the usage status of the flash memory 5 is confirmed by referring to the information indicating the usage status of the sector. For example, if there is a completely rewritable memory block, the data of the write buffer 41 is written in the sector of the memory block (S15). If no such memory block exists, garbage collection processing is performed (S1).
1 YES). In the garbage collection process, as described based on FIGS. 3 to 5, the data of the valid sector of the target memory bank is saved in the PSRAM and the compaction of the invalid sector is performed (S12). Then, the batch erase operation is performed on the memory block (S13). After erasing, the saved and compacted sector data is written from the garbage buffer 40 of the PSRAM 4 to the relevant memory block of the flash memory 5 (S14), and is held in the write buffer 41 in the area subsequent to the relevant memory block. Write data is written (S1
5).

In the above embodiment, the upper address bus PABU dedicated to each of the PSRAM 4 and the flash memory 5 is used.
S-H and FABUS-H are used. In this case, the card controller 2 uses the respective buses PABUS-H and FAB.
An interface terminal must be provided to connect the US-H to the PSRAM 4 and the flash memory 5 separately. When reducing the number of external terminals of such a card controller 2, a bus PABU is provided inside the card controller.
A multiplexer for selecting S-H or FABUS-H may be provided, and the corresponding address input terminals of the PSRAM 4 and the flash memory 5 may be commonly connected to the output thereof. FIG. 7 shows an operation timing chart for such a configuration. As is clear from the figure, the bus PABUS-H
And FABUS-H values are multiplexed and output. When the address of the bus PABUS-H is selected as the upper address, the flash memory 5 must maintain the data output operation. The data output circuit of the flash memory 5 includes an output data latch circuit.

According to the above embodiment, the following operational effects can be obtained. (1) During the garbage collection process, the read data is supplied to the microcomputer 3 and is writable to the PSRAM 4 in parallel with reading the data to be processed from the flash memory 5, so that the garbage is collected. The write operation of reading the data to be the collection processing target from the flash memory 5 and saving it in the PSRAM 4 can be realized in the same memory cycle.

(2) Since the macro computer 3 can take in the data to be garbage-collected, the microcomputer 3 updates the address and stores the memory until the file end information of the data to be saved in the PSRAM 4 is detected. The transfer control can be performed by repeating the access operation.

(3) Since the data targeted for the garbage collection process can also be taken in by the macro computer 3, when such data includes sector management information indicating the validity of the sector, a microcomputer is used. 3 can obtain control information for compaction in the same memory cycle and can also perform processing for compaction.

(4) The microcomputer repeatedly executes the load instruction and the store instruction to send data one by one from the flash memory to the PS via the microcomputer.
Compared with the case where the data saving and compaction are realized by performing the process of writing in the RAM, the data transfer of the memory block from the flash memory 5 to the PSRAM 4 can be speeded up, and the speed of the write process inside the flash memory card can be increased. It will be possible. As a result, in the system using the flash memory card of the present embodiment, it is possible to improve the throughput when the host device 10 side performs continuous writing.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes. For example,
Although the flash memory is used as the storage means for the sector data in the above embodiment, the present invention is not limited to this and E
It may be an EPROM, a flexible disk device, a hard disk device, or the like. In the above description, the case where the invention made by the present inventor is mainly applied to a memory card as an IC card, which is a field of application which is the background of the invention, is not limited thereto and the same as the host device. It may be mounted on a circuit board.

[0038]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in the garbage collection process, in parallel with reading the data to be processed from the nonvolatile semiconductor memory, the read data is supplied to the microcomputer and can be written in the volatile semiconductor memory. Therefore, the write operation of reading the data to be garbage-collected from the nonvolatile semiconductor memory and saving it in the volatile semiconductor memory can be realized in the same memory cycle.

Since the data targeted for the garbage collection process can also be fetched by the macro computer, the microcomputer accesses the memory while updating the address until it detects the file end information of the data to be saved in the volatile semiconductor memory. The transfer control can be performed by repeating the operation. Further, when such data includes sector management information indicating the effectiveness of the sector, the microcomputer obtains control information for compaction in the same memory cycle,
Processing for compaction can also be performed.

Compared to a microcomputer in which a load instruction and a store instruction are repeatedly executed to transfer data one by one from a nonvolatile semiconductor memory to a volatile semiconductor memory via the microcomputer, the nonvolatile semiconductor memory is more volatile. The data transfer of the memory block to the semiconductor memory is accelerated, and the sector data can be written at high speed to the file memory device. As a result, in the system using the file memory device of the present invention, the waiting time of the host system is shortened even when the system side performs continuous writing. Therefore, it contributes to the improvement of the processing speed of the entire system.

[Brief description of drawings]

FIG. 1 is a block diagram of a flash memory card according to an embodiment of the present invention.

FIG. 2 is a block diagram of a data processing system to which a flash memory card according to an embodiment of the present invention is applied.

FIG. 3 is an explanatory diagram showing a control mode for a flash memory and a PSRAM using a write bank register and a file bank register.

FIG. 4 is a timing chart showing how data read from a flash memory is supplied in parallel to a microcomputer and PSRAM.

FIG. 5 is an explanatory diagram showing a state of data compacted by a garbage collection process.

FIG. 6 is a flowchart of a write operation inside the memory card when a garbage collection process occurs during sector write from the host device side.

FIG. 7 is a timing chart of a modified embodiment in which the PSRAM and the upper address input terminals of the flash memory are commonly connected to reduce the number of external terminals of the card controller and a unique upper address is multiplexed and supplied to each. is there.

[Explanation of symbols]

1 Flash Memory Card 2 Card Controller 20 Interface 21, 22 Selector 23 Write Bank Register 24 File Bank Register 3 Microcomputer DBUS Data Bus ABUS-H Upper Address Bus ABUS-L Lower Address Bus PBUS-H PSRAM Unique Upper Address Bus FBUS -H Upper address bus specific to flash memory φ1 Data save and compaction instruction signal φ2 Write back instruction signal to memory bank 4 PSRAM 40 Garbage buffer 41 Write buffer 5 Flash memory 10 Host device

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Kikuchi 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hiritsu Cho-LS Engineering Co., Ltd. (72) Inventor Soichi Hatano Kodaira, Tokyo 5-20-1 Jitsumizu Honcho, Ichi, Japan, within Hitate Super L.S.I. Engineering Co., Ltd. (72) Inventor Yasuhiko Saie 5-20-1, Kamimizuhoncho, Kodaira, Tokyo Metropolitan Government I Engineering Co., Ltd. (72) Inventor Kyoo Okubo 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hirate RLS AI Engineering Co., Ltd. (72) Inventor Takeshi Suzuki Kodaira, Tokyo 5-20-1 Kamimizuhonmachi, Ichi, Hitate Cho-LS Engineering Co., Ltd. (72) Inventor Katayama Hiroshi 1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Inside the Hitachi, Ltd. System Development Laboratory (72) Inventor Kenichi Kaki 1099, Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Inside the Hitachi, Ltd. System Development Laboratory (72) Inventor Kadowaki Shigeru 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Super RLS AI Engineering Co., Ltd. (72) Inventor Masamichi Kishi 5-20-1 Sanmizuhoncho, Kodaira-shi, Tokyo Super LSI Engineering Co., Ltd.

Claims (5)

[Claims] 1. A first storage means for storing file data in sector units, and a second storage means for storing valid data existing in the storage area in a garbage collection process for the storage area on the first storage means. Storage means of
Data processing means that can access the first and second storage means, a data bus shared by the first and second storage means and the data processing means, and a target of the processing in the garbage collection processing. Parallel access control means for writing the read data into the second storage means in parallel with the data read operation by the data processing means for the first storage means. File memory device. 2. A non-volatile semiconductor memory in which file data is stored in units of sectors and which can be electrically erased in units of memory blocks having a storage capacity of a plurality of sectors, and a Garvey for memory blocks of the non-volatile semiconductor memories. A volatile semiconductor memory used as a garbage buffer for storing valid data existing in the memory block in the dicorrection process and a write buffer for temporarily storing write data when a write instruction is given from the outside, and the nonvolatile memory. A microcomputer capable of accessing the semiconductor memory and the volatile semiconductor memory respectively; a data bus shared by the microcomputer with the nonvolatile semiconductor memory and the volatile semiconductor memory;
Parallel access control means for writing the read data into the volatile semiconductor memory in parallel with the data read operation by the microcomputer for the nonvolatile semiconductor memory that is the target of the garbage collection processing. A file memory device comprising: 3. The parallel access control means generates a write control signal of a volatile semiconductor memory when the microcomputer reads sector data of a memory block targeted for garbage collection processing from the non-volatile semiconductor memory, and is volatile. 3. A memory controller for generating a write control signal for a non-volatile semiconductor memory when a microcomputer reads sector data saved and compacted in a garbage buffer of the semiconductor memory. File memory device. 4. A lower address bus provided with a lower address signal for addressing in one sector from a microcomputer and an upper address bus provided with an upper address signal from the microcomputer, the lower address bus being nonvolatile together with the microcomputer. Volatile and volatile semiconductor memory are commonly connected, the upper address signal input terminal of the non-volatile semiconductor memory is coupled to the dedicated non-volatile memory upper address bus, and the upper address signal input terminal of the volatile semiconductor memory is dedicated to it Of the volatile memory upper address bus of the parallel access control means, the parallel access control means, when the sector data of the memory block targeted for the garbage collection processing is read from the nonvolatile semiconductor memory by the microcomputer and accessed. Volatile memory high-order address file bank registers to supply a required high-order address to the bus, and nonvolatile memory when the microcomputer stores and accesses the compacted sector data saved in the garbage buffer of the volatile semiconductor memory. 4. The file memory device according to claim 3, further comprising a write bank register for supplying a required upper address to the upper address bus. 5. A memory card is provided which is provided with an interface unit for receiving a command to be executed by a microcomputer from a host device and for transferring data to and from the host device. The file memory device according to claim 4, wherein the file memory device is provided.