JPH08314638A - Control and signal processing unit for recording and reproducing device - Google Patents

Abstract

PURPOSE: To reduce a chip size or improve the operating frequency when a control and signal processing circuit is composed of an integrated circuit. CONSTITUTION: The analog signal read out of a magnetic recording medium 101 through a magnetic head 109 and a read/write amplifier 102 is converted by a read system signal processing circuit 110 into binary data, which are stored in a buffer memory 104. A disk controller 105 is switched to a sleep mode with the signal from an MPU 106 and the MPU 106 performs the addressing of the buffer memory 104. Then a servocontrol circuit 107 operates with the signal from the MPU 106 to make the magnetic head 109 to seek a next track. The binary data stored in the buffer memory 104, on the other hand, have an error corrected by the disk controller 105 in the seek time and are outputted from the magnetic recording and reproducing device through an interface 108.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing apparatus, and more particularly to signal processing means for operating a signal processing circuit in a divided manner.

[0002]

2. Description of the Related Art A configuration example of a recording / reproducing apparatus equipped with a control / signal processing circuit for a conventional recording / reproducing apparatus will be described with reference to FIGS. 2, 3, 7, 8 and 9. The recording / reproducing apparatus of FIG. 7 includes a magnetic recording medium 101, a read / write amplifier 102, a signal processing unit 103, a buffer memory 104, a disk controller unit 105, a microprocessor unit (hereinafter, MPU) 106, a servo control unit 107,
And an interface unit 108.

The signal processing unit 103 comprises a read system signal processing unit 110 and a write system signal processing unit 120. There are various types of read and write signal processing circuits. Here, PRML (Partial Response Maxi
The signal processing circuit using the mum likelihood method is taken as an example, but the present invention is not limited to this. A publicly known example of the PRML system is disclosed in Japanese Patent Application Laid-Open No. 2-182032.

Read and write signal processing circuits are shown in FIGS. 2 and 3.

The read system signal processing circuit 110 uses the AGC2
11, A / D converter 212, waveform equalizer 213, Viterbi decoder 214, demodulation circuit 215,
It is composed of a PLL circuit 216.

The write system signal processing circuit 120 comprises a modulation circuit 313, a precoder 312, and a write compensation circuit 311.

The data recording / reproducing operation of the magnetic recording / reproducing apparatus will be described below. The recording data transferred from the host side to the magnetic disk device is the interface unit 108.
And is temporarily stored in the buffer memory 104 via the disk controller 105, and is input from the buffer memory 104 to the write system signal processing circuit 120 via the disk controller in accordance with the processing speed of the signal processing circuit. The recording data is converted into a recording code suitable for high-density recording by the modulation circuit 313, the PR characteristic is given by the precoder 312, the process for correcting the magnetization interference is performed by the write compensation circuit 311, and the read / write operation is performed. Amplifier 10
At 2, the magnetic head 109 is driven to record on the magnetic recording medium 101.

A signal read from the magnetic recording medium 101 via the magnetic head 109 and the read / write amplifier 102 is input to the read system signal processing circuit 110.
The read signal is amplified to a proper signal amplitude by the AGC 211, converted into a digital signal by the A / D converter 212, waveform-equalized by the waveform equalizer 213, and maximum likelihood decoded into binary by the Viterby decoder 214. The original data is demodulated from the recording code in the demodulation circuit 215 and temporarily stored in the buffer memory 104 via the disk controller 105. The data stored in the buffer memory is transferred to the interface unit 108 according to the transfer speed on the host side.
Sent to the host side via. The PLL circuit 216 has A
This is a circuit for generating a reference clock for sampling in the / D converter 212.

The position of the magnetic head 109 and the number of rotations of the magnetic recording medium 101 are determined by the servo control circuit 107 and the MPU 1.
It is controlled by 06.

The signal processing circuit 10 in the conventional circuit configuration example.
3, a time chart of operations of the buffer memory 104, the disk controller 105, the MPU 106, and the servo control circuit 107 will be described with reference to FIGS. 8 and 9.

FIG. 8 shows a signal processing circuit 103 and a buffer memory 10 for reading data in the conventional circuit configuration example.
4 is a time chart of operations of the disk controller 105, MPU 106, and servo control circuit 107. The seek times 801 and 804 are 5 to 10 msec on average, and the minimum is about 1 msec. Spin waiting times 802 and 805
Is about 0 msec to 10 msec, and the average is about 5 msec.
Data read time 803 and 806 is about 0.1m
sec / track. The signal processing circuit 103 operates during the data read times 811 and 812. Since the buffer memory 104 performs the caching for holding the data of the previously read track until the data of the next track is read, it always operates (821). The disk controller 105 operates until the data read at the data read time is output to the interface 108 (831 and 832). The MPU 106 always operates (841). The servo control circuit 107 performs a settling operation (851 and 853) for moving the magnetic head to a target position during a seek time, and a following operation (852 and 854) for holding the magnetic head at a fixed position during a disk rotation waiting time.

FIG. 9 shows a signal processing circuit 103 and a buffer memory 10 for reading data in the conventional circuit configuration example.
4 is a time chart of operations of the disk controller 105, MPU 106, and servo control circuit 107. Overlapping description of parts corresponding to those in FIG. 8 will be omitted. The data writing times 903 and 906 are about 0.1 msec / track. The signal processing circuit 103 operates during data writing times 911 and 912. Since the buffer memory 104 performs the caching for holding the previously written data until the data of the next track is written, it always operates (921). The disk controller 105 takes in the data to be written at the same time as the seek of the magnetic head starts via the interface 108 (931 and 933), and outputs it to the signal processing circuit 103 after completion of the rotation waiting (932 and 934). MPU
106 always operates (941).

In the conventional method, both the signal processing circuit 103 and the disk controller 105, which consume a large amount of power, operate during the data read time and the data write time. Therefore, the maximum power consumption of the control / signal processing circuit of the magnetic recording / reproducing apparatus becomes large.

[0014]

Control of recording / reproducing apparatus
In order to configure the signal processing circuit to operate at low cost and at high speed, it is necessary to increase the integration degree of the circuit and simultaneously increase the frequency of the operation clock. However, if the frequency of the operation clock is increased, the power consumption of the circuit increases, and it is difficult to increase the degree of integration of the circuit at low cost.

An object of the present invention is to control a recording / reproducing apparatus by using a system in which a signal processing circuit is divided so that only a necessary part is operated by a high frequency clock and the other parts are stopped or put in a sleep mode. The purpose is to reduce the maximum power consumption of the entire signal processing device.

[0016]

The operation of reading data from a recording / reproducing apparatus has the following three stages. (1) Seek head, (2) Wait for medium rotation, (3) Read data. Of these, the read system signal processing circuit operates only during the data read operation. On the other hand, the signal processing circuit does not operate while the head seeks and the medium waits for rotation.

Similarly, the operation of writing data to the recording / reproducing apparatus has the following three stages. (1) Seek head, (2) Wait for medium rotation, (3) Write data. Of these, the write system signal processing circuit operates only during the data write operation. On the other hand, the signal processing circuit does not operate while the head seeks and the medium waits for rotation.

By using this fact, a means for stopping the signal processing circuit or putting the signal processing circuit into the sleep mode is provided during the seek of the head and the waiting of the rotation of the medium, so that the power consumption of the entire control / signal processing circuit of the recording / reproducing apparatus is reduced. Can be lowered.

Further, by providing a buffer memory between the signal processing circuit and the controller, there is provided means for stopping the disk controller or putting it in a sleep mode during data read and data write. The power consumption of the entire circuit can be reduced.

[0020]

A buffer memory is arranged between the signal processing circuit of the control / signal processing circuit of the present invention and the disk controller, and the reproduced digital data is temporarily stored in the buffer memory to seek the head and the medium. And a data read / write device having means for stopping the signal processing circuit or putting the signal processing circuit into a sleep mode while waiting for rotation of
According to the control and signal processing device for the recording / reproducing device, which is provided with means for stopping the disk controller during writing or lowering the clock frequency to put it in the sleep mode,
The power consumption of the control / signal processing circuit can be reduced, the heat generation of the circuit can be suppressed, the operating frequency can be increased, or the chip size when the control / signal processing circuit is configured by an integrated circuit can be reduced. it can.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1, 2, 3, 10 and 11.

FIG. 1 is a block diagram showing an embodiment of a control and signal processing apparatus for a recording / reproducing apparatus of the present invention. Here, a signal processing circuit using the PRML system is taken as an example.
Duplicated description will be omitted for portions corresponding to those in FIGS. 2, 3 and 7 described in the section of the related art.

In FIG. 1, the buffer memory 104
Is a signal processing unit 103 and a disk controller 105.
And the recorded data or the reproduced data is temporarily stored. The operation of reading data from the magnetic recording / reproducing apparatus shown in FIG. 1 will be described below.

An analog signal for a maximum of one track read from the magnetic recording medium 101 via the magnetic head 109 and the read / write amplifier 102 in response to a data read request is read by the read system signal processing circuit 110 to 0 /. 1 is converted into binary data, and the buffer memory 104
Is accumulated in During this time, the disk controller 105
Is switched to the sleep mode by a signal from the MPU 106, and the addressing of the buffer memory 104 is performed by the MPU 106. The address information is notified from the disk controller 105 to the MPU 106 during the seek time of the magnetic head before reading the data.

When the data reading from the track is completed, the servo control circuit 10 receives a signal from the MPU 106.
7, the magnetic head 109 seeks to the next track. During this period, the signal processing unit 103 keeps the MPU 1
A signal from 06 switches to sleep mode. On the other hand, when reading data, the buffer memory 10
The binary data stored in 4 is subjected to error correction processing and the like in the disk controller 105 during this seek time, and is output from the magnetic recording / reproducing apparatus via the interface 108.

The operation of the magnetic recording / reproducing apparatus shown in FIG. 1 at the time of writing data will be described below.

In response to the data write request, the MPU 10
The servo control circuit 107 operates in response to the signal from 6, and the magnetic head 109 seeks to the target track.
During this period, the signal processing unit 103 is switched to the sleep mode in which it is stopped or the frequency of the clock is lowered by the signal from the MPU 106. On the other hand, the recording data is input to the disk controller 105 via the interface 108 during this seek time, subjected to error correction processing, conversion into a recording code, etc., and stored in the buffer memory 104.

When the seek to the target track by the magnetic head 109 is completed, the write data for the target track stored in the buffer memory 104 is converted into a write signal by the write system signal processing circuit 120, and read / write. Writing is performed on the magnetic recording medium 101 via the amplifier 102 and the magnetic head 109. During this time, the disk controller 105 is switched to the sleep mode by the signal from the MPU 106, and the MPU 106 performs the addressing of the buffer memory. The address information is notified from the disk controller 105 to the MPU 106 during the seek time of the magnetic head before writing data.

In the magnetic recording apparatus of the embodiment, the disk controller 105 is set to the sleep mode during data reading and data writing, and the signal processing unit 103 is set to the sleep mode during seeking of the magnetic head 109. The power consumption of the entire control / signal processing circuit of the magnetic recording / reproducing apparatus can be reduced.

In the embodiment, the signal processing circuit 103, the buffer memory 104, the disk controller 105, M
A time chart of operations of the PU 106 and the servo control circuit 107 will be described with reference to FIGS. 10 and 11.

FIG. 10 is a time chart of the operations of the signal processing circuit 103, the buffer memory 104, the disk controller 105, the MPU 106, and the servo control circuit 107 when reading data in the embodiment. Overlapping description of parts corresponding to those in FIG. 8 will be omitted. The signal read at the data read time and output from the signal processing circuit 103 is directly stored in the buffer memory 104 without passing through the disk controller 105. The disk controller is in sleep mode during the data read time (1032 and 1034). Since the buffer memory 104 caches data until the data of the next track is read, it always operates (1
021). When the data reading is completed and the seek to the next track is started, the disk controller operates (1031, 1033 and 1035) to transfer the data stored in the buffer memory 104 to the interface 10.
Output via 8. The MPU 106 always operates (1
041).

FIG. 11 is a time chart of operations of the signal processing circuit 103, the buffer memory 104, the disk controller 105, the MPU 106, and the servo control circuit 107 at the time of writing data in the embodiment. Overlapping description of parts corresponding to those in FIG. 9 will be omitted. The disk controller operates from the write request to the end of storing the data input via the interface 108 in the buffer memory (1131, 113).
3 and 1135), the data write time
Mode (1132 and 1134). buffer·
Since the memory 104 performs the caching for holding the previously written data until the data of the next track is written, it always operates (1121). The MPU 106 always operates (1141).

In the magnetic recording / reproducing apparatus control / signal processing circuit having the configuration shown in the present embodiment, the maximum power consumption is kept low because the signal processing circuit 103 with large power consumption and the disk controller 105 do not operate simultaneously. You can

Another embodiment of the present invention will be described with reference to FIGS. 4, 5 and 6.

FIG. 4 is a block diagram showing an embodiment of the control and signal processing apparatus for the recording / reproducing apparatus of the present invention. Here, a signal processing circuit using the PRML system is taken as an example. Regarding parts corresponding to FIGS. 2, 3 and 7,
A duplicate description will be omitted.

The read system signal processing circuit 410 uses the AGC2
11, an A / D converter 212, a waveform equalizer 213, a Viterby decoder 214, and a PLL circuit 216.

The write system signal processing circuit 420 comprises a precoder 312 and a write compensation circuit 311.

In FIG. 4, the buffer memory 104 is a Viterby decoder 214 in the read system signal processing unit 410.
And a precoder 312 in the write signal processing unit 420
Between the demodulation circuit 215 and the modulation circuit 313,
Temporarily saves recorded data or playback data. The operation of reading data from the magnetic recording / reproducing apparatus shown in FIG. 4 will be described below. In the circuit configuration shown in this embodiment, the buffer memory 104 can be shared with the path memory of the Viterby decoder 214.

An analog signal for a maximum of one track read from the magnetic recording medium 101 via the magnetic head 109 and the read / write amplifier 102 in response to a data read request is read by the read system signal processing circuit 410 to the maximum likelihood. It is decoded and stored in the buffer memory 104. During this time, the disk controller 105, the demodulation circuit 215, and the modulation circuit 313 are switched to the sleep mode by the signal from the MPU 106, and the MPU 106 performs the addressing of the buffer memory. The address information is stored in the disk during the seek time of the magnetic head before reading the data.
The controller 105 notifies the MPU 106.

When the data reading from the track is completed, the servo control circuit 10 is activated by the signal from the MPU 106.
7 operates and seeks to the next track of the magnetic head 109 is performed. During this period, the signal processing unit 103 keeps the MPU 1
A signal from 06 switches to sleep mode. On the other hand, when reading data, the buffer memory 104
The maximum likelihood decoded data stored in the demodulation circuit 215 demodulates the original data from the recording code during the seek time, the disk controller 105 performs error correction processing, and the like, and the magnetic recording / reproducing apparatus transmits the data through the interface 108. Is output.

The operation of the magnetic recording / reproducing apparatus shown in FIG. 4 at the time of writing data will be described below.

In response to the data write request, the MPU 10
The servo control circuit 107 operates in response to the signal from 6, and the magnetic head 109 seeks to the target track.
During this period, the signal processing unit 103 is switched to the sleep mode in which it is stopped or the frequency of the clock is lowered by the signal from the MPU 106. On the other hand, the recording data is converted from a user code to a recording code by the modulation circuit 313 via the interface 108 during the seek time and then input to the disk controller 105, where error correction processing and the like are performed, and the buffer memory is processed. It is stored in 104.

When the seek to the target track of the magnetic head 109 is completed, the write data to the target track stored in the buffer memory 104 is converted into a write signal by the write system signal processing circuit 420, and read / write. Writing is performed on the magnetic recording medium 101 via the amplifier 102 and the magnetic head 109. During this time, the disk controller 105 is switched to a sleep mode in which it is stopped or the frequency of the clock is lowered by a signal from the MPU 106, and the MPU 106 performs addressing of the buffer memory. The address information is notified from the disk controller 105 to the MPU 106 during the seek time of the magnetic head before writing data.

In the magnetic recording apparatus of the embodiment, the demodulation circuit 215, the modulation circuit 313 and the disk controller 105 are set to the sleep mode during the data reading and the data writing, and the signal processing unit 103 is set during the seek of the magnetic head 109. By putting it in sleep mode,
The power consumption of the entire control / signal processing circuit of the magnetic recording / reproducing apparatus can be reduced.

The control and signal processing apparatus for recording / reproducing apparatus of the present invention can be applied to other than magnetic recording / reproducing apparatus such as an optical disk.

[0046]

According to the present invention, the maximum power consumption of the entire control / signal processing circuit of the magnetic recording / reproducing apparatus can be reduced, so that the heat generation amount of the control / signal processing circuit of the magnetic recording / reproducing apparatus can be reduced. It is possible to reduce the chip size when configuring the control / signal processing circuit with an integrated circuit,
Alternatively, the operating frequency can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a control / signal processing circuit of a magnetic recording / reproducing apparatus of the present invention.

FIG. 2 is a block diagram of a read system signal processing circuit of the present invention and a conventional magnetic recording / reproducing apparatus.

FIG. 3 is a block diagram of a write system signal processing circuit of the present invention and a conventional magnetic recording / reproducing apparatus.

FIG. 4 is a block diagram of a second embodiment of the control / signal processing circuit of the magnetic recording / reproducing apparatus of the present invention.

FIG. 5 is a block diagram of a second embodiment of a read system signal processing circuit of the magnetic recording / reproducing apparatus of the present invention.

FIG. 6 is a block diagram of a second embodiment of a write system signal processing circuit of the magnetic recording / reproducing apparatus of the present invention.

FIG. 7 is a block diagram of a control / signal processing circuit of a conventional magnetic recording / reproducing apparatus.

FIG. 8 is a time chart showing the operation of the main part at the time of reading data in an example of the control / signal processing circuit of the conventional magnetic recording / reproducing apparatus.

FIG. 9 is a time chart showing the operation of the main part at the time of data writing in an example of the control / signal processing circuit of the conventional magnetic recording / reproducing apparatus.

FIG. 10 is a time chart showing the operation of the main part at the time of data reading in one embodiment of the control / signal processing circuit of the magnetic recording / reproducing apparatus of the present invention.

FIG. 11 is a time chart showing the operation of the main part at the time of data writing in one embodiment of the control / signal processing circuit of the magnetic recording / reproducing apparatus of the present invention.

[Explanation of symbols]

101 ... Magnetic recording medium, 102 ... Read / write amplifier, 103 ... Signal processing unit, 104 ... Buffer memory,
105 ... Disk controller, 106 ... MPU, 1
07 ... Servo control circuit, 108 ... Interface, 1
09 ... Magnetic head, 110 ... Read system signal processing circuit, 1
20 ... Write system signal processing circuit.

Claims (6)

[Claims] 1. A control unit comprising a signal processing circuit for recording recording data on a recording medium and reproducing digital data from analog data read from the recording medium, a disk controller and an MPU. In a recording / reproducing apparatus that includes a signal processing circuit and reproduces recorded data, a buffer memory is arranged between the signal processing circuit of the control / signal processing circuit and the disk controller to reproduce reproduced digital data. A control and signal processing device for a recording / reproducing device, wherein the signal processing circuit and the disk controller are temporarily stored in the buffer memory and can operate at different clocks. 2. The recording / reproducing apparatus according to claim 1, wherein the signal processing circuit and the disk controller are provided with a sleep mode for lowering a clock frequency. . 3. The recording / reproducing apparatus according to claim 2, wherein when the data is read, the reproduction data output from the signal processing circuit is accumulated in the buffer memory, and the disk controller is set to a sleep mode. Control and signal processing device for recording and reproducing device. 4. The recording / reproducing apparatus according to claim 2, wherein during the seek of the head, the reproduced data accumulated in the buffer memory by the time of the start of the head seek,
A control and signal processing apparatus for a recording / reproducing apparatus, which outputs from the buffer memory and is processed by the disk controller and puts the signal processing circuit into a sleep mode during a seek of the head. 5. The recording / reproducing apparatus according to claim 2, wherein when there is a data write request, the recording data output from the disk controller is recorded in the buffer memory during seek of the head. And a signal processing device for a recording / reproducing device which stores the signal processing circuit in a sleep mode. 6. The recording / reproducing apparatus according to claim 2, wherein when there is a data write request, the recording data accumulated in the buffer memory at the time of head seek is written to the signal after the head seek is completed. A control and signal processing device for a recording / reproducing device which outputs the signal to a processing circuit and puts the disk controller into a sleep mode.