JPH08313875A - Liquid crystal device - Google Patents

Abstract

PURPOSE: To mitigate or suppress a 'burn-in' phenomenon by providing the driving device including a means impressing the information signal having at least three phases on signal lines, a means impressing a DC voltage in between electrodes and a means changing over the polarity of the DC voltage. CONSTITUTION: The scanning selection SS is successively impressed on liquid crystal panels and scanning electrodes whose one pair of substrates are applied with orientation processings made different each other and the information signal constituted of at least three phases is impressed on signal electrodes by making the signal synchronize with the scanning selection signal while selecting at least one scanning electrode. Then, the DC voltage VDC of ±1.5V0 is impressed on scanning electrodes on which the signal SS is not impressed as a scanning non-selection signal SN. Since first and second cycles may be set to the cycle of one frame scannings or to the cycle of the one vertical scanning of the cycle of one frame scannings and or to the cycle of one horizontal scanning, the polarity of the DC voltage VDC can be changed in these cycles.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal panel using a chiral smectic liquid crystal exhibiting a ferroelectric state or both a ferroelectric state and an antiferroelectric state, and a liquid crystal device equipped with a matrix driving device.

[0002]

2. Description of the Related Art In a chevron smectic liquid crystal device having a chevron structure described in US Pat. No. 4,900,132 and US Pat. No. 4,997,264, a tilt angle could not be set to a large value, so that it was applied to a display device. At times, a high-brightness light source was required to generate sufficient display brightness. U.S. Pat. No. 5,377,033 discloses a chiral smectic liquid crystal having a bookshelf structure capable of setting the tilt angle to a large value. The bookshelf structure of the chiral smectic liquid crystal does not develop a cholesteric phase from the isotropic phase when the temperature is lowered, and a smectic A phase is immediately generated from the isotropic phase. Had a problem that uniform alignment could not be obtained. In European Published Specification No. 637622, only one substrate of a pair of substrates forming a chiral smectic liquid crystal panel is subjected to uniaxial alignment treatment such as rubbing treatment or oblique vapor deposition treatment, and the other substrate is treated. It has been clarified that a chiral smectic liquid crystal panel that realizes a bookshelf structure with a uniform alignment state is obtained by using a pair of substrates that have been subjected to a random alignment treatment that does not have uniaxial alignment characteristics.

Also, Keizo Ito, "Journal of Television Society", Vol. 44, No. 5, pp. 536-543
(1990) "Switching between three stable states in antiferroelectric stabilized (AFS) ferroelectric liquid crystal (FLC)".
Applied an alignment control method of imparting polyimide rubbing only to a pair of substrates to a chiral smectic liquid crystal exhibiting an antiferroelectric state and having a temperature range in which a smectic A phase is immediately generated from an isotropic phase under cooling. At that time, it is described that uniform alignment was realized. In addition, this document
It is revealed that the chevron structure is developed when no voltage is applied, and the bookshelf structure is developed when voltage is applied.

[0004]

A liquid crystal panel using a chiral smectic liquid crystal that enables such a high-luminance display has an asymmetric alignment control structure applied to a pair of substrates and a spontaneous polarization of 10 nC. Since it is a chiral smectic liquid crystal of / cm ² or more, a chiral smectic liquid crystal which should generate a plurality of stable alignment states during a display operation by matrix drive has only a single alignment state as a stable alignment state over time. It was found that a phenomenon of changing the orientation state as described above, a so-called "burn-in" phenomenon occurs.

An object of the present invention is to provide a liquid crystal device which can alleviate or suppress the above-mentioned "burn-in" phenomenon.

[0006]

The present invention provides a pair of substrates,
A liquid crystal having a matrix electrode which constitutes a pixel by intersecting a scanning electrode provided on one substrate of the pair of substrates and a signal electrode provided on the other substrate, and a chiral smectic liquid crystal arranged between the pair of substrates. A panel, which is a liquid crystal panel in which the pair of substrates are subjected to different alignment treatments, and a scan selection signal is sequentially applied to the scan electrodes to select at least one scan electrode, and the scan selection is performed. It has means for applying an information signal composed of at least three phases to the signal electrode in synchronization with the signal, means for applying a DC voltage between the scanning electrode and the signal electrode, and means for switching the polarity of the DC voltage. The liquid crystal device having the driving means is characterized.

In the present invention, the driving means has means for applying the DC voltage to the scan electrodes to which the scan selection signal is not applied.

In the present invention, the driving means has means for uniformly applying the DC voltage to the signal electrode.

In the present invention, the DC voltage is a voltage value set in the range of 0.1V _{0 to} 5V ₀ when the maximum voltage value of the information signal is V ₀ .

[0010] In the present invention, the DC voltage, when the maximum voltage value of the information signal is a V _0, preferably 0.5V ₀
It is a voltage value set in the range of up to 3V ₀ .

In the present invention, the driving means has means for switching the polarity of the DC voltage for each vertical scanning period (one frame scanning period or one field scanning period).

In the present invention, the driving means has means for switching the polarity of the DC voltage for each horizontal scanning period.

In the present invention, the information signal has three phases of a first phase, a second phase and a third phase. When the period of the second phase is ΔT, the first phase and the third phase The period is 1/2 · ΔT.

In the present invention, an AC voltage is applied to the pixel on the scanning electrode when scanning is not selected by the information signal received by the pixel, and the time average value of the AC voltage is equal to the voltage value of the DC voltage. I am doing it.

In the present invention, the liquid crystal device in which only one of the pair of substrates is subjected to uniaxial alignment treatment and the other substrate is subjected to non-uniaxial alignment treatment.

In the present invention, the non-uniaxial orientation treatment is random orientation treatment.

In the present invention, the pair of substrates have uniaxial alignment characteristics and have alignment control films formed of different films.

In the present invention, one of the films is an organic film and the other is an inorganic film.

In the present invention, the chiral smectic liquid crystal is a liquid crystal exhibiting a ferroelectric state.

In the present invention, the chiral smectic liquid crystal is a liquid crystal exhibiting a ferroelectric state and an antiferroelectric state.

In the present invention, at least one of the liquid crystal components constituting the chiral smectic liquid crystal has a fluorinated carbon terminal group, and at least one carbon of the fluorinated carbon is completely contained. It is fluorinated.

In the present invention, the chiral smectic liquid crystal has a temperature range in which it produces a smectic A phase from an isotropic phase at a lowered temperature, and at least one kind of liquid crystal components constituting the chiral smectic liquid crystal is fluorine. Has a fluorinated carbon end group, and at least one carbon of the fluorinated carbon is completely fluorinated.

In the present invention, the fluorinated carbon has 2 to 15 carbon atoms.

The present invention will be described below with reference to the drawings.

[0025]

EXAMPLES As a chiral smectic liquid crystal exhibiting a ferroelectric state that can be used in the present invention, at least one liquid crystal component has a fluorinated carbon (eg, fluorinated carbon has 2 to 15 carbon atoms) terminal group. However, a chiral smectic liquid crystal in which at least one carbon of the fluorinated carbon is completely fluorinated is used. Specific examples of such a liquid crystal include the following compositions 1 to 4 described in US Pat. No. 5,377,033.

Composition 1 76.5% 5-octyl-2- (4- (1,1-dihydroperfluoro-2- (2-butoxyethoxy) ethoxy) phenyl) -pyrimidine 4.5% 5-octyl-2 -(4- (1,1-Dihydroperfluorooctyloxy) phenyl) pyrimidine 4.5% 5-nonyl-2- (4- (1,1-dihydroperfluorooctyloxy) phenyl) pyrimidine 4.5% 5-decyl -2- (4- (1,1-dihydroperfluorooctyloxy) phenyl) pyrimidine 10.0% (S) -4- (2-chloro-4-methylpentanonyloxy) phenyl-4- (1,1- Dihydroperfluorobutoxy) benzoate. The transition temperature from the isotropic state (I) to the crystalline state (K) by cooling is I-
73 ° C for SmA, 30 ° C for SmA-SmC ^* and Sm
C ^* -K was -10 degreeC or less.

Hereinafter, SmA represents a smectic A phase, and SmC ^* represents a chiral smectic C phase.

Composition 2 12.44% 5-hexyl-2- (4- (1,1-dihydroperfluoro-2- (2-butoxyethoxy) ethoxy) phenyl) -pyrimidine 20.74% 5-octyl-2 -(4- (1,1-Dihydroperfluorohexyloxy) phenyl) pyrimidine 20.74% 5-nonyl-2- (4- (1,1-dihydroperfluorohexyloxy) phenyl) pyrimidine 20.74% 5-decyl -2- (4- (1,1-dihydroperfluorohexyloxy) phenyl) pyrimidine 8.30% 5-decyl-2- (4- (1,1-dihydroperfluorobutoxy) phenyl) pyrimidine 7.21% (S ) -4- (2-Chloro-4-methylpentanoyloxy) phenyl-4- (1,1-dihydroperfluorobutoxy) ) Benzoate 3.25% 2,3-dicyano-4-octyloxyphenyl-4- (1,1-dihydroperfluorohexyloxy) benzoate 6.58% 2,3-difluoro-4-octyloxyphenyl-4- ( 1,1-Dihydroperfluorohexyloxy) benzoate The transition temperature from the isotropic state (I) to the crystalline state (K) by cooling is 78 ° C. for I-SmA and 5 for SmA-SmC ^*.
9 ° C and SmC ^* -K was 12 ° C.

Composition 3 13.08% 5-hexyl-2- (4- (1,1-dihydroperfluoro-2- (2-butoxyethoxy) ethoxy) phenyl) pyrimidine 23.00% 5-octyl-2- (4- (1,1-Dihydroperfluorohexyloxy) phenyl) pyrimidine 23.00% 5-nonyl-2- (4- (1,1-dihydroperfluorohexyloxy) phenyl) pyrimidine 23.00% 5-decyl- 2- (4- (1,1-dihydroperfluorohexyloxy) phenyl) pyrimidine 9.20% 5-decyl-2- (4- (1,1-dihydroperfluorobutoxy) phenyl) pyrimidine 8.00% (S) -4- (2-chloro-4-methylpentanoyloxy) phenyl-4- (1,1-dihydroperfluoroptoxy Benzoate transition temperature of the cooling from the isotropic state by (I) to the crystalline state (K) is I-SmA is 81 ° C., the SmA-SmC ^* 5
4 ° C and SmC ^* -K was 10 ° C.

Composition 4 90% 5-octyl-2- (4- (1,1-dihydroperfluoro-2- (2-butoxyethoxy) ethoxy) phenyl) pyrimidine 10% 5-octyl-2- (4- ( S)-(2-chloro-4-methylpentanoyloxy) phenyl) pyrimidine The transition temperature from the isotropic state (I) to the crystalline state (K) by cooling is 76 ° C for I-SmA and SmA-SmC ^*. Is 3
0 ° C and SmC ^* -K <-10 ° C.

The chiral smectic liquid crystals exhibiting both the ferroelectric state and the antiferroelectric state that can be used in the present invention include the following compounds.

[0032]

[Outside 1]

[0033]

[Outside 2]

In the above table, Cry is a crystalline phase and SmX is
Unknown phase, is, SmC _A ^*, SmCr ^* and SmC ^*
Is a state of the chiral smectic C phase, is unique spiral array structure expressed in the suppression in chiral smectic C phase, when produced non-helical arrangement state, SmC _A ^* is strongly under-voltage applied state SmC ^* represents a phase in which a dielectric state and an antiferroelectric state under no voltage are applied, and SmC ^* represents a phase in which a ferroelectric state is generated under no voltage is applied. In addition, SmCr ^* represents an unknown phase.

Specific examples of the liquid crystal element exhibiting the antiferroelectric property used in the present invention include US Pat. No. 5,046,823, JP-A-6-95624, and JP-A-6-202078.
Examples thereof include those described in Japanese Patent Publication No. 6-202082 and the like.

FIG. 1 is a sectional view of a liquid crystal panel used in the present invention. 11a and 11b are a pair of crossed Nicols polarizers. Reference numerals 12a and 12b are transparent substrates such as glass substrates, and the distance between the pair of substrates is set to be thin enough (for example, 1 μm to 5 μm) to suppress the formation of a spiral structure unique to chiral smectic liquid crystals. It

Reference numerals 13a and 13b denote a pair of transparent electrodes, one of which is a scanning electrode (scanning line) to which a scanning signal consisting of a scanning selection signal and a scanning non-selection signal is serially applied.
The other is set as a signal electrode (information line) to which an information signal corresponding to information is applied in parallel. The scan electrodes and the signal electrodes intersect each other to form matrix electrodes.

Numerals 14a and 14b are alignment control films forming mutually asymmetric alignment structures. In the first specific example, only the alignment control film 14a is subjected to a uniaxial alignment process such as a rubbing process or an oblique vapor deposition process. Then, the alignment control film 14b is subjected to the alignment treatment in a state where the uniaxial alignment treatment is not performed. For the orientation control film 14a, for example, a rubbing-treated aliphatic polyimide film described in European Patent Publication No. 450549 or a rubbing-treated polyimide film described in US Pat. No. 4,690,089, a polyamide film, A polyamide-imide film, a polyvinyl alcohol film, or the like is used, and as the orientation control film 14b, for example, a laminated film of a SiO ₂ sputtered film described in US Pat. No. 4,662,721 and a baked film of the following organic silane compound or a US patent The non-uniaxially oriented inorganic insulating film described in Japanese Patent No. 4763995 (for example, silicon nitride, silicon carbide, boron nitride, cesium oxide, silicon oxide, magnesium fluoride) can be used. Further, in the present invention, both the orientation control films 14a and 14b can be formed of the same film (for example, the same polyimide film or the same polyamide film).

Specific examples of organic silane compounds

[0040]

[Outside 3]

In the second specific example of the asymmetric alignment structure, the films forming the alignment control films 14a and 14b are different from each other. The different orientation control films 14a and 14b are both subjected to a uniaxial orientation process such as a rubbing process or an oblique vapor deposition process. A rubbing-processed organic film (for example, a polyimide film or a polyamide film) is used for the alignment control film 14a, and a rubbing-treated inorganic film (for example, a baked film of the above-mentioned organic silane compound) is used for the alignment control film 14b. .

Reference numeral 15 is the above-mentioned chiral smectic liquid crystal. In this chiral smectic liquid crystal, the inherent helical structure is suppressed by the interface effect between the pair of substrates 12a and 12b, and as a result, a non-helical structure is formed. In the case where the chiral smectic liquid crystal having the non-helical structure does not exhibit the antiferroelectric state but exhibits the ferroelectric state, it preferably exhibits two stable alignment states, or the chiral smectic liquid crystal exhibits the ferroelectricity. When both the state and the antiferroelectric state are exhibited, preferably three stable orientation states are exhibited. In addition, in the liquid crystal panel in which the above two stable alignment states are generated, the extinction position due to the crossed Nicols of the pair of polarizers 11a and 11b is made to coincide with the molecular axis direction of either one of the stable alignment states. In the liquid crystal panel that produces the above-mentioned three stable alignment states, a pair of polarizers 11a is used.
The extinction positions due to crossed nicols of 11 and 11b are aligned with the average molecular axis direction in the antiferroelectric state, and the antiferroelectric state is dark and the ferroelectric state is bright.

FIG. 2 is a plan view of the matrix electrode structure. The matrix electrode structure is composed of the scanning electrodes 13a (scanning lines S
₁ , S ₂ , S ₃ , S ₄ , S ₅ ...) and the signal electrode 13b
(Information lines I ₁ , I ₂ , I ₃ , I ₄ , I ₅ ...).

FIG. 3 shows the graphics controller 1 provided on the main body side of the ferroelectric liquid crystal display device 101 and the personal computer which is the source of display information.
It is a block diagram of 02. Further, FIG. 4 is a communication timing chart of image information. The liquid crystal panel 103 is
1120 scanning electrodes and 1280 information electrodes are arranged in a matrix, and a ferroelectric liquid crystal is enclosed in two glass plates that have been subjected to orientation processing. The scanning lines are the scanning line driving circuit 104, the information lines. The lines are connected to the information line drive circuit 105, respectively.

The operation will be described below with reference to the drawings. The graphics controller 102 displays the scanning line address information designating the scanning electrodes and the image information (PD0 to PD3) on the scanning lines designated by the address information on the display drive circuit (scanning line drive circuit 104 and information line) of the liquid crystal display device 101. It is configured by the driving circuit 105) and transferred to 104/105. In the present embodiment, the image information having the scanning line address information and the display information is transferred through the same transmission line, so that the two types of information must be distinguished. The signal for this identification is AH / DL, and this AH / DL signal is H
The i level indicates that the information is a scanning line address, and the Lo level indicates that the information is display information.

The scanning line address information is used for the liquid crystal display device 10.
In the drive control circuit side 111 in 1, the image information PD0 to PD0
After being extracted from the image information transferred as 3,
While the designated scan electrode is driven by the scan signal generation circuit 107, the display information is guided to the shift register 108 in the information line drive circuit 105 and is shifted in units of 4 pixels by the transfer clock. When the shift register 108 completes the shift of one scanning line in the horizontal direction, the display information for 1280 pixels is transferred to the line memory 109 provided side by side and stored for one horizontal scanning period, and the information signal is generated. It is output from the circuit 110 to each information electrode as a display information signal.

Further, in the present embodiment, the driving of the liquid crystal panel 103 in the liquid crystal display device 101 and the generation of the scanning line address information and the display information in the graphics controller 102 are performed asynchronously. It is necessary to synchronize (101/102).
The signal that controls this synchronization is SYNC, which is generated in the drive control circuit 111 in the liquid crystal display device 101 every horizontal scanning period. The graphics controller 102 side is always S
The YNC signal is monitored, and if the SYNC signal is at the Lo level, the image information is transferred. On the contrary, when it is at the Hi level, the transfer is not performed after the transfer of the image information for one horizontal scanning line is completed. That is, in FIG. 2, when the graphics controller 102 detects that the SYNC signal has become Lo level, it immediately sets the AH / DL signal to Hi level and starts the transfer of image information for one horizontal scanning line. The drive control circuit 111 in the liquid crystal display device 101 sets the SYNC signal to the Hi level during the image information transfer period. After the writing to the liquid crystal panel 103 is completed after a predetermined horizontal scanning time, the drive control circuit (FLCD controller) 11
1 can return the SYNC signal to the Lo level again and receive the image information of the next scanning line.

5, FIG. 6, FIG. 8 and FIG. 9 show a scanning selection signal (Ss), a scanning non-selection signal (Sn) and an information signal 1 (output from the scanning line driving circuit 104 and the information line driving circuit 105. The voltage waveforms of Is) and 2 (In) are shown.
The voltage of the scanning selection signal is 2V based on the voltage of the scanning non-selection signal. And -2V ₀ with bipolar voltage.

In FIG. 5 and FIG. 6, the first half 2 · ΔT period (voltage 2V ₀ period) of the scan selection signal is used for the erasing period, and the latter half ΔT period (-2V ₀ period). , Is synchronized with the second phase of the information signals 1 and 2 and is used as a writing period. Then, 1 between the erase period and the write period
/ 2 · ΔT period (voltage 2V ₀ period) and the last 1/2
The ΔT period (0 period) is used as an auxiliary signal application period in synchronization with the first and third phases of the information signals 1 and 2.

In FIG. 5, a scanning non-selection signal of ± 1.5 is applied to the scanning electrode to which the scanning selection signal is not applied.
A DC voltage V _{DC of} V ₀ is applied. The first period and the second period in FIG. 5 may be set to one frame scanning period or one field scanning period and one vertical scanning period,
Alternatively, it may be set to one horizontal scanning cycle, so that the polarity of the DC voltage V _DC can be switched in this cycle.

In FIG. 6, a DC voltage V of ± 1.5V _0
DC is uniformly applied to the information electrodes. Also in FIG. 6, the first period and the second period may be set to one vertical scanning period of one frame scanning period or one field scanning period, or one horizontal scanning period. The polarity of the DC voltage V _DC can be switched in this cycle.

(Is-Ss) and (In-Sn) of FIG.
Is the scan selection signal and the information signal 1 of FIGS. 5 and 6, respectively.
And (In-Ss) and (In-
Sn) is a composite waveform of the scanning non-selection signal and the information signals 1 and 2 of FIGS. 5 and 6, respectively. The scan selection signal is
Each scan electrode may be sequentially output to the scan electrodes 13a (non-interlaced scan) or one or more interlaced scan outputs (interlaced scan). Particularly, in the case of repetitive scanning operation, the operation by interlaced scanning output is used. Further, when the display screen is rewritten by the information input from the keyboard, only the scan lines of the rewritable area of the display screen are non-interlaced and the scan lines of the non-rewritable area are interlaced. Is good. Composite waveform (I
The voltage applied during the period 2 · ΔT in s-Ss) and (In-Ss) exceeds one threshold voltage of the chiral smectic liquid crystal, and the pixel on the scanning line has one alignment state (for example, , Corresponding to the dark state), and the writing state during the previous scanning is erased in this period. Further, in the present invention, the erase period is, for example, 1.5ΔT,
It may be 2.5ΔT or 3ΔT or higher. The period ½ · ΔT following the erase period corresponds to the auxiliary signal application period. This auxiliary signal application period is combined with the auxiliary signal application period provided in the last period 1/2 · ΔT so that the voltage waveform applied to the pixel on the scanning line when not selected is an AC voltage waveform. It is provided. The period ΔT set between the two auxiliary signal application periods corresponds to the writing period, and the selectively applied voltage 3V ₀ is a voltage exceeding the other threshold voltage of the chiral smectic liquid crystal, The voltage V ₀ that causes the other alignment state (for example, corresponding to the bright state) or is selectively applied to another pixel does not exceed the threshold voltage of the chiral smectic liquid crystal, and the alignment state during the erase period Is retained as is.

FIGS. 8 and 9 show another specific example, which is the last 1 / 2.Δ of the scan selection signal shown in FIGS. 5 and 6.
The drive waveform is the same as that of FIGS. 5 and 6 except that the voltage waveform is changed to the voltage V ₀ applied during the period T. By using the scan selection signal having such a voltage waveform, the driving margin during display driving can be increased. FIG. 10 shows a composite voltage waveform when the drive waveforms shown in FIGS. 8 and 9 are used.

11 and 12 are time-series waveform charts when the scan selection signal of FIG. 5 is output to the scan electrodes. FIG.
In the second specific example, even if the number of scanning lines is 1000 or more,
It can be driven at a high frame frequency (for example, 15 Hz or higher). Further, in the specific example of FIG. 12, two continuous scan selection signals are partially overlapped and output to different scan electrodes, and as a result, the period when the voltage of the information signal is zero is omitted. Further, in the time-series waveforms of FIGS. 11 and 12, a DC voltage V _DC is applied as a scanning non-selection signal,
An AC voltage equal to the _DC voltage value V _{DC on} a time average is applied to the pixels on the scan electrodes when scanning is not selected, and the polarity is inverted every frame scanning period.

13 and 14 are time-series waveform charts when the scan selection signal of FIG. 6 is output to the scan electrodes. FIG.
In the specific example of 4, even if the number of scanning lines is 1000 or more,
It can be driven at a high frame frequency (for example, 15 Hz or higher). Further, in the specific example of FIG. 14, two continuous scan selection signals are partially overlapped and output to different scan electrodes, and as a result, the period when the voltage of the information signal is zero is omitted. Further, in the time-series waveforms of FIGS. 13 and 14, a DC voltage V _DC is applied as a scanning non-selection signal,
An AC voltage equal to the _DC voltage value V _{DC on} a time average is applied to the pixels on the scan electrodes when scanning is not selected, and the polarity is inverted every frame scanning period.

[0056]

According to the present invention, even if the spontaneous polarization of the chiral smectic liquid crystal is 10 nC / cm ² or more, a "burn-in" with time occurs when a display operation by matrix driving is performed for a long time. The occurrence of the phenomenon could be sufficiently mitigated or suppressed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a chiral smectic liquid crystal panel used in the present invention.

FIG. 2 is a plan view of a matrix electrode structure used in the present invention.

FIG. 3 is a block diagram of the device of the present invention.

FIG. 4 is a timing chart of image information communication used in the present invention.

FIG. 5 is a diagram of drive waveforms used in the present invention.

FIG. 6 is a diagram of another drive waveform used in the present invention.

FIG. 7 is a composite waveform diagram based on the drive waveforms shown in FIGS. 5 and 6 used in the present invention.

FIG. 8 is a diagram of another drive waveform used in the present invention.

FIG. 9 is a diagram of another drive waveform used in the present invention.

FIG. 10 is a composite waveform chart based on FIGS. 8 and 9 used in the present invention.

11 is a time-series waveform chart when the drive waveform of FIG. 5 is used.

FIG. 12 is another time-series waveform diagram when the drive waveform of FIG. 5 is used.

FIG. 13 is a time-series waveform diagram when the drive waveform of FIG. 6 is used.

14 is another time-series waveform diagram when the drive waveform of FIG. 6 is used.

Front page continued (72) Inventor Hironao Kimura 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Kazunori Katakura 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. Within

Claims (19)

[Claims] 1. A pair of substrates, a matrix electrode which constitutes a pixel by intersecting a scanning electrode provided on one substrate of the pair of substrates and a signal electrode provided on the other substrate, and between the pair of substrates. A liquid crystal panel having a chiral smectic liquid crystal arranged in a pair, wherein the pair of substrates are subjected to different alignment treatments, and a scan electrode is sequentially applied with a scan selection signal to perform at least one scan. Means for selecting an electrode and applying an information signal composed of at least three phases to the signal electrode in synchronization with the scanning selection signal, means for applying a DC voltage between the scanning electrode and the signal electrode, and the DC A liquid crystal device having driving means having means for switching the polarity of voltage. 2. The liquid crystal device according to claim 1, wherein the driving means has means for applying the DC voltage to the scan electrodes to which the scan selection signal is not applied. 3. The liquid crystal device according to claim 1, wherein the driving means has means for uniformly applying the DC voltage to the signal electrode. 4. The liquid crystal device according to claim 1, wherein the DC voltage is a voltage value set in a range of 0.1V _{0 to} 5V ₀ when a maximum voltage value of the information signal is V ₀ . 5. The liquid crystal device according to claim 1, wherein the DC voltage is a voltage value set in a range of 0.5V _{0 to} 3V ₀ when a maximum voltage value of the information signal is V ₀ . 6. The liquid crystal device according to claim 1, 2 or 3, wherein the driving means has means for switching the polarity of the DC voltage for each vertical scanning period. 7. The liquid crystal device according to claim 1, wherein the driving means has means for switching the polarity of the DC voltage for each horizontal scanning period. 8. The information signal has three phases of a first phase, a second phase and a third phase, and a period of the second phase is ΔT.
, The period of the first phase and the third phase is 1
The liquid crystal device according to claim 1, wherein the liquid crystal device has a value of / 2 · ΔT. 9. An AC voltage is applied to the pixel on the scan electrode when scanning is not selected by the information signal received by the pixel, and the time average value of the AC voltage is equal to the voltage value of the DC voltage. The liquid crystal device according to claim 1. 10. The liquid crystal device according to claim 1, wherein only one substrate of the pair of substrates is subjected to uniaxial alignment treatment, and the other substrate is subjected to non-uniaxial alignment treatment. 11. The liquid crystal device according to claim 10, wherein the non-uniaxial alignment process is a random alignment process. 12. The liquid crystal device according to claim 1, wherein the pair of substrates have uniaxial alignment characteristics and have alignment control films formed of different films. 13. The liquid crystal device according to claim 12, wherein one of the films is an organic film and the other is an inorganic film. 14. The liquid crystal device according to claim 1, wherein the chiral smectic liquid crystal is a liquid crystal exhibiting a ferroelectric state. 15. The chiral smectic liquid crystal is a liquid crystal exhibiting a ferroelectric state and an antiferroelectric state.
The liquid crystal device described. 16. Among the liquid crystal components constituting the chiral smectic liquid crystal, at least one liquid crystal component has a fluorinated carbon terminal group, and at least one carbon of the fluorinated carbon is completely fluorinated. The liquid crystal device according to claim 1. 17. The number of carbon atoms of the fluorinated carbon is 2 to
The liquid crystal device according to claim 16, which is 15. 18. The chiral smectic liquid crystal has a temperature range in which an isotropic phase to a smectic A phase is generated when the temperature is lowered, and at least one of the liquid crystal components constituting the chiral smectic liquid crystal is fluorinated carbon. The liquid crystal device according to claim 1, wherein the liquid crystal device has an end group, and at least one carbon in the fluorinated carbon is completely fluorinated. 19. The number of carbon atoms of the fluorinated carbon is 2 to
The liquid crystal device according to claim 18, which is 15.