JPH0831178A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To suppress increasing of power consumption by operating a sense amplifier provided for amplifying a read-out signal of a common data-line to which a bit line is connected through a transfer gate with power supply voltage. CONSTITUTION:In a control circuit 22, an input signal of a terminal 23a is made a H level, an input signal of a terminal 23b is made a L level, and a memory mat block is selected. Then, a signal line controlling gate electrodes of (n) type MOS transistors Q9, Q10 connected to a power supply terminal 3 of which a source electrode is 0V is made approximately 0.5Vcc, pairs of bit line 4a, 4b are previously charged to approximately 0.5Vcc by transistors Q', Q9 and Q8, Q10 of a control circuit 20. In a non-selection memory mat block, an input signal of the terminal 23a is made a L level, an input signal of the terminal 23b is made a H level, a signal line 21 is made a L level, and pairs of bit lines 4a, 4b are previously charged to approximately Vcc. Thereby, a DC current flowing between a terminal 1 and 3 is cut off, and power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static semiconductor memory device which requires low voltage operation.

[0002]

2. Description of the Related Art FIG. 7A shows a bit line voltage level during a read operation in the prior art. In the bit line precharge operation performed prior to the read operation, the bit line is the power supply voltage Vcc of the memory cell or the n-type MO.
Voltage Vc that is lower than the threshold voltage Vth of the S transistor
It was precharged to c-Vth and the bit line read signal voltage level was designed to be near the precharge voltage.

Reference numerals 60 and 61 shown in FIG. 8 connect bit line pairs 44a and 44b to power supply voltages Vcc and Vcc-, respectively.
A bit line voltage control circuit that precharges to Vth.

FIG. 7B shows a memory mat portion. A memory cell array in which memory cells 51 each including a flip-flop (FF) using a high resistance, polysilicon PMOS, or a PMOS transistor formed on a substrate as a load element and a transfer MOS transistor are arranged in M rows and N columns. ,
M word lines 48 for selecting memory cells in the column direction and M word line driving circuits 47 for selecting word lines;
Bit line pairs 44a and 44b for writing and reading information to and from the memory cells, and N transfer gate pairs 45a and 45b for selecting bit lines in the row direction, and a bit line voltage provided for each bit line pair. Control circuit 4
2 and complementary signal lines 50a and 50b for controlling the bit line voltage control circuit, and a common data line pair 49a and 49b to which a plurality of bit lines are connected via a transfer gate.
And a group of sense amplifiers 46 for amplifying a read signal.

In the prior art, when it is assumed that high information is written in storage node N3 in memory cell 51 and row information is written in N4, bit lines 44a and 44b are transferred from power supply voltage Vcc to transfer MOS transistors Q30 and Q3.
After precharging to a voltage lower than the threshold voltage Vth of 1 or more and then Vcc is applied to the word line 48 to start the read operation for the memory cell 51, the transfer MO is transferred.
When the S transistor Q30 is turned on, a current flows from the high node N3 to the bit line, the voltage of the high storage node N3 drops, and the stored information in the memory cell 51 is destroyed. This is because, in the high resistance cell or the poly-PMOS cell, the current that can be supplied to the high storage node N3 by the high resistance and the polysilicon PMOS which are load elements is smaller than the leak current of the transfer MOS transistor. However, increasing the high resistance and the current supply capacity of the poly-PMOS is not realistic because it increases the standby current of the entire memory array section.

Even in a full CMOS cell in which a PMOS transistor formed on a substrate is used as a load element, when the power supply voltage Vcc is about 5 V, the power consumption due to the leak current from the high node to the bit line is large, and the leak current is large. However, the p-type MOS transistor, which is a load element capable of supplying a sufficiently large current to the high node N3, has the drawback of increasing the cell area and is not realistic. Therefore, the bit line voltage during reading is set to 0.
Designing to about 5 Vcc is practically impossible.

On the other hand, in low power supply voltage operation of 3.3 V or less, the fact that the bit line read signal voltage level in the prior art is close to Vcc causes the sensitivity of the sense amplifier to decrease and the access time to increase. Has become. Furthermore, in the read operation performed after the end of the write operation, the read operation for the memory cell cannot be performed during the period in which the bit line having the voltage of about 0 V extracted during the write operation is precharged to near Vcc, and the write operation required for the precharge operation is not performed. The recovery time is a constraint for increasing the cycle of static memory operation.

[0008]

The present invention is based on the fact that the bit line precharge voltage level and the read signal voltage level are designed in the vicinity of the power supply voltage Vcc in the low voltage operation of the power supply voltage 3.3 V or less. It is an object to reduce an increase in sense time and to reduce a write recovery time during a write operation to realize a high speed access and a high cycle operation of a static memory.

[0009]

A driving element for a memory cell,
The above problem is solved by forming the transfer element and the load element from MOS transistors and setting the voltage of the bit line to about 1/2 of the power supply voltage Vcc during reading.

[0010]

By designing the bit line voltage at the time of reading to be about 0.5 Vcc, the sense amplifier can be operated in a high sensitivity region, and high speed operation becomes possible. Further, it has an effect of reducing the write recovery time of the bit line after the end of the write operation and enabling a high cycle operation.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is shown in FIGS. FIG. 1A shows the bit line voltage level during the read operation. The bit line voltage level during read operation is 3.
0.5 Vcc ± 0.5 for power supply voltage Vcc of 3 V or less
Design within the V range.

FIG. 1B shows the configuration around the memory mat portion. The memory mat portion has M rows and N rows of memory cells 11 each including four n-type MOS transistors which are drive elements Q1 and Q2, transfer elements Q3 and Q4, and two p-type MOS transistors which are load elements Q5 and Q6. There are M memory cell array portions arranged in columns, M word lines 8 for selecting memory cells in the column direction, and M word line driving circuits 7 for selecting word lines, for writing and reading information to and from the memory cells. Bit line pair 4a, 4b and transfer gate pair 5a, 5b for selecting a bit line in the row direction
, N, complementary signal lines 10a and 10b for controlling the bit line voltage control circuit 2 and the bit line voltage control circuit provided in each bit line pair, and a plurality of bit lines are connected via a transfer gate. Common data line pair 9a, 9b
And a group of sense amplifiers 6 for amplifying a read signal. Reference numeral 1 is a power supply terminal of voltage Vcc, and 3 is a power supply terminal of voltage 0V.

Reference numeral 20 shown in FIG. 2A is a bit line voltage control circuit for realizing the bit line voltage level shown in FIG. 22 is a control circuit provided for each memory mat block, and the input signal of the terminal 23a becomes high and the terminal 2
When the input signal of 3b becomes low and the memory mat block is selected, the signal line 21 for controlling the gate electrodes of the n-type MOS transistors Q9 and Q10 connected to the power supply terminal 3 whose source electrode is 0V is set to 0. It becomes about 5 Vcc, and the bit line pair 4a, 4b is set to 0.5 Vcc by the MOS transistors Q7 and Q9 and Q8 and Q10 of the control circuit 20.
It is precharged to the extent.

In the non-selected memory mat block, terminal 2
The input signal of 3a is low, the input signal of the terminal 23b is high, the signal line 21 is low, and the bit lines 4a and 4b are low.
Precharged near Vcc. Therefore, in the non-selected memory mat block, the DC current flowing between the power supply terminals 1 and 3 of the control circuit 20 is cut off, and the power consumption is reduced.

Reference numeral 24 shown in FIG. 2 (b) is a second bit line voltage control circuit for realizing the bit line voltage level shown in FIG. 1 (a). Bit lines 4a and 4b are set to 0.5 by MOS transistors Q17 and Q20 and Q19 and Q22.
Precharged to Vcc. At this time, the DC current flowing between the power supply terminals 1 and 3 of the bit line voltage control circuit 24 is from the power supply terminal 1 to the resistor R1 and the MOS transistor Q1.
It is determined by the current flowing through the power supply terminal 3 via 8, Q21 and the resistor R2, and can be made smaller than that during the operation of the control circuit 20 by appropriately selecting R1 and R2, so that the power consumption can be reduced. .

FIG. 3 shows operation signal waveforms of the word line and the bit line. The write operation 30 in which the voltage of the pair of bit lines becomes almost 0 V and Vcc is completed, and the bit line pair 4a, 4b is equalized with the equalize control signals 10a, 1 during the period 31.
Almost at the same time when Q11 and Q12 or Q23 and Q24 are turned on by 0b to be at the same potential, the bit line precharge operation causes 0.5V.
It is precharged to the cc level, and then the stored information of the memory cell is read in the period 32. At this time, the voltage of the bit line on the row storage node side of the memory cell drops due to the drawing current of the memory cell, and the voltage of the bit line on the high storage node side rises due to the charging current of the memory cell. A period 33 is a bit line signal waveform in the case where the memory cells storing the reverse information to the read information in the period 32 are continuously read.

FIG. 4 shows the static noise margin (SNM) of the memory cell in this embodiment. The vertical axis represents the static noise margin of this embodiment (Vbit = 0.5Vc
c) is shown as a relative value with respect to the prior art (Vbit = Vcc), and the horizontal axis shows the memory cell power supply voltage and the word line voltage V
It is cc. M drive element, transfer element, and load element
The full CMOS cell composed of OS transistors includes a high resistance cell using a high resistance as a load element and a poly PMOS using a polysilicon PMOS transistor as a load element.
Unlike the cell, Vcc = 3.3V,
60% of it = Vcc), 80% at Vcc = 2.5V,
When Vcc = 1.5V, it has a noise margin of almost 100%, and the noise margin recovers as the voltage becomes lower.

Further, FIG. 5 shows the present embodiment (Vbit = 0.5).
The absolute value of the static noise margin of Vcc) is set to full C
The results of comparison between a MOS cell, a poly-PMOS cell, and a high resistance cell are shown. Even when the bit line precharge voltage level during reading is 0.5 Vcc, the full CMOS cell has a larger noise margin than the high resistance cell and the poly-PMOS cell, and the low voltage up to the power supply voltage of about 1.5 V. The noise margin increases with the increase in the number.

FIGS. 4 and 5 show that in a full CMOS cell, when the bit line precharge voltage level is designed to be 0.5 Vcc at a power supply voltage of 3.3 V or less, a noise margin necessary for stable operation of the memory cell can be secured. Shows.

FIG. 6 shows the relationship between the input signal level and the gain in the current mirror type sense amplifier. The gain sharply decreases as the input signal level approaches the low level or the high level of the power supply voltage. Therefore, by designing the input signal level to about 0.5 Vcc,
1 compared to the prior art in which the input signal level is near Vcc
It is possible to operate with a gain of 0 times or more. In the present embodiment, the precharge voltage level and the read signal voltage level of the common data lines 9a and 9b are set to the bit line 4a,
By setting it to about 0.5 Vcc as in the case of 4b, the sense amplifier 6 operating at the power supply voltage Vcc can be operated in a high gain state.

FIG. 9 shows a second embodiment of the present invention. Reference numeral 70 denotes a static memory chip. The voltage Vcc is supplied between the external power supply terminals 71 and 72, and the voltage conversion circuit 73 generates 0.5 Vcc with respect to the external voltage Vcc. Indicated by 74 is 0 V, 75 is 0.5 Vcc, and 76 is Vcc in-chip power supply wiring. The peripheral circuit section 77 such as a decoder is supplied with 0V and Vcc, and the memory mat section 78 is supplied with 0V, Vcc and 0.5Vcc from the voltage conversion circuit, which is used as a bit line precharge voltage. And the bit line voltage during reading is 0.
It is designed to be maintained at about 5Vcc.

FIG. 10 shows a third embodiment of the present invention. The circuit system 80 is composed of a plurality of arithmetic units 88 and 89 and a plurality of static memory units 87 and 90, and a voltage Vcc is supplied between external power supply terminals 81 and 82. The voltage conversion circuit 83 supplies 0 V to the power supply line 84 in the system, 0.5 Vcc to 85, and Vcc to 86, so that the arithmetic unit group and the static memory unit group in the system have the voltage required by each unit. Is being supplied.
For example, 0 V and Vcc are supplied to the arithmetic unit 89,
0V, 0.5Vcc and Vcc are supplied to the static type memory devices 87 and 90 and the arithmetic processing device 88,
The static memory device uses 0.5 Vcc as a bit line precharge voltage, and is designed to hold the bit line voltage at the time of reading at about 0.5 Vcc.

FIG. 11 shows a fourth embodiment of the present invention. Reference numeral 100 indicates a static memory chip. 10
1, 102 and 103 are external power supply terminals, 0 V,
The voltages of 0.5 Vcc and Vcc are supplied from the outside. The peripheral circuit 104 such as a decoder is supplied with 0V and Vcc, and the memory mat section 105 is supplied with 0V, Vcc and 0.5Vcc, which is used as a bit line precharge voltage and is used as a bit line voltage at the time of reading. 0.
It is designed to be maintained at about 5Vcc.

FIG. 12 shows a memory array portion in the static type memory in the second, third and fourth embodiments of the present invention. Vc is applied to the power supply terminals 114 and 115, respectively.
A power supply voltage of c, 0 V is supplied, a voltage of 0.5 Vcc is supplied to the source terminals 110 of the p-type MOS transistors Q40, Q41, which are load elements of the bit line, and the bit line pair 116a, 116b has a voltage of Q40, It is designed to be precharged to 0.5 Vcc by Q41 and hold the bit line voltage at the time of reading at about 0.5 Vcc. 111 and 112 are bit line equalize control signal terminals, and 113 is a word line.

[0025]

According to the present invention, in a static memory that operates at a low voltage of 3.3 V or less, the effect of reducing the access time, enabling a high cycle operation, and increasing the power consumption accompanying a high cycle are achieved. Suppress.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a bit line voltage level and a memory mat portion in a first embodiment.

FIG. 2 is a bit line voltage control circuit diagram in the first embodiment of the present invention.

FIG. 3 is a waveform diagram of an operation signal in the first embodiment of the present invention.

FIG. 4 is a diagram illustrating an SNM (Vbi) according to the first embodiment of the present invention.
t = 0.5 Vcc) and SNM (Vbi in the prior art)
The characteristic view of the power supply voltage dependence of the relative ratio of t = Vcc).

FIG. 5 shows SNM (Vbi in the first embodiment of the present invention.
The characteristic view of the power supply voltage dependence of t = 0.5 Vcc).

FIG. 6 is a characteristic diagram of input signal level dependency of current mirror type sense amplifier gain in the first embodiment of the present invention.

FIG. 7 is an explanatory diagram of a bit line voltage level and a memory mat portion in the conventional technique.

FIG. 8 is a conventional bit line voltage control circuit diagram.

FIG. 9 is an explanatory diagram of the second embodiment of the present invention.

FIG. 10 is an explanatory diagram of the third embodiment of the present invention.

FIG. 11 is an explanatory diagram of the fourth embodiment of the present invention.

FIG. 12 is an explanatory diagram of a memory cell array portion in the second, third and fourth embodiments of the present invention.

[Explanation of symbols]

1 ... Power supply voltage Vcc terminal, 2 ... Bit line voltage control circuit,
3 ... GND terminal, 4a, 4b ... Bit line, 5a, 5b ...
Transfer gate, 6 ... Sense amplifier, 7 ... Word line drive circuit, 8 ... Word line, 9a, 9b ... Common data line, 10a, 10b ... Bit line voltage control circuit control signal line, 11 ... Memory cell.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Koichiro Ishibashi 1-280 Higashi Koikeku, Kokubunji, Tokyo Metropolitan Research Center, Hitachi Ltd. (72) Masataka Minami 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Institute (72) Inventor Kiyotsugu Ueda 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Institute (72) Inventor Kunihiro Komiji 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi Central Research Institute (72) Inventor Takahiro Nagano 1-280, Higashi Koigokubo, Kokubunji, Tokyo, Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Hiroshi Toyoshima 5-2-1, Kamisuihonmachi, Kodaira-shi, Tokyo I Engineering Co., Ltd.

Claims (8)

[Claims] 1. A drive element, a transfer element, and a load element are M
A static memory having a memory cell composed of an OS transistor, at least a memory cell and a word line selecting the memory cell operating at a power supply voltage Vcc, and writing information to a storage node of the memory cell,
Alternatively, two transfer M provided for reading
The potentials of the pair of bit lines connected to the diffusion layer region, which is the source electrode or drain electrode of each OS transistor, are the same as the power supply voltage Vcc at the time of reading the memory cell storage information, and the transfer MOS transistor constituting the memory cell. Threshold voltage V of a certain n-type MOS transistor
A sense amplifier, which has a potential lower than Vcc-Vth with respect to th and is provided for amplifying a read signal of the bit line or a common data line to which the bit line is connected via a transfer gate, is the power supply voltage. V
A semiconductor memory device operating in cc. 2. The drive element, the transfer element, and the load element are M
A static memory having a memory cell composed of an OS transistor, at least a memory cell and a word line selecting the memory cell operating at a power supply voltage Vcc, and writing information to a storage node of the memory cell,
Alternatively, two transfer M provided for reading
The potentials of the pair of bit lines connected to the diffusion layer region, which is the source electrode or the drain electrode of each OS transistor, are higher than the low-potential side potential of the power supply voltage and lower than the high-potential side potential when the memory cell storage information is read. Potential, 0.5Vcc-0.5V or more, 0.5Vcc + 0.5V
In the following range, a sense amplifier provided for amplifying a read signal of the bit line or a common data line to which the bit line is connected via a transfer gate operates at the power supply voltage Vcc. Semiconductor memory device. 3. The drive element, the transfer element, and the load element are M
A static memory having a memory cell composed of an OS transistor, at least a memory cell and a word line selecting the memory cell operating at a power supply voltage Vcc, and writing information to a storage node of the memory cell,
Alternatively, two transfer M provided for reading
The potentials of the pair of bit lines connected to the diffusion layer region, which is the source electrode or drain electrode of each OS transistor, are the same as the power supply voltage Vcc at the time of reading the memory cell storage information, and the transfer MOS transistor constituting the memory cell. Threshold voltage V of a certain n-type MOS transistor
A semiconductor memory device having a potential lower than Vcc-Vth with respect to th. 4. The drive element, the transfer element, and the load element are M
A static memory having a memory cell composed of an OS transistor, at least a memory cell and a word line selecting the memory cell operating at a power supply voltage Vcc, and writing information to a storage node of the memory cell,
Alternatively, two transfer M provided for reading
The potentials of the pair of bit lines connected to the diffusion layer region, which is the source electrode or the drain electrode of each OS transistor, are higher than the low-potential side potential of the power supply voltage and lower than the high-potential side potential when the memory cell storage information is read. Potential, 0.5Vcc-0.5V or more, 0.5Vcc + 0.5V
A semiconductor memory device characterized by being in the following range. 5. The drive element, the transfer element, and the load element are M
A static type memory having a memory cell composed of an OS transistor, wherein a source electrode or a drain of each of two transfer MOS transistors provided for writing or reading information to or from a storage node of the memory cell The potentials of the pair of bit lines connected to the diffusion layer regions, which are electrodes, amplify the read signal of the bit line or the common data line to which the bit line is connected via the transfer gate when the memory cell storage information is read. The power supply voltage Vcc for operating the sense amplifier is higher than the low-potential side potential and lower than the high-potential side potential, and is 0.5 Vcc-0.5 V or more, 0.5 Vcc
A semiconductor memory device characterized by being in a range of +0.5 V or less. 6. The method according to claim 1, 2, 3, 4 or 5.
During reading, the potential of the common data line to which the bit line is connected via a transfer gate is higher than the low potential side potential of the power supply voltage Vcc for operating the memory cell, the word line or the sense amplifier, and the high potential side potential. Lower potential, 0.5Vcc-0.5V
Above, a semiconductor memory device in the range of 0.5 Vcc + 0.5 V or less. 7. The semiconductor memory device according to claim 1, 2, 3, 4, 5 or 6, wherein the power supply voltage Vcc is 3.3 V or less. 8. A semiconductor memory device according to claim 7, which is a static type memory having memory cells composed of six MOS transistors formed on a substrate.