JPH0831170A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit device capable of reducing the power consumption of a dynamic RAM and capable of making the data processings of a microprocessor efficient. CONSTITUTION:This device has a storage bit corresponding to the refreshing address of the dynamic RAM and also a refreshing address counter generating a refreshing address by a refreshing starting signal made to be corresponded to the refreshing cycle of the dynamic RAM and performs the recording of a memory access when the memory access is performed to the storage circuit. Then, the device reads out a storage bit corresponding to an address in which a refresh is to be performed by the refreshing starting signal and the refreshing address signal and when the recording of the memory access is present, the device allows only the refereshing address to be updated by making a refreshing control signal ineffective and also allows the recording to be cleared and besides when the recording of the memory access is not present, the device allows a refreshing operation to be performed in the address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a microprocessor or a dynamic type RAM (random
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device such as an access memory).

[0002]

2. Description of the Related Art As shown in FIG. 6, refresh for generating a refresh cycle at regular intervals.
There is a microprocessor with a controller. Alternatively, there is a dynamic RAM in which a built-in timer circuit automatically performs a refresh operation at regular intervals. Regarding the microprocessor with the refresh controller as described above, for example,
H8 / 500 series sold by Hitachi,
There are H8 / 300 series microprocessors.

[0003]

The inventor of the present application, when a memory access to a dynamic RAM is performed, a substantial refresh operation is performed on a memory cell connected to a word line selected by the memory access. Focusing on the fact that the dynamic RAM is used, the power consumption of the dynamic RAM and the efficiency of data processing in the microprocessor accessing the dynamic RAM are considered.

An object of the present invention is a dynamic RAM.
Another object of the present invention is to provide a semiconductor integrated circuit device capable of reducing the power consumption and improving the efficiency of data processing of a microprocessor. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor integrated circuit device including at least a central control unit or a dynamic RAM that performs data processing according to a program, a memory circuit having a memory bit corresponding to a refresh address of the dynamic RAM and a refresh cycle of the dynamic RAM are supported. And a refresh address counter for generating a refresh address by a refresh activation signal, and when the memory access is made to the memory circuit, the recording is performed, and the refresh activation signal and the refresh address signal are used for the memory circuit. When the memory bit corresponding to the address to be refreshed is read out and the memory access record exists, the refresh control signal is invalidated and only the refresh address is updated. Clear the recording, when the recording of the memory access does not exist providing a refresh control circuit comprising Toka control circuit to perform a refresh operation according to the refresh address signal and the refresh control signal.

[0006]

According to the above-mentioned means, the refresh for the word line which has been accessed can be omitted.
The power consumption of the dynamic RAM is reduced, and the dynamic RA is also used in the microprocessor.
The waiting time of the refresh period of M is reduced, and the efficiency of data processing can be improved.

[0007]

1 is a schematic block diagram of an embodiment of a microprocessor according to the present invention. In the figure, as a microprocessor, a central processing unit CPU is represented by a black box as a representative, and each of the following circuit blocks is formed by a known semiconductor integrated circuit manufacturing technique into one semiconductor such as single crystal silicon. It is formed on a chip (CHIP).

The refresh controller is composed of the following circuit blocks. The RAM is composed of a dynamic RAM, although not particularly limited. The reason for this is that, as described below, the memory access for writing or reading is always performed to the RAM in a constant cycle, and the substantial refresh operation can be made unnecessary.

The RAM has a storage capacity corresponding to the refresh address. For example, when the refresh cycle of the dynamic RAM connected to the microprocessor is 1024,
It has a storage capacity of 4 bits. The RAM is composed of a memory array of 128 words × 8 bits, a word line selection circuit and a column selection circuit for selecting the memory array, although not particularly limited. However, the column selection circuit is used only when a memory access is recorded and a write operation such as a clear operation during a refresh operation, and 8 bits are read in parallel during a read operation described later.

The latch circuit and the adder constitute a refresh address counter, and form a 10-bit address signal corresponding to a refresh address of 1024. The refresh address signal held in the latch circuit and the address signal corresponding to the refresh address among the address signals output from the central processing unit CPU are the multiplexer MU.
It is supplied to the RAM through X2. Of the 10-bit refresh address signal, 7 bits are used for word line selection, and the remaining 3 bits are used for column switch selection.

The timer circuit forms a refresh start signal corresponding to the refresh cycle. Although not particularly limited, the timer circuit is the central processing unit C.
A system clock supplied to the PU is divided to form a refresh activation signal. That is, the refresh activation signal is formed so that 1024 cycles correspond to the information holding time of the dynamic memory cell.

In this embodiment, 128 cycles correspond to the information holding time of the dynamic type memory cell, corresponding to the fact that the memory circuit RAM is read in units of 8 bits in order to perform efficient refresh control. Thus, a low-frequency divided signal and a high-frequency divided signal corresponding to one refresh operation are formed. By combining the two kinds of frequency-divided signals as described above, the first refresh activation signal corresponding to 128 cycles is used to read out 8 bits from the memory circuit RAM, and thereafter, seven consecutive times are performed by the high-frequency frequency-divided signal. Form a second refresh activation signal consisting of

The control circuit receives the first refresh activation signal from the timer circuit as described above and adds +1 to the adder.
Is added to the latch circuit and the multiplexer MUX2 is switched to access the memory circuit RAM to read 8-bit memory information and transfer it in parallel to the shift register. If the storage bit at the head of the shift register is set (“1”), it is determined that memory access has been performed to the refresh address, the refresh request signal is invalidated, and 0 is written and cleared according to the selected bit.

If the memory bit is clear ("0"), a refresh request signal is output and the row address strobe (RAS) of the dynamic RAM is output from the control pin via the bus controller (Bus-Control).
The control signal corresponding to the 9 signal is set to low level, and the refresh address signal is output from the address pin by switching the multiplexer MUX1. That is, the RAS only refresh operation is performed on the dynamic RAM. Thereafter, the refresh address is updated and the shift register is shifted by the second refresh activation signal composed of the high frequency divided signal to correspond to the set state / cleared state of the bit, and the above operation is repeated seven times. And do it.

When a memory access for writing or reading to the dynamic RAM is performed by the central processing unit CPU at a time other than the above refresh operation,
The control circuit is activated by the bus cycle request signal,
The multiplexer MUX2 is switched to perform the memory access, "1" is written in the memory cell of the address, and the memory access is recorded at the address.

FIG. 5 shows the CP with the above refresh function.
A block diagram of an embodiment of an information processing system using U is shown. That is, centering on such a CPU, ROM via the address bus, data bus, and control bus
(Read-only memory), DRAM (dynamic RAM) and I / O device are connected. R above
A program indicating a procedure of data processing by the CPU and a pattern such as characters are written in the OM. DRA
M is used for temporary storage for data processing.
The I / O device includes a display device, its control circuit, a key input circuit, and the like.

As described above, the CPU and the refresh control circuit incorporated therein acquire the external bus as described above to access the DRAM. For this reason,
For efficient CPU data processing, how efficiently the refresh operation of the DRAM is performed is important. That is, if the refresh operation (burst refresh) is continuously performed for 1024 cycles within the information holding time of the dynamic memory cell, the CPU gives up the bus during that time and the data processing is interrupted. For this reason, there arises a problem that the data processing is delayed every refresh cycle. On the contrary, if the refresh operation is performed by dividing the information holding time of the dynamic memory cell into 1/1024 equal parts,
The bus is handed over only 24 times, and the time during which no operation is performed substantially increases, resulting in poor efficiency.

In this embodiment, as described above, the first refresh start signal which divides the information holding time of the dynamic type memory cell into 128 equally, and 7 times excluding the first refresh start in each cycle. So-called intermittent burst refresh is performed by the continuous second refresh activation signal. As a result, the number of times the bus is transferred between the CPU and the refresh control circuit is reduced, and at the same time, efficient data processing can be performed without the adverse effect of the refresh control circuit monopolizing the external bus for a long time. .

This brings an advantage also in the refresh control circuit. In other words, the memory circuit RAM provided in the refresh control circuit can read the recording of eight refresh addresses by one reading, which can reduce the access to the memory circuit RAM and can make a memory of eight cycles in advance. This is because it is possible to judge the record of recycling.

FIG. 2 is a schematic block diagram of an embodiment of the dynamic RAM according to the present invention. In the figure, as a dynamic RAM, a memory mat (MAT) and a memory control circuit are represented by a black box as a representative, and each of the following circuit blocks is made of single crystal silicon by a known semiconductor integrated circuit manufacturing technique. One such semiconductor chip (DRAM chip)
Formed.

The refresh controller is composed of the following circuit blocks. The RAM is composed of a dynamic RAM, although not particularly limited. The reason is that the same memory cell as the memory mat can be used and the memory access for writing or reading is always performed to the RAM in a constant cycle as described above, and the substantial refresh operation can be made unnecessary. is there.

In this embodiment, in response to the replacement of the CPU with the memory mat, the multiplexer M
The UX1 switches between an address signal supplied from the outside and a refresh address signal formed by a latch circuit forming a refresh address counter and supplies the memory mat with the address signal supplied from the outside and the address signal supplied from the outside. The refresh address signal is supplied to the memory circuit RAM via the multiplexer MUX2.

A refresh request signal (CBR refresh signal as described later) from the CPU or the like is input to the memory control circuit via the control pin. When the memory control circuit determines that it is CBR refresh, it transmits a refresh start signal to the control circuit. That is, it is equivalent to the refresh activation signal from the timer circuit in FIG. 1 being output from the memory control circuit. Thereafter, in the same manner as in the embodiment of FIG. 1, the refresh address is incremented, the recording bit of the memory circuit RAM is read and determined, and the refresh is executed / invalidated for the memory mat MAT.

A timer circuit may be built in the refresh control circuit so that the dynamic RAM itself performs the refresh operation at a constant cycle. In this case, the CPU or the like can dispense with the refresh control circuit as shown in FIG. That is, the CPU or the like can handle the dynamic RAM in the same manner as the static RAM. In this case, if the refresh operation and the memory access compete with each other, the memory access is delayed. Therefore, when burst refresh is adopted,
Considering the efficiency of data processing because the CPU waits for a long period of 1024 cycles, it is better to equally divide the information holding time of the dynamic memory cell into 1/1024 for refreshing.

FIG. 3 is a flow chart for explaining an example of the operation of the refresh control circuit according to the present invention. In step (1), the refresh operation is activated by the refresh control circuit. That is, in the refresh control circuit built in the CPU, it is possible to specify whether the refresh control circuit provided externally controls the refresh of the dynamic RAM or the built-in refresh control circuit performs the refresh control. In (1), the refresh operation is designated by the built-in refresh control circuit.

In step (2), the timer circuit is activated to measure time. In step (3), the time measurement is continued until the time when the refresh is activated, and if it is determined that the above time has been reached, a refresh request signal (activation signal) is generated and the step (2) is performed.
Return to Separately from that, step (5)
When a memory access request is generated, the table is written in step (6), in other words, the memory access to the memory circuit RAM is recorded and the dynamic RAM is accessed.

In step (7), the refresh operation is activated by the activation of refresh from the timer circuit, and the refresh address is incremented by 1 in step (8). In step (9), the table is read, that is, the storage circuit is read. In step (10), the recording of the table is judged, and when there is no recording of the memory access, the refresh control circuit ends as it is and the refresh operation is carried out. In the step (10), when the memory access record exists, the record bit of the table is cleared to prohibit the output of the refresh request signal, and the refresh cycle is invalidated. As a result, the operation is ended only when the refresh address is incremented by +1.

FIG. 4 is an operation conceptual diagram for explaining an example of memory access of the dynamic RAM by the refresh control circuit according to the present invention. After refreshing to the row address = 0, writing or reading of the dynamic RAM is performed in accordance with the instruction execution (operand access) of the data processing by the CPU or the like to access the row address = n. Be seen. After this, refresh is activated,
When the row address is n, the storage circuit RAM
The refresh operation itself is invalidated only by incrementing the refresh address to +1 because the corresponding storage bit of is set.

Hereinafter, the memory access of the dynamic RAM by the execution of the data processing instruction by the CPU and the refresh operation by the timer circuit are performed.
At the time of refresh activation, the corresponding storage bit of the storage circuit RAM is read, and it is determined whether or not the refresh operation is executed.

In such a refresh control operation, the actual power consumption is the shaded portion in FIG.
Power consumption can be reduced only in the portion where the refresh operation is omitted. In other words, since the conventional refresh control circuit performs the refresh operation regardless of the memory access, the refresh operation also consumes the current even in the non-shaded area.

A microprocessor having a built-in refresh control circuit is convenient for constructing a data processing device of a relatively small scale. This is because by incorporating the refresh control circuit, only the ROM, the dynamic RAM and the I / O device as shown in FIG. 5 need be connected on the system bus.

As an example of such a small-scale data processing apparatus, there is a microcomputer called an electronic notebook for pen input. In such an electronic notebook, as a main memory, a dynamic type R having a relatively small storage capacity is used.
Since the AM is sufficient and the memory is frequently accessed to the dynamic RAM, by using the refresh control circuit according to the present invention, the current consumption due to the refresh operation can be greatly reduced. And
Since such a small-scale data processing device is driven by a battery, it is possible to extend the battery life by reducing the power consumption.

FIG. 7 is a timing chart showing an example of the operation of the memory of the dynamic RAM. The clock pulse φ defines the operation of the bus controller of the microprocessor, and in synchronization with this, the address signals, / RAS, / CAS and R * / W signals are output. Here, in the specification, an overbar having a low level as an active level is replaced with / (slash). Therefore, the slash / in the read / write control signal R / W is replaced with * for the purpose of illustration.

The CBR refresh is performed by first setting the / CAS signal to the low level and then setting the / RAS signal to the low level. At this time, the address is invalidated and a refresh address is formed by a refresh address counter provided inside the dynamic RAM. In normal memory access, / RAS is set to a low level, a row address signal is input in synchronization with it, and then a / CAS signal is set to a low level and a column address signal is input from the same address terminal. . If the signal R * / W is high level, the read operation is performed, and if the signal R * / W is low level, the write operation is performed. The signal R * / W can also be expressed as a signal / WE.
When the / CAS signal is changed and the column address signal is switched while / RAS is kept at the low level, only the column address is switched to perform the memory access (page mode).

The operation and effect obtained from the above embodiment are as follows. (1) In a semiconductor integrated circuit device including at least a central control unit or a dynamic RAM that performs data processing according to a program, a storage circuit having a storage bit corresponding to a refresh address of the dynamic RAM and a refresh cycle of the dynamic RAM. And a refresh address counter for generating a refresh address according to the refresh activation signal corresponding to the above, and the memory address is recorded when the memory access is performed to the storage circuit, and the storage is performed by the refresh activation signal and the refresh address signal. When the memory bit corresponding to the address to be refreshed is read out to the circuit and the memory access record exists, the refresh control signal is invalidated and only the refresh address is updated. Along with the provision of a refresh control circuit that clears the above-mentioned recording and performs a refresh operation by a refresh address signal and a refresh control signal when the memory access recording does not exist, the power consumption of the dynamic RAM can be reduced. In addition to the above, it is possible to obtain the effect of reducing the waiting time of the refresh period of the dynamic RAM in the microprocessor and improving the efficiency of data processing.

(2) In the refresh control circuit provided in the microprocessor, the timer circuit generates the refresh start signal for performing the refresh operation continuously a plurality of times, and the refresh control signal is generated in response to the intermittent continuous refresh times. By reading out a plurality of bits of the memory circuit at the same time, it is possible to obtain efficient access to the memory circuit and efficiency of data processing of the CPU.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the refresh cycle may be 512 in addition to 1024 cycles.
Various settings such as cycle or 2048 cycle are possible. The refresh cycle may be set by a program when the CPU is initially set. For example, an 11-bit latch circuit is used to enable up to 2048 cycles, and if the upper 1 bit is invalidated, it becomes 1024 cycles, and if the upper 2 bits are invalidated, it becomes 512 cycles. Only a part of the memory circuit RAM may be used for such a refresh cycle.

The RAM for recording the memory access may be a static RAM in addition to the one using dynamic memory cells. The memory circuit RAM can adopt various embodiments such as 512 × 16. The microprocessor may include peripheral circuits such as a cache memory, a direct memory access control circuit, a D / A conversion circuit, an A / D conversion circuit, etc. in addition to the central processing unit CPU as described above.

[0039]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor integrated circuit device including at least a central control unit or a dynamic RAM that performs data processing according to a program, a memory circuit having a memory bit corresponding to a refresh address of the dynamic RAM and a refresh cycle of the dynamic RAM are supported. And a refresh address counter for generating a refresh address by a refresh activation signal, and when the memory access is made to the memory circuit, the recording is performed, and the refresh activation signal and the refresh address signal are used for the memory circuit. When the memory bit corresponding to the address to be refreshed is read out and the memory access record exists, the refresh control signal is invalidated and only the refresh address is updated. Clear the recording, by providing the refresh control circuit comprising Toka control circuit to perform a refresh operation according to the refresh address signal and the refresh control signal when the recording of the memory access does not exist, a dynamic RA
In addition to reducing the power consumption of M, the microprocessor can improve the efficiency of data processing by reducing the waiting time of the refresh period of the dynamic RAM.

In the refresh control circuit provided in the microprocessor, the timer circuit generates the refresh start signal for performing the refresh operation continuously for a plurality of times, and the refresh circuit of the memory circuit is provided corresponding to the intermittent continuous refresh times. By reading out a plurality of bits at the same time, efficient access of the memory circuit and efficiency of data processing of the CPU can be achieved.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a microprocessor according to the present invention.

FIG. 2 is a schematic block diagram showing an embodiment of a dynamic RAM according to the present invention.

FIG. 3 is a flow chart diagram for explaining an example of the operation of the refresh control circuit according to the present invention.

FIG. 4 is an operation conceptual diagram showing an example of memory access of a dynamic RAM by a refresh control circuit according to the present invention.

FIG. 5 is a block diagram showing an embodiment of an information processing system using the CPU with the refresh function.

FIG. 6 is a schematic block diagram showing an example of a conventional microprocessor with a refresh function.

FIG. 7 is a timing chart showing an example of the operation of the dynamic RAM.

[Explanation of symbols]

RAM ... Storage circuit, MUX1, MUX2 ... Multiplexer, CPU ... Central processing unit, ROM ... Read only memory, DRAM ... Dynamic RAM.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Ikuya Kawasaki 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo Incorporated company Hitachi, Ltd. Semiconductor Division (72) Inventor Susumu Narita 1-280, Higashi Koikeku, Kokubunji, Tokyo Address: Central Research Laboratory, Hitachi, Ltd. (72) Inventor Susumu Kaneko 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Incorporated: Hitachi, Ltd., Semiconductor Business Division

Claims (3)

[Claims] 1. In a semiconductor integrated circuit device including at least a central control unit for performing data processing according to a program, a memory circuit having a memory bit corresponding to a refresh address of a dynamic RAM provided externally, and a refresh cycle of the dynamic RAM. And a timer circuit that forms a refresh start signal corresponding to
A refresh address counter for generating a refresh address by a refresh activation signal formed by such a timer circuit and recording when a memory access is made to the memory circuit, and the refresh activation signal and the refresh address signal are recorded. Read the memory bit corresponding to the address to be refreshed to the memory circuit and invalidate the refresh control signal to be sent to the outside when there is a memory access record and update only the refresh address and record the above A semiconductor integrated circuit device characterized in that a refresh control circuit comprising a refresh address signal and a control circuit for sending a refresh control signal to the outside is provided when the memory access record is cleared. . 2. The timer circuit forms a refresh activation signal for continuously performing a refresh operation a plurality of times, and a plurality of bits of the memory circuit are simultaneously read in correspondence with the number of consecutive refresh times. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a semiconductor integrated circuit device. 3. A semiconductor integrated circuit device including a dynamic RAM, a memory circuit having a memory bit corresponding to a refresh address of the dynamic RAM, a refresh address counter for generating a refresh address by a refresh start signal, and the memory. When a memory access is made to the circuit, the memory access is recorded, and the memory start bit and the refresh address signal are used to read the memory bit corresponding to the address to be refreshed from the memory circuit to perform the memory access. When there is a record, the refresh control signal is invalidated and only the refresh address is updated, and the above record is cleared, and when there is no record of the above memory access, the refresh address signal and refresh control signal are set. A semiconductor integrated circuit device comprising a refresh control circuit including a control circuit for performing a refresh operation according to a control signal.