JPH08306870A - Semiconductor integrated booster circuit device - Google Patents

Abstract

PURPOSE: To provide high-voltage output without introducing special manufacture process by composing a capacity, which is required by a semiconductor integrated booster circuit device, by connecting a MOS capacity element and a junction capacity element in series and fixing a number of connections in series so as to allow a voltage to be applied to the MOS capacity element, etc., to be at the withstand voltage or below. CONSTITUTION: A capacity C2 at the second stage, for example, is composed by connecting the two rows in parallel. The row is provided by connecting two capacity elements C in series. Since the two rows, which are composed of two elements connected in series respectively, are connected in parallel, the capacity of the whole capacity C2 is equivalent to that of one capacity element C. However, since two capacity elements C are connected in series, the withstand voltage is doubled compared with that of the prior art element. In the same manner, a capacity Cn at the step (n) has a total capacity equivalent to one capacity element C. However, the withstand voltage is (n) times the prior art withstand voltage. Therefore, a capacity with a high withstand voltage is provided by properly connecting the prior art capacity elements C without specially providing a capacity with a high withstand voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated booster circuit device in which a booster circuit composed of a charge pump circuit is integrated on a semiconductor integrated device in which other circuits are also integrated.

[0002]

2. Description of the Related Art As a circuit for obtaining a high voltage equal to or higher than a power supply voltage, a charge pump circuit which sequentially increases the voltage is known. A charge pump circuit is often used also when forming a high voltage source on a semiconductor integrated circuit device.

FIG. 6 is a diagram showing a conventional semiconductor integrated booster circuit device using such a charge pump circuit.
In FIG. 6, 1 is an input terminal, 2 is an output terminal, 3 and 4 are control signal terminals, P _{1 to} P _n , Q _{1 to} Q _n , R _{1 to} R _n are connection points, C is a capacitive element, and C _{1 is} -C _n capacity, D ₁ to D _n
Is a connection path switching circuit, T _{01 to} T _{0n + 1} , T _{11 to} T _1n are nM
OS transistors, T _{21 to} T _2n are pMOS transistors, and φ ₁ , φ ₂ , -φ ₁ , and -φ ₂ are control clock pulses. Note that −φ ₁ and −φ ₂ are φ ₁ and φ ₂ respectively.
Is a pulse that is inverted.

A circuit including a capacitance such as C ₁ and a connection path switching circuit such as D ₁ constitutes one step-up unit circuit, which is connected in a plurality of stages, so that the step-up is performed a plurality of times. V _in is the input voltage, which is being sequentially boosted obtained high output voltage. Therefore, in order to obtain a desired high voltage with a small number of stages, it is better to use a voltage as high as V _in . Therefore, as V _{in, the} power supply voltage V _cc is the maximum voltage supplied to the semiconductor integrated circuit device may also be used.

Each of the capacitors C _{1 to} C _n is composed of one capacitance element C. The capacitive element C referred to here
Is a MOS capacitance element or a junction capacitance element obtained by using a layer formed when forming a MOS transistor or a bipolar element in a normal LSI manufacturing process. The connection path switching circuits D _{1 to} D _n have capacitances C ₁ to C.
It is a circuit that switches whether one terminal of _n is connected to the ground potential or a predetermined potential (in the figure, the same V _in as the input voltage) is connected. Control clock pulse φ
₁ , φ ₂ , −φ ₁ , and −φ ₂ are for controlling the switching. To explain the operation of the circuit of FIG.
First, the operation of the booster unit circuit of the first stage will be described.

FIG. 5 is a diagram showing the configuration of the first stage of the charge pump circuit. The reference numerals correspond to those in FIG.
1 is the output terminal of the first stage, and V ₀₁ is the output voltage of the first stage. The nMOS transistor T ₀₁ is diode-connected in a direction that allows current to flow from the input voltage V _in applied to the input terminal 1. In this case, the gate and the drain are collectively connected, and the P ₁ side of the connection point is the anode side. Therefore, when the reverse voltage is applied, the nMOS transistor T ₀₁ is turned off.

The first terminal of the capacitor C ₁ is connected to the source of the nMOS transistor T ₀₁ . (The connection point Q _1). In the connection path switching circuit D ₁ , the drain has a capacitance C ₁
N connected together to the second terminal of (the connection point is R ₁ ) n
It is composed of a MOS transistor T ₁₁ and a pMOS transistor T ₂₁ . The source of the nMOS transistor T ₁₁ is connected to the ground potential, and the source of the pMOS transistor T ₂₁ is connected to a predetermined potential (V _{in in} this case). nM
The control clock pulse φ ₁ is applied to the gate of the OS transistor T ₁₁ , and the control clock pulse −φ ₂ is applied to the gate of the pMOS transistor T ₂₁ . By these pulses, the connection destination of the second terminal of the capacitor C ₁ is switched to the ground potential or the predetermined potential V _in .

FIG. 9 is a diagram showing the waveform of the control clock pulse. t _{1 to} t ₄ are times. The size of the control clock pulse is pMO _in which V _in is applied to the drain.
It is set to V _in so that the on / off of the S transistor T ₂₁ can be controlled. Next, the operation will be described in order of time.

Since the time t _{1 to} t ₂ control clock pulse −φ ₂ is high (V _in ),
The pMOS transistor T ₂₁ is off. On the other hand, since the control clock pulse φ ₁ is low (0), the nMOS transistor T ₁₁ is also off.

From time t _{2 to} t ₃ control clock pulse −φ ₂ remains high, so p
The MOS transistor T ₂₁ remains off. Time t ₂
The control clock pulse φ ₁ goes high at
The transistor T ₁₁ is turned on. Therefore, the input voltage V _in
Input terminal 1 → nMO
A current flows through a path of S transistor T ₀₁ → capacitance C ₁ → nMOS transistor T ₁₁ → ground potential, and charging of the capacitance C ₁ is started. As the charging progresses, the potential at the connection point Q ₁ becomes V _in . It should be noted that the voltage drop in each MOS transistor is ignored in order to avoid a complicated description (the same applies to the following description).

[0011] Since the control clock pulse φ ₁ at time t ₃ ~t ₅ hours t ₃ is low,
The nMOS transistor T ₁₁ is turned off and the charging is stopped. At this time, since the control clock pulse -φ ₂ is still high, the pMOS transistor T ₂₁ also remains off. However, when the control clock pulse -φ ₂ goes low at time t ₄ , the pMOS transistor T ₂₁ turns on.
At this moment, the second terminal of the capacitor C ₁ is connected to the predetermined potential V _in , so the potential at the connection point Q ₁ is raised by V _in due to the capacitive coupling action.

Since the charging potential was V _in , the charging potential and the bottom-up V _in were summed, and the potential at the connection point Q ₁ was 2 V _in.
Rise to. That is, the voltage is boosted by the predetermined potential V _in applied to the drain of the pMOS transistor T ₂₁ . At this time, the potential at the connection point Q ₁ becomes higher than the potential at the connection point P ₁ , so that the nMOS transistor T ₀₁ is turned off. The voltage boosted as described above is the output voltage V ₀₁ of the first stage.
As the input voltage of the boosting unit circuit of the second stage.

Note that the reason why the period in which either of the MOS transistors of the connection path switching circuit D is turned off before being turned on is provided is that the predetermined potential V _in → pMOS transistor _in the connection path switching circuit D is set. T ₂₁ → nMO
This is to prevent a short circuit in the path of S transistor T ₁₁ → ground potential from occurring. If both MOS transistors are turned on, this short circuit will occur.

In the semiconductor integrated booster circuit device of FIG. 6, since the booster unit circuits as described above are cascaded in a plurality of stages,
The voltage is increased by a predetermined potential V _in at each stage, and the following output voltage V _O is obtained at the output terminal 2. V _O = input voltage + step-up voltage total = V _in + nV _in = (n + 1) V _in

By the way, since such a semiconductor integrated booster circuit device is formed on a semiconductor integrated circuit device in which various other electric circuits are simultaneously integrated at the time of manufacture, the capacitance C ₁
The -C _n, Toka pn junction for the gate oxide portion Toka bipolar element of MOS transistors are used. Next, one example of them will be shown.

FIG. 7 is a diagram for explaining a MOS capacitor element in which the gate oxide film portion of the MOS transistor is used as a capacitor element. 10 is a p-substrate, 11 is a p-layer, 12 is S
iO ₂ layer, 13 is a CVD SiO ₂ layer, 14 is an aluminum layer,
Reference numeral 15 is a poly-Si layer, 16 is an n ⁺ layer, and 17 is an aluminum layer. The p-substrate 10 is grounded. Q and R correspond to the connection points Q ₁ and R ₁ respectively. Poly S
The gate oxide film SiO ₂ layer 12 sandwiched between the i layer 15 and the n ⁺ layer 16 is used as a capacitive element. The aluminum layers 14 and 17 are formed as electrodes for wiring. The poly-Si layer 15 is connected to the connection point Q via the aluminum layer 14, and the n ⁺ layer 16 is connected to the connection point R via the aluminum layer 17. Even if the connection point Q side is positive and the connection point R side is negative, or vice versa, capacitance is formed, so that Q and R may be reversed.

FIG. 8 is a diagram for explaining a junction capacitance element using a pn junction portion for a bipolar element as a capacitance element. Reference numerals correspond to those in FIG. 7, and 18 is an n ⁺ buried layer, 1
9 is an n layer, 20 is a p ⁺ layer, 21 is an n ⁺ layer, and 22 is SiO 2.
_{There are two} layers. The p-substrate 10 is grounded. The capacitance is obtained by applying a reverse bias to the pn junction between the p ⁺ layer 20 and the n layer 19 (that is, the connecting point Q side is positive and the connecting point R side is negative) to be in an insulating state. To be If the biasing method is reversed, pn
No capacitance is obtained because the junction does not become an insulating state.

Documents relating to the semiconductor integrated booster circuit device described above include, for example, Japanese Patent Publication No. 42905/1992.
There is a gazette.

[0019]

[Problems to be Solved by the Invention]

(Problem) In the above-described conventional semiconductor integrated booster circuit device, in order to obtain a high output voltage, it is necessary to introduce a special manufacturing process for forming a high breakdown voltage capacitor.
There is a problem that the integrated circuit manufacturing process becomes complicated.

(Explanation of Problems) Among the capacitors of the booster unit circuits of a plurality of stages of the semiconductor integrated booster circuit device, a higher voltage is applied to a capacitor at a later stage. Conventionally, the capacitors C _{1 to} C _n are formed by a normal LSI manufacturing process, as shown in FIG.
The MOS capacitance element and the junction capacitance element as shown in FIG.
One was used for each. However, their withstand voltages are generally designed to withstand the maximum voltage (that is, the power supply voltage V _CC ) supplied to the semiconductor integrated circuit device in which they are formed. Therefore, if the output voltage to be obtained by the semiconductor integrated booster circuit device is as large as the power supply voltage V _CC , there will be no problem in terms of withstand voltage.

However, if an attempt is made to obtain an output voltage higher than that, the withstand voltage of the latter stage capacitor becomes insufficient. That is,
A gate oxide film formed by a normal LSI manufacturing process or a capacitor using a pn junction portion cannot be used. In order to increase the breakdown voltage, in the case of a MOS capacitive element, S
The thickness of the iO ₂ layer needs to be thicker than that of the gate oxide film, and in the case of the junction capacitance element, it is necessary to increase the depth of the p ⁺ layer and reduce the concentration of the n layer. is there.

However, in order to obtain the capacitance in this way, it is necessary to introduce a special manufacturing process for forming a high breakdown voltage capacitor during the LSI manufacturing process, which complicates the integrated circuit manufacturing process. Manufacturing cost is high. Further, there is a problem that the thickness increases because the thickness of the layer has to be increased. An object of the present invention is to solve the above problems.

[0023]

In order to solve the above-mentioned problems, in the semiconductor integrated booster circuit device of the present invention, the capacitance in which the first terminal is connected to the input power supply and the connection potential of the second terminal of the capacitance are set. In a semiconductor integrated boosting circuit device, a charge pump circuit having a plurality of boosting stages each including a connection path switching circuit for switching is formed on the semiconductor integrated circuit device.
The capacitance is formed by connecting in series one or more capacitance elements obtained by using layers formed when forming an OS transistor or a bipolar element, and the number of capacitance elements connected in series is applied to each capacitance element. It is decided to select such a number that the voltage to be applied is equal to or lower than the withstand voltage of the capacitive element.

In this case, the capacitance of the n-th boosting stage counting from the input power source side may be configured by connecting the n capacitance elements in series. Further, the capacitance of the n-th boosting stage counting from the input power source side may be configured by connecting in parallel n columns of the above-mentioned n capacitive elements connected in series.

[0025]

[Operation] For the capacitance required for a semiconductor integrated booster circuit device that uses a charge pump circuit, use one MOS capacitance element or junction capacitance element that uses the layer formed when forming a MOS transistor or bipolar element. The above is configured by connecting in series, and the number of series connections is set so that the voltage applied to each of the MOS capacitive element and the junction capacitive element is equal to or lower than the withstand voltage. As a result, it is possible to realize a high breakdown voltage without introducing a special manufacturing process for forming a high breakdown voltage capacitor for a semiconductor integrated booster circuit device. Thus, it is possible to obtain a semiconductor integrated booster circuit device that generates a high voltage.

[0026]

Embodiments of the present invention will now be described in detail with reference to the drawings. (First Embodiment) FIG. 1 is a diagram showing a semiconductor integrated booster circuit device according to a first embodiment of the present invention. The reference numerals correspond to those in FIG. The configuration is different from the conventional example of FIG. 6 in that the capacitance C of the n-th boosting stage counting from the input power source side is
_This is the point where n columns of the capacitive elements C connected in series are connected in parallel.

For example, the second-stage capacitance C ₂ is formed by connecting in parallel two columns in which two capacitive elements C are connected in series. Since two columns in series are two columns in parallel, this capacitance C
The capacitance of _{2 as} a whole is equivalent to one capacitance element C.
This is the same as the capacity C ₂ of the conventional example of. However, the capacitive element C
Since two are connected in series, the breakdown voltage is twice that of the conventional example. Similarly, the capacitance C _n of the nth stage is the capacitance of one capacitance element C as a whole, but the breakdown voltage is n times that of the conventional one. Therefore, even if a capacitor having a large breakdown voltage is not specially formed, it is possible to realize a capacitor having a high breakdown voltage by a connection configuration in which the capacitive elements C that have been used in the past are appropriately combined.

(Second Embodiment) FIG. 4 is a diagram showing only the capacitance portion of the second embodiment of the present invention. The reference numerals correspond to those in FIG. The configuration of the portion other than the capacitors C _{1 to} C _n is the same as that of the first embodiment of FIG. In the second embodiment, the capacitance C of the boosting unit circuit of the nth stage from the input power source side
_n is configured by connecting n capacitive elements C in series. For example, the second-stage capacitance C ₂ is formed by connecting two capacitance elements C in series.

With this configuration, even if the number of stages is increased and the boosted voltage applied to the entire capacitance of the stages is increased, the voltage applied to one capacitive element C can be set to be equal to or lower than the withstand voltage. I can. However, since the capacity is reduced because it is only connected in series, the ability to supply current to the output side is reduced. For example, since the capacitance of the nth stage is C / n, the capacitance C
The current supply capacity is 1 / n as compared with the case where

(Third Embodiment) In the second embodiment, the capacitance of the nth stage is made up of n capacitive elements C connected in series, so that the number of stages and the number of series connections are the same. But
It does not necessarily have to match. The reason is that the input voltage V _in applied to the input terminal 1 and the predetermined boosting potential applied to one MOS transistor in the connection path switching circuit (in the case of FIG. 1, V _in applied to the pMOS transistor T _{21 and the} like). ) is because not necessarily the power supply voltage V _cc is the maximum voltage applied to the semiconductor integrated circuit device.

[0031] As mentioned previously, the capacitive element C typically are designed to be resistant to _the power supply voltage V _cc is the maximum voltage. Therefore, if V _cc as the input voltage and the predetermined potential is used, the second stage 2V in the capacitor C ₂ of
It _cc is applied, the capacitance C _n of n-th stage because nV _cc is applied, the second stage of the capacitor C ₂ constitute the two capacitive elements C are connected in series, the n-th stage The capacitance C _n needs to be configured by connecting n capacitance elements C in series.

[0032] However, in the case where a voltage lower than V _cc is used, does not need to be up there. For example, when V _cc / 2 is used as the input voltage or the predetermined potential, 2
Up to the capacitance C ₂ of the stage can be withstood by one capacitive element C, and for the capacitance of a larger number of stages, the voltage applied to each capacitive element C is tolerable in consideration of the maximum voltage applied to it. The number of capacitive elements C connected in series may be determined so as to be as follows.

In the second and third embodiments, some capacitance elements C are connected in series to form each stage capacitance, but some series connection bodies may be connected in parallel. . The number of parallel connections may be determined as appropriate in consideration of the current supply capacity required on the output side.

Next, an example of a specific configuration in which the capacitive element C is connected in series will be shown. FIG. 2 is a diagram showing a cross-sectional structure when a MOS capacitor element is used as the capacitor element C and two MOS capacitor elements are connected in series. Reference numerals correspond to those in FIG. 7, and 14A, 1
4B, 17A and 17B are aluminum layers, and 23 is wiring.
_Two MOS capacitance elements utilizing the SiO ₂ layer 12 formed when forming the oxide film for the gate of the MOS transistor are connected in series by the wiring 23.

FIG. 3 is a diagram showing a cross-sectional structure when a junction capacitance element is used as the capacitance element C and two junction capacitance elements are connected in series. Reference numerals correspond to those in FIGS. 8 and 2. Two pn junction portions (portions of the n layer 19 and the p ⁺ layer 20) formed when forming the bipolar element are connected in series by the wiring 23. Although only two series connections are shown in FIGS. 2 and 3, a larger number of series connections can be realized by repeating the connection in the same manner. The parallel connection of the serially connected ones can be realized by connecting the corresponding ones at both ends (R ₂ and Q _{2 in} FIGS. 2 and 3) of the serially connected ones.

[0036]

As described above, according to the present invention, the capacitance required for a semiconductor integrated booster circuit device using a charge pump circuit is provided in a layer formed when forming a MOS transistor or a bipolar element. One or more of the used MOS capacitance elements or junction capacitance elements are connected in series, and the number of serial connections is such that the voltage applied to each of the MOS capacitance elements or junction capacitance elements is below its withstand voltage. To do. Therefore, a semiconductor integrated booster circuit device that generates a high voltage can be obtained without introducing a special manufacturing process for forming a capacitor having a high breakdown voltage for the semiconductor integrated booster circuit device.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor integrated booster circuit device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a cross-sectional structure when two MOS capacitance elements are connected in series.

FIG. 3 is a diagram showing a cross-sectional structure when two junction capacitance elements are connected in series.

FIG. 4 is a diagram showing only a capacitance portion of a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of one stage of a charge pump circuit.

FIG. 6 is a diagram showing a conventional semiconductor integrated booster circuit device.

FIG. 7 is a diagram illustrating a MOS capacitor element.

FIG. 8 is a diagram illustrating a junction capacitor element.

FIG. 9 is a diagram showing a waveform of a control clock pulse.

[Explanation of symbols]

1 ... input terminal, 2 ... output terminal, 3,4 ... control signal terminal,
10 ... p-substrate, 11 ... p layer, 12 ... SiO ₂ layer, 13
... CVD SiO ₂ layer, 14 ... Aluminum layer, 15 ... Poly Si
Layers, 16 ... n ⁺ layers, 17 ... aluminum layers, 18 ... n ⁺ buried layers, 19 ... n layers, 20 ... p ⁺ layers, 21 ... n ⁺ layers, 22 ...
SiO ₂ layer, 23 ... Wiring, P _{1 to} P _n , Q _{1 to} Q _n , R
₁ to R _n ... connection point, C ... capacitive element, C ₁ -C _n ... capacity,
D _{1 to} D _n ... Connection path switching circuit, T _{01 to} T _{0n + 1} , T ₁₁ to
T _1n ... nMOS transistor, T _{21 to} T _2n ... pMOS transistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshinori Yamaguchi 2274 Hongo, Ebina City, Kanagawa Prefecture Fuji Xerox Co., Ltd.

Claims (3)

[Claims] 1. A semiconductor integrated circuit comprising a charge pump circuit having a plurality of boosting stages each comprising a capacitor having a first terminal connected to an input power supply and a connection path switching circuit for switching a connection potential of a second terminal of the capacitor. In a semiconductor integrated booster circuit device formed on a circuit device, one or more capacitive elements obtained by utilizing layers formed when forming a MOS transistor or a bipolar element are connected in series to configure the capacitance,
2. A semiconductor integrated booster circuit device, wherein the number of capacitors connected in series is selected so that the voltage applied to each capacitor is equal to or lower than the withstand voltage of the capacitor. 2. The semiconductor integrated boosting circuit device according to claim 1, wherein the capacitance of the n-th boosting stage counting from the input power source side is configured by connecting the n capacitance elements in series. 3. The capacitor of the n-th boosting stage counting from the input power source side is configured by connecting n columns of the capacitive elements connected in series to n columns in parallel. Semiconductor integrated booster circuit device.