JPH0830566A - Communication control equipment loaded into processor element in parallel computer - Google Patents

Abstract

PURPOSE:To issue a command with a user level in a communication control equipment loaded into a processor element in a parallel computer. CONSTITUTION:When a processor 110 writes a command data sequence in a command entry area in its address space, a bus interface 141 in the communication control equipment 140 determines the sort of a command from the writing address of the command data string. A command is generated by filling the 1st word of the command data string with the command sort and transmitted to a transmission controller 142.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an interconnection network (IN: In) in which a plurality of processing elements (PEs) are interconnected.
The present invention relates to a parallel computer coupled to a terconnection network), and particularly to a communication control device implemented in the processor element.

[0002]

2. Description of the Related Art As the speeding up of a general-purpose large-scale computer based on the sequential processing method as a basic principle is approaching the limit in terms of hardware technology and logical method, a plurality of processor elements (hereinafter referred to as PE) are used. There is a growing need for parallel computers that perform parallel processing.

Especially in the field of science and technology calculation (fluid dynamics, atomic physics, molecular science, etc.),
Since a huge amount of calculation is required to secure the reliability and accuracy of the solution, there is a strong need for reducing the calculation time.

FIG. 15 is a block diagram showing the overall configuration of a parallel computer having a general distributed memory configuration. PE70
Includes a processor 71, a memory 72 accessed by the processor 71, and a communication control device 73 that controls the processor 71 for exchanging messages with other PEs 70 via the mutual communication network 80.

In the parallel computer, the communication between the processors 71 is indispensable because the plurality of processors 71 provided in each PE 70 cooperate with each other to carry out the processing while balancing the load and the function. In the parallel computer having the above configuration, the communication between the processors 71 is performed by the mutual communication network 80.
It is carried out by a message passing method via the.

In order to improve the performance of the parallel computer, it is necessary to perform the communication processing between the processors 71 at high speed, and to perform the communication processing and the calculation processing (arithmetic processing) by the processor 71 in parallel. It has become.

Generally, message communication between the processors 71 is performed by exchanging a command having a plurality of parameters and data associated with the command. The following methods have been conventionally used for such message communication. The processor 71 provides, in the communication control device 73, a plurality of registers for setting a command including a command type and individual parameters associated with the command. The processor 71 sets the type of the command to be transmitted to the processor 71 of the other PE 70 and its parameters in the individual registers, and then activates a transmission mechanism (not shown) provided in the communication control device 73. This causes the transmission mechanism to
The command and its parameters set in the plurality of registers are sequentially interpreted to construct a transmission message, and the message is transmitted to the other PE 70 via the mutual connection network 80. The processor 71 writes the above command in a predetermined area of the memory 72. Subsequently, the processor 71 notifies the communication control device 73 of the write address of the command in the predetermined area on the memory 72, and the communication control device 73
To start. The communication control device 73 constructs a transmission message in the same manner as described above, and sends the message to the interconnection network 8.
It is transmitted to the other PE 70 concerned via 0.

[0008]

The above system has the following drawbacks. In the case of this system, the contents of the register set in the communication control device 73 must be protected until the contents are transmitted to the other PE 70 by the transmission mechanism via the mutual coupling network 80. Therefore, during this period, in order to prohibit the access to the register at the user level, the operation of setting a command in the register needs to be performed by issuing a system call to shift to the system level.

When a system call is issued to shift from the user level to the system level, the execution shifts to the kernel, and the kernel executes many processor instructions for the level shift processing. Then, the processing time of the processor 71 for executing this instruction becomes an overhead, which causes a decrease in system throughput.

Further, in this method, since a command consisting of one or a plurality of words must be set in the register in the communication control device 73 for each communication, when a plurality of messages are continuously transmitted. The communication control device 73 had to be activated after waiting for the completion of the communication process of the immediately preceding message. That is, only one message communication process can be performed at a time. In addition, in order to reduce the waiting time that occurs each time one message is communicated, a device that interrupts the processor 71 each time the message communication ends is often installed in the communication control device 73. However, the interrupt process executed by the processor 71 in response to this interrupt requires the execution of many processor instructions similarly to the process at the time of shifting to the level, and there is a problem that the processing time becomes an overhead. .

On the other hand, in the latter method, a plurality of commands can be set in the continuous area by utilizing the continuous area in the memory 72, and the communication processing of continuous messages can be processed efficiently and at high speed. It is possible. However, the memory 7 in which the above multiple commands are set
The area above 2 must be protected from other processes until the transfer of the message is complete. This protection is not possible at the user level, and it is necessary to move to the system level as in the above method, and MMU (Me
It is necessary to protect the above memory area by using the (Mory Management Unit). Therefore, there is a problem similar to the above method.

Also, the value of one or a plurality of parameters for a plurality of commands is calculated, the calculated command is stored in the memory 72, the storage address of the command is set in the communication control device 73, and then the communication control device is set. There is a problem that a series of processing of activating 73 is required, and when the amount of parameters stored in the memory 72 increases, the overhead of the above processing time increases.

According to the present invention, it is possible to issue a command at the user level, reduce the overhead involved in the transition to the system level, which has been conventionally required, and speed up continuous message communication. is there.

Another object is to enable the processor to issue a plurality of commands continuously and efficiently.

[0015]

FIG. 1 is a diagram for explaining the principle of the present invention. The invention comprises a plurality of processor elements 1
A parallel computer system in which 0s are connected via an interconnection network 20 is premised on a communication control device 30 installed in each processor element 10.

The communication control device according to the invention of claim 1 has the following means. The bus interface 31 detects writing of a command data string to a predetermined command entry area by the processor 11 in the processor element 10, generates a command from the command data string, and also writes data to the memory 12 of its own processor element 10. Read / write control of.

The transmission controller 32 interprets the command generated by the bus interface 31 and constructs a transmission message. Interconnection network interface 33
Sends a transmission message constructed by the transmission controller 32 to the interconnection network 20 and receives a message addressed to its own processor element 10 from the interconnection network 20.

The reception controller 34 interprets the message received by the interconnection network interface 33, and transfers the data transferred by the message via the bus interface 31 to its own processor element 1.
0 is stored in the designated area of the memory 12.

According to a second aspect of the present invention, in the first aspect of the present invention, the reception controller 34 is designated with a special buffer area predetermined as a data storage destination in the command of the received message. In this case, the received message data is stored in the buffer area via the bus interface 31.

According to a third aspect of the present invention, in the above-described first aspect of the invention, a command requesting the reception controller 34 to transfer the contents of the memory 12 of the own processor element 10 to another processor element 10 is issued. When received, the command is transmitted to the transmission controller 32.

When the transmission controller 32 receives the above command, it reads the data requested by the above command from the memory 12 of its own processor element 10 via the bus interface 31, and constructs a message for transmitting the data. To configure.

The invention according to a fourth aspect comprises, in addition to each element of the invention according to the first aspect, a command queue 35 in which a command generated by the bus interface 31 is written.

According to a fifth aspect of the present invention, there is provided the bus interface 31 according to the third aspect of the invention.
When the processor 11 detects an access to a certain address area, the processor 11 includes a mechanism for generating a remote access command for accessing the memory 12 of another processor element 10. The access includes, for example, referring to or updating the memory 12.

In addition to the elements of the invention described in claim 5, the invention according to claim 6 further includes a remote access transmission queue 35A in which the remote access command generated by the bus interface 31 is written.
Is provided.

According to a seventh aspect of the present invention, there is provided the bus interface 31 according to the first aspect of the invention.
Generates a system mode communication command from the command data string written in the command entry area when the processor 11 is running at the system level, and outputs the command when the processor 11 is running at the user level. A user mode communication command is generated from the command data string written in the entry area.

In addition to the elements of the invention described in claim 7, the invention described in claim 8 further includes a system transmission queue 35B in which a communication command in the system mode generated by the bus interface 31 is written, and the system transmission queue 35B. It is provided with a user transmission queue 35C to which a user mode communication command is written.

Then, the transmission controller 32 uses the system transmission queue 35B or the user transmission queue 3
The transmission command is extracted from 5C and the communication command is executed.

The ninth aspect of the present invention, in addition to the elements provided in the first aspect of the present invention, further includes a message of a command for which processing is completed in the own processor element 10 constructed by the transmission controller 32. , A transfer means 36 for transferring to the reception controller 34 without passing through the mutual connection network interface 33.

The present invention as set forth in claim 10 is, in addition to the elements provided in the invention as set forth in claim 3, further, the reception controller 34 receives the memory 12 of its own processor element 10 via the transfer means 36. In the reply queue 35, a reply command to a message for which a communication command requesting the transfer of data stored in a certain area is set is written by the reception controller 34.
D.

Then, the transmission controller 32 takes out the communication command from the reply queue and executes the communication command via the bus interface 31.

In addition to the elements provided in the invention described in claim 5, the invention described in claim 11 further includes another processor element 10 received by the reception controller 34 via the mutual connection network interface 33. The reply command to the message set by the remote access command for requesting the reference of the contents of the memory 12 of the own processor element 10 issued from
Remote access reply queue 3 written by
5E is provided.

Then, the transmission controller 32 takes out the remote access command from the remote access reply queue 35E, and the bus interface 3
The content of the memory 12 of the own processor element 10 requested by the remote access command is read via 1 to construct a transmission message addressed to the other processor element 10.

According to a twelfth aspect of the invention, there is provided the bus interface 31 according to the first aspect of the invention.
Determines the command type according to the address of the command data string written in the command entry area by the processor 11.

The invention according to claim 13 is the above-mentioned claim 12.
In addition to the elements included in the described invention, a memory protection unit 37 is further provided for limiting the area in the command entry area in which the processor 11 can write the command data string when running at the user level. , Prepare.

The invention according to claim 14 is the above-mentioned claim 1,
In the configuration of the invention described in 4, 6, 8, 10 or 11, the bus interface 31 is the processor 1
1 includes a detection unit 31A that counts the number of command data written in the command entry area according to the type of command to be written in the command entry area and detects the end of the command data string.

The invention of claim 15 is the same as that of claim 14
In the configuration of the described invention, the bus interface 3
1 further includes a check unit 31B that checks the validity of a certain portion of the command data string based on the count value of the command data.

The invention according to claim 16 is the above-mentioned
In the described invention, the bus interface 31 is
An information adding unit 31C is further provided for adding information used in the system to a certain portion of the command data string based on the count value of the command data.

[0038]

According to the present invention, the bus interface 31 detects the writing of the command data string to the predetermined command entry area by the processor 11 in the processor element 10 and generates the command from the command data string. .

Then, the transmission controller 32 interprets the command generated by the bus interface 31 and constructs a transmission message. The interconnection network interface 33 sends the transmission message constructed by the transmission controller 32 to the interconnection network 20. Also, it receives a message addressed to its own processor element 10 from the interconnection network 20.

The reception controller 34 interprets the message received by the interconnection network interface 33, and transfers the data transferred by the message via the bus interface 31 to its own processor element 1.
0 is stored in the designated area of the memory 12.

As described above, when issuing a desired command, the processor 10 sends the command to the address previously assigned to the desired command in the command entry area provided as a specific area in its own address space. You only need to write the parameters. Therefore, by allocating an address area for issuing a user level command to the command entry area, the processor can issue a command at the user level. That is, it is not necessary to shift to the system level when a command is issued, so that the overhead can be reduced.

According to the second aspect of the present invention, the reception controller 34 transfers the data to the bus interface 31 when a special buffer area that is predetermined as a data storage destination is designated in the command of the reception message.
To the buffer area via.

Therefore, it is not necessary to explicitly set the data storage destination address in the message, and the data can be transferred by the message passing method. Also,
Even if the hardware for realizing the above-mentioned data transfer is provided in the reception controller, most of the transmission / reception mechanism can be shared, and an increase in the amount of hardware can be suppressed.

According to the third aspect of the invention, the command for requesting the transfer of the contents of the memory 12 of the own processor element 10 to another processor element 10 is the reception controller 3
When received by 4, the command is transmitted to the transmission controller 32. And the transmission controller 3
When receiving the above command, the 2 reads out the data requested by the above command from the memory 12 of its own processor element 10 via the bus interface 31, and constructs a message for transmitting the data.

Therefore, the processing of the reply command can be executed by the transmission controller 32, and the amount of hardware can be reduced. In the invention according to claim 4, the bus interface 31 immediately transmits the generated command to the command queue 35.
Since the plurality of commands can be continuously written without waiting for the command processing of the transmission controller 32 to end, the processing efficiency is improved.

According to the fifth aspect of the invention, the processor 11
By previously allocating an address area in the access space of the above as an area for generating a remote access command, the bus interface 31 detects an access to the address area by the processor 11, and, for example, a hardware mechanism is used. Thus, the processor 11 automatically generates a remote access command for accessing the memory 12 of another processor element 10.
Therefore, the remote access function can be realized by adding a small amount of hardware.

According to the sixth aspect of the invention, the bus interface 31 writes the generated remote access command in the remote access transmission queue 35A. Therefore, it becomes possible to issue a plurality of remote access communication commands continuously without waiting for the completion of the command processing of the transmission controller 32.

According to the seventh aspect of the invention, the bus interface 31 generates a system mode communication command from the command data string written in the command entry area when the processor 11 is running at the system level. Then, a user mode communication command is generated from the command data string written in the command entry area when the processor 11 is running at the user level.

Therefore, the processor 11 can control the issuance of the system mode communication command and the user mode communication command according to the running level. According to the invention described in claim 8, the system interface and the user mode communication commands are respectively transmitted by the bus interface 31 to the system transmission queue 35.
B is written in the user transmission queue 35C.

Then, the transmission controller 32 takes out the communication command from the system transmission queue 35B or the user transmission queue 35C and executes the communication command. Therefore, it is possible to prioritize the processing of the system command and the user command by determining in advance which of the system transmission queue 35B and the user transmission queue the communication command is extracted. Further, since the system command and the user command are stored in separate queues, even if the running level of the processor 11 is frequently switched between the user level and the system level, the communication command in the user mode and the system mode Communication commands are correctly stored in the queue. Therefore, the processor 11 can issue the above two communication commands independently at any time.

According to the invention described in claim 9, the transfer means 3
6, the message of the command that the processing is completed in the own processor element 10 constructed by the transmission controller 32 is transferred to the reception controller 34 without passing through the mutual completion network interface 33.

Therefore, the processing completed within the own processor element can be performed at high speed. According to the invention described in claim 10, the reply command to the communication command requesting the transfer of the data stored in the certain area of the memory 12 of the own processor element 10 is the reception controller 3
4 is sent to the reply queue 35D.

Then, the transmission controller 32 takes out the communication command from the reply queue and executes the communication command via the bus interface 31.

Therefore, the reception controller 34 can continuously issue the reply command without waiting for the completion of the processing of the transmission controller 32. Claim 11
According to the described invention, the reception controller 34 receives via the mutual connection network interface 33,
A reply command to the remote access command issued from another processor element 10 for requesting the reference of the contents of the memory 12 of its own processor element 10 is sent by the reception controller 34 to the remote access reply queue 35.
Written to E.

Then, the transmission controller 32 takes out the remote access command from the remote access reply queue 35E and reads the content of the memory 12 of the own processor element 10 requested by the remote access command via the bus interface 31. Then, a transmission message addressed to the other processor element 10 is constructed.

Therefore, the reception controller 34 can continuously output the reply command to the remote access command requesting the reply message received via the mutual connection network interface 33 without waiting for the completion of the processing of the transmission controller. it can.

According to the twelfth aspect of the invention, the type of command is determined by the bus interface 31 according to the address of the command data string written in the command entry area by the processor 11.

Therefore, the command entry area can be divided into an area for issuing a user command and an area for issuing a system command. According to the thirteenth aspect of the present invention, the processor 11 is provided with the memory protection means 37.
However, the area in the command entry area in which the command data string can be written while traveling at the user level can be limited to a part of the area.

Therefore, the types of commands that can be issued at the user level can be restricted. According to the fourteenth aspect of the invention, the bus interface 31 detects the number of command data written in the command entry area by the detection means 31A in accordance with the type of the command written in the command entry area by the processor 11. Is counted to detect the end of the command data string.

Therefore, by using this detection information, it is possible to suppress the issuance of uncompleted commands stored in the queue. Also, if multiple queues are prepared according to the type of command, it is sufficient to retrieve the completed command from the queue that stores the completed command and process it. Can be reduced and the processing efficiency can be improved.

According to the fifteenth aspect of the present invention, the bus interface 31 uses the checking means 31B to check the validity of a portion of the command data string based on the count value of the command data.

Therefore, the issuance of an illegal command can be prevented. According to the sixteenth aspect of the present invention, the bus interface 31 adds the information used in the system to a certain portion of the command data string based on the count value of the command data by the information adding means 31C. .

Therefore, various information can be embedded in any part of the command data string.

[0064]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing an overall configuration of a processor element (hereinafter referred to as PE) 100 connected to an interconnection network 200 of a parallel computer which is an embodiment of the present invention.

The PE 100 is composed of a processor 110, a memory 120 connected to the processor 110 via a bus 130, and a communication control device 140. When the processor 110 transmits a command message instructing to transfer the contents of the memory 120 of its own PE 100 to the memory 120 of another PE 100, the area 1 called “command entry” set in its own address space.
Write the command data string to 50.

The command data string is one or more words of data composed of parameters and data forming a command for instructing the processor 110 to execute a certain function. The above parameters include, for example, <destination P
E>, <message size>, <destination address>, <source address>, <other parameters>, ...

FIG. 3 shows the command entry area 150.
It is a figure explaining the concept of. Command entry area 15
0 is a specific area on the address space 112 of the processor 110, and each address is the above PE 100.
There is a one-to-one correspondence with various commands that instruct to transfer the contents of the memory 120 of the other PE 100 to the memory 120 of another PE 100. The processor 100 sends the above commands to other PE1s.
00 to the processor 110, the command entry area 1 that is pre-allocated to the command
The command data string is written to the address of 50.

The communication control device 140 interprets the command data string written on the command entry area 150 output on the bus 130, and the other PE 1
The communication control device 140 of 00 builds a message for command transmission in a format that can be interpreted and sends the message to the interconnection network 160.

The communication control device 140 includes a bus interface 141, a transmission controller 142 and a multiplexer 1.
43, an interconnection network interface 144, and a reception controller 145.

The bus interface 141 is the bus 130.
Of the address data output to the command bus of the bus 130, if the address signal is an address in the command entry area 150, the command data string is extracted from the data bus of the bus 130, and the process ID (PI
The information such as D) is added and transmitted to the transmission controller 142. Further, it also has a mechanism for accessing the memory 120, and performs reading and writing of data from the memory 120. When transferring the contents of the memory 120 of the self PE 100 to the memory 120 of another PE 100, the transfer data is transferred to the self PE 1 by the memory access mechanism.
00 from the memory 120, the multiplexer 14
Output to 3.

The transmission controller 142 interprets the command data string received from the bus interface 141,
Construct a message for sending a command to another PE 100. Then, the message is sent to the multiplexer 14
3 to the mutual connection network interface 145. Also, the command of the received message is the PE 10 itself.
When it is instructed to transfer the content of the memory 120 of 0 to another PE 100, a request for reading the data instructed by the command from the memory 120 is output to the bus interface 141.

The multiplexer 143 is controlled by the transmission controller 142, and the transmission controller 142 is controlled.
Command input from the transmission controller 14
In accordance with the memory read request from the above-mentioned No. 2, one of the data read from the memory 120 of the self PE 100 which is input and sent from the bus interface 141 is selectively output to the mutual connection network interface 145, thereby transmitting to the other PE 100. Output a message.

The interconnection network interface 144 sends the message input from the multiplexer 143 to the interconnection network 160. Also, it receives a message transmitted from another PE 100 from the mutual connection network 160 and outputs it to the reception controller 145.

The reception controller 145 interprets the message input from the mutual connection network interface 144 and performs processing corresponding to the command set in the message. Then, for example, the data transferred by the message is written to the address specified by the above command in the memory 120 of the self PE 100.

In the present embodiment having the above configuration, the processor 110 writes the command data string in a special area called the command entry area 150 in its own address space, so that the processor 110 can execute the above operation at the user level without shifting to the system level. It is possible to write a command data string and perform message communication with another PE 100.

Next, FIG. 4 shows PE2 of another embodiment of the present invention.
Is a block diagram showing the overall configuration of 00. In the figure, the same blocks as the blocks in the embodiment shown in FIG. 2 described above are designated by the same reference numerals, and detailed description thereof will be omitted.

The communication control device 240 of this embodiment is provided with a command queue 246 between the bus interface 241 and the transmission controller 242. The command queue 246 is a queue in which the bus interface 241 writes a command data string, and, for example, a FIFO (First
In First Out) A memory (FIFO buffer) and the like. Then, the command data string written in the queue 246 is read out to the transmission controller 242 by the FIFO method.

In the present embodiment, by providing the command queue 246 in this way, the bus interface 241 can continuously output the command data string without adjusting to the processing speed of the transmission controller 242. Efficiency is improved.

FIG. 5 shows PE3 of still another embodiment of the present invention.
Is a block diagram showing the overall configuration of 00. Also in FIG. 5, the same blocks as the blocks in the embodiment shown in FIG. 2 are denoted by the same reference numerals.

The processor 310 is the processor 310.
An MMU (Memory Management Unit) 312 is provided for protecting unauthorized access at the user level to an area in the command entry area 150 on the address space of which access is permitted only at the system level. The MMU 312 also has a command entry area 15
It also has a memory protection function that prohibits unauthorized access to 0. The MMU 312 is the processor 310.
It may be a chip other than.

Next, the configuration of the communication control device 340 will be described. The bus interface 341 monitors the writing of the command data string to the command entry area 150 of the processor 100 by monitoring the address signal output on the address bus of the bus 130. Then, the type of command is obtained from the write address, and this is set in the first word of the command data string. Further, the process ID (PID) is set in the second word of the command data string. The PID is a unique identifier assigned to each process. When a plurality of processes are executed in a single system, the resource allocated to each process is identified by this PID, and the protection function of access to the resource is realized. Then, the command data string created in this manner is used as the command queue group 346.
Write to the appropriate queue in.

The command queue group 346 includes three transmission queues (user transmission queue 346A, system transmission queue 346B, remote access transmission queue 346C) and two transmission queues.
Book reply queue (remote access reply queue 346
F and other reply queues 346G).

The user transmission queue 346A is a queue for temporarily storing a data string of communication commands (user mode communication commands) issued at the user level. The system transmission queue 346B is a queue that temporarily stores a data string of communication commands (system mode communication commands) issued at the system level.

Processor 310 performs processes at multiple levels. The user level processing is under the control of the system level, the access to the hardware resources is restricted as compared with the system level, and the use of the system privileged instruction is prohibited. If a user level process violates these restrictions, an exception interrupt occurs and processor 310 transitions to the system level.

The remote access transmission queue 346C is
The processor 310 of the own PE 300 refers to (reads) and updates (writes) the contents of the memory 120 of another PE 300.
Further, it is a queue that temporarily stores a data string of communication commands (remote access commands) for executing remote access such as data exchange.

The remote access reply queue 346F is
This is a queue that temporarily stores a data string of a reply command to the remote access command for the memory 120 of its own PE 300 transmitted from another PE 300.

The reply queue 346G is a queue for temporarily storing a data string of a reply command for an access command to the memory 120 of the self PE 300 other than the above remote access command.

The reply command is, for example, the self PE 300.
Is a command for reply when a message of a command requesting reference to the contents of the memory 120 arrives. For example, a reply command to a remote access command from another PE 400, such as a remote read command described in detail later, is stored in the remote access reply queue 346F. Further, for example, the reply command to the communication command requesting the transfer of the contents of the memory 120 area of the self PE 300 is stored in the reply queue 346G.

The concept of “remote access” in this embodiment is the processor 310 of a PE 300.
However, for the memory 120 of another PE 300, its own PE 300
Similar to the memory 120, the function of being directly accessible (data can be read and written) is represented.
The remote access command is a command used to realize this remote access function.

Each of the queues 346A to 346G in the command queue group 346 is selected by an arbiter (not shown) or the like based on an appropriate priority order, and a command data string is output from the selected queue.

The transmission controller 342 receives the command data string output from the selected queue in the command queue group 346 and interprets it. Then, by accessing the memory 120 via the bus interface 341, the multiplexer 343 is controlled to construct a transmission message, and the transmission message is stored in the transmission buffer 347. That is, the command data string interpreted above is the self P
When the command is a command requesting the transfer of data stored in a certain area of the memory 120 of the E300, the bus interface 341 is requested to read the data from the memory 120. In response to this, the data read from the memory 120 by the bus interface 341 is stored in the transmission buffer 347 following the command via the multiplexer 343, and a transmission message is constructed.

The transmission buffer 347 has its own PE in this way.
A message (transmission message) to be transmitted from the other PE 300 to the other PE 300 or a transmission message addressed to the own PE 300 including the data read from the memory 120 of the own PE 300 is stored.

When the destination of the stored message is the self PE 300, the transmission buffer 347 makes the self PE addressed signal output to the arbiter 348 “active”. When a message is stored in the transmission buffer 347, it is output to the arbiter 348 as empty.
Make the S signal "inactive". Then, when the message stored in the transmission buffer 347 is addressed to the self PE 300, the message is sent to the multiplexer 349 as input data. Then, the arbiter 348 adds the message addressed to its own PE and the empty S signal as “active” and “inactive” respectively, so that the message addressed to its own PE output from the transmission buffer 347 from the multiplexer 349 to the reception controller. Select output to 345. On the other hand, the transmission buffer 347 is the other PE.
The message addressed to 300 is output to the mutual connection network interface 344.

The mutual connection network interface 344 sends the message addressed to the other PE 300, which is input from the transmission buffer 347, to the mutual connection network 160. Also, it receives a message addressed to its own PE 300 from the mutual connection network 160 and stores the message in the reception buffer 350.

The reception buffer 350 stores a message (reception message) addressed to its own PE 300, which is input from the mutual connection network interface 344 and transmitted from the other PE 300 via the mutual connection network 200. And
The empty R signal is "deactivated" and applied to the arbiter 348 while storing the received message.

The arbiter 348 receives the empty S signal input from the transmission buffer 347 and the signal addressed to its own PE, and the empty R signal input from the reception buffer 350.
Either the message input from the transmission buffer 347 or the reception message input from the reception buffer 350 is selectively output from the multiplexer 349.

The reception controller 345 interprets the message addressed to its own PE 300 stored in the transmission buffer 347 input via the multiplexer 349 or the message addressed to its own PE 300 stored in the reception buffer 350 and transmitted from the other PE 300. To do. When a data transfer command requesting data transfer to the memory 120 is set in the message, the requested data is transferred to the bus interface 341 and the bus 1.
The data is transferred to the area of the memory 120 designated by the command via 30. On the other hand, in the case of the message in which the command requesting the reply command is set, the reply command is stored in the reply queue 346E or the remote access reply queue 346F. That is, for example, another PE3
00 or processor 310 of own PE 300 is own PE 3
If the message is a message for which a remote access command requesting the reference of the contents of the memory 120 to 00 is set, the reply command is written in the remote access reply queue 346F. Also, the memory 1 of own PE 300
If the message has a command other than the remote access command requesting that the contents of 20 be transferred to the memory 120 of the self PE 300 or another PE 300, the command for the reply is written in the reply queue 346G.

These remote access reply queues 34
The reply command stored in 6F or the reply queue 346G is input to the transmission controller 342. The transmission controller 342 reads the data requested by the reply command from the memory 120 via the bus interface 341, and the data is transmitted to the multiplexer 34.
3 to write to the transmission buffer 347 to construct a reply message.

Next, the internal structure of the bus interface 341 will be described. FIG. 6 is a diagram showing a circuit configuration of a portion that monitors the bus 130 in the bus interface 341 and generates a communication command to be stored in the user transmission queue 346A or the system transmission queue 346B.

The data bus of the bus 130 has a width of 64 bits. The address bus has a width of 36 bits. The Bus Write Data latch circuit 3411 shown in FIG.
The data latch circuit 3411 (hereinafter referred to as the data latch circuit 3411) latches the data output by the processor 310 onto the data bus. Bus Address latch circuit 3412 (hereinafter,
The address latch circuit 3412) latches the address signal output from the processor 310 on the address bus. The processor 310 uses the 0-th bit to the 31st bit (lower word) of the 64-bit width data bus.
Data is output to any one of the bus line of No. 2 or the bus line of 32nd to 63rd bits (upper word). Which of these is to be used to output data depends on the address value output on the address bus, that is, the command entry area 1
It is determined by the write address of the 50 command data string.

Further, on the bus 130, the processor 31
There is a SU flag signal line that indicates whether 0 is executing the process at the user level or the system level. The SU flag signal line is set by the processor 310 to "0" at the user level and to "1" at the system level.

When the processor 310 issues a communication command (user communication command or system communication command), the data string of the command is stored in the command entry area 150 preset in its own address space as described above. Write.

FIG. 6 is a diagram showing an example of a format of a command data string output from the processor 310 on the data bus. The processor 310 sequentially outputs each command data of the first word (32-bit width) to the n-th word shown in the figure onto the data bus.

In the first word, in the 16th to 31st bits, the destination PE, that is, the PE 300 of the command transmission destination, is transmitted.
Identification information is set. The message size is set to the 0th bit to the 19th bit in the second word.

A destination address, a source address, and other parameters 1, 2, ... Are set in the third and subsequent words. The destination address is a data transfer destination address on the memory 120, and the source address is a data transfer source address on the memory 120.

The bus interface 341 is the bus 130.
The address output on the address bus of the bus is constantly monitored, and when it is detected that the address is within the command entry area 150, the data and the address are fetched from the data bus and the address bus of the bus 130, respectively. , And the data latch circuit 3411 and the address latch circuit 3412, respectively.

The SU flag analysis circuit 3413 uses the bus 13
By referring to the SU flag signal line on 0, it is determined whether the data currently output on the data bus is a user level command or a system level command. Then, when the SU flag is “1”, the address value latched by the address latch circuit 3412 is referred to, and the upper word (32nd word) of the data latch circuit 3411 is referred to.
The command data written in the command entry area 160 is extracted from the bit to the 63rd bit) or the lower word (the 0th bit to the 31st bit). This command data is output to the multiplexer 3416S.

The SYSCNT circuit 3414S is a counter for counting necessary to create a system level communication command according to a clock input from a sequencer for controlling the operation timing of the entire bus interface 341 (not shown), and has an initial value. "1" is set. This counter value indicates the word position of the communication command currently being processed.

The command kind embedding circuit 3415S (hereinafter referred to as the command circuit 3415S) receives the count value of "1" from the SYSCNT circuit 3414S.
The data of the first word of the command shown in FIG. 6 is fetched from the data latch circuit 3411, and the address latch circuit 3 is set in the 0th bit to the 13th bit of the data as shown in FIG.
The 14-bit command kind data read from 412 is embedded. The "command kind" data is composed of 7-bit information indicating the kind of command and some flags. Then, the first word of the communication command in which the command kind data is set in this way is output to the multiplexer 3416S.

The multiplexer 3461S is controlled by an arbiter (not shown) and creates / outputs the command shown in FIG. The arbiter controls the selection of the multiplexer 3416S based on the count value information of the SYSCNT 3414S.

The command kind data is cmdsiz.
It is also input and held in the circuit 3417S. Next, the data of the second word of the system level communication command shown in FIG. 7 written in the command entry area 160 is latched in the data latch circuit 3411. This data is SU
PID embedding circuit 3 via flag analysis circuit 3413
419S and the cmdsiz circuit 3417 described above.
It is also input to S.

The cmdsiz circuit 3417S determines the data length of the command, that is, the command, from the message size information set in the 0th to 19th bits of the second word and the command kind data already input and held. Find the word length (command size) of the data string to be composed.

Further, the data latch circuit 3411 latches the data of the second word of the system level communication command, whereby a clock is applied to the SYSCNT circuit 3414S and the SYSCNT circuit 3414S is incremented to "2".

The count value "2" of the SYSCNT circuit 3414S is added to the SYSLEN circuit 3418S as a LOAD signal, and the SYSLEN circuit 3418S receives the cmdsiz circuit 3417S.
Input and hold the above command size from.

Further, the count value "2" of the SYSCNT circuit 3414S is the same as the PID embedding circuit 3419S (hereinafter referred to as PI
D circuit 3419S). PID
When this input is added, the circuit 3419S inputs the second word data shown in FIG. 7 from the data latch circuit 3411 via the SU flag analysis circuit 3413. Then, the PID information held in the register (not shown) is set in the 20th to 31st bits of this data. And
The set data is output to the multiplexer 3416S. The processor 310, when the process switching occurs,
The process ID (P
ID information) is set in the register.

As described above, the command circuit 3415
Data of the first word and the second word of the command shown in FIG. 8 which are respectively created by the S and PID circuits 3419S are sequentially selected and output by the multiplexer 3416S, and the system transmission queue (System Queue) 3
46B is input.

Then, the data latch circuit 3411 sequentially latches the data from the third word onward of the system level communication command. These data are directly transmitted to the multiplexer 341 via the SU flag analysis circuit 3413.
Input to 6S. And a multiplexer 3416S
Are sequentially selected by and input to the system transmission queue 346B.

When the last data of the system level communication command latched by the data latch circuit 3411 is latched and input to the multiplexer 3416S via the SU flag analysis circuit 3413, the SYSCNT
The count value of 3414S becomes the same value as SYSLEN.

Compare circuit (comparator) 3420S
Outputs the End bit data set to a valid value (for example, "1") when the values of both the SYSCNT circuit 3414S and the SYSLEN circuit 3418S become equal. The End bit data is added to the SYSCNT circuit 3414S as a preset signal, and the value of the SYSCNT circuit 3414S is preset to "1".

As described above, the system transmission queue 3
A communication command having a format as shown in FIG. 8 is written in 46B. The above-mentioned SYSCNT circuit 3414S,
command circuit 3415S, multiplexer 3416S,
cmdsiz circuit 3417S, SYSLEN circuit 3418S, PID
A circuit 3410U (user communication command generation circuit 3410U) similar to the circuit 3410S (system communication command generation circuit 3419S) for generating a communication command for the system transmission queue 346B, which includes a circuit 3419S and a compare circuit 3420S, has a user transmission queue 346.
It is provided as a device for generating a user level communication command to be written in A. In this circuit 3410U, the corresponding letter of the corresponding block is shown by changing the letter at the end of the code from "S" to "U".

When the processor 310 sequentially writes the data string of the communication command in the command entry area 150 at the user level, the SU flag signal line on the bus 130 is set to "0". As a result, the SU flag analysis unit 34
13 outputs the data string of the user level communication command output from the processor 310, which is latched by the data latch circuit 3411, to the circuit 3410U. As a result, the same operation as the circuit 3410S described above is performed by the circuit 341.
The circuit 3410U embeds the command kind data latched in the 12th to 25th bits of the address latch circuit in the first word and the "PID information" latched in the internal register in the second word. so,
Generate user level communication commands. Then, the data string of this communication command is input to the user transmission queue 346A. Further, the completion of the input of the data string of the communication command to the user transmission queue 346A is compared by the compare circuit 34.
Detected by 20U (end bit output of valid value).

The End bit may be added to each word of the user level or system level transmission command and stored in the user transmission queue 346A or the system transmission queue 346B. This allows the transmission controller 342 to easily detect the end of each command. In addition, a counter (not shown) may be provided and used to count the number of packets stored in the transmission queue 346A or 346B.

Next, FIG. 9 shows the bus interface 341.
It is the figure which simplified and showed the apparatus which produces | generates the communication command of the remote access stored in the remote access transmission queue 346C provided inside.

The processor 310 accesses a predetermined address area (remote access space) on the address space. In this access, bus 13
The most significant bit (MSB) of the 36-bit address signal output on the 0 address bus is set to "0". Further, in the 25th bit to the 34th bit of the address signal, the PE 30 which is the destination of the remote access command is transmitted.
The identification information rcid of 0 (destination PE 300) is the 0th bit to
The address on the memory 120 of the destination PE 300 is set in the 24th bit. Therefore, the specific address of the memory 120 of the specific PE 300 can be accessed by the 0th bit to the 34th bit of the address signal.

For the remote access command, the processor 310 refers to the contents of the memory 120 of another PE 300,
Update. Further, there are those that realize functions such as exchanging data with the contents of the memory 120 of the other PE 300.
It is designated by each signal line of the signal and the LDST signal.

Remote access command generation circuit 345
0 is data written to a certain area in the remote access space by the processor 310 latched by the data latch circuit 3411, an access address in the remote access space latched by the address latch circuit,
Also, by inputting / analyzing the states of the RD signal, the WR signal, and the LDST signal on the bus 130, the communication command (remote access command) of the remote access issued by the processor 310 by the hardware (not shown) provided inside is transmitted. To generate. Then, the generated remote access command is sent to the remote access transmission queue (Remote Access
Que) Write to 346C. Also, the end of the remote access command is notified by End bit. Remote read commands are created by the RD signal, remote write commands by the WR signal, and remote swap commands by the LDST signal. In the case of the remote write command, both the upper word and the lower word of the data latched by the data latch circuit 3411 are valid. And
In this case, the remote access circuit 3450 reads out the upper word and the lower word in this order from the data latch circuit 341 and writes them in the remote access transmission queue 346C.

Next, FIG. 10 is a block diagram showing a circuit configuration of the bus interface 341 provided with a mechanism for protecting the user communication command generation circuit 3410 shown in FIG. 6 from generating (issuing) an illegal command. . In the figure, the same blocks as those shown in FIG. 6 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the Parameter check circuit 34
60 is newly added. Parameter check circuit 34
The 60 inputs the count value from the USRCNT circuit 3414U, and when the count value is "1", inputs the data of the first word of the command generated by the circuit from the command circuit 3415U. Then, for example, the value of the data is inspected, and if the value is an illegal value that does not fall within a predetermined range, it is determined that an illegal command has been created, and an error signal is sent via the bus 130. Output to the processor 310.

As a result, the processor 310 executes the processing for the creation of the illegal command. Next, FIG. 11 is a diagram showing a configuration example of the reception controller 345 that realizes data transfer to another PE 300 by the message passing function.

The reception controller 345 also supports a data transfer function of designating a destination of transfer data, in addition to the data transfer by the message passing function.
FIG. 12 shows an example of the format of a command related to data transfer used in this embodiment.

Information of the destination PE (Destination PE) is set in the 16th bit to the 31st bit of the first word of this command. The rcid is set to this destination PE. Further, in the 0th bit to the 6th bit, a message kind (Message kind), AS (Source), AS (Destination)
Information of a part of the Command kind data indicating the command kind consisting of is set.

AS (Source) is a field in which information designating a read location of transfer data is set, and is composed of 2 bits. AS (Destination) is a field in which information designating the storage location of transferred data is set, and is composed of 2 bits.

A value of "00" or "10" is set in this AS field. 00: Logical Memory 10: Ring Buffer A ring buffer (Ring Buffer) is a special buffer area provided for communication in the “message passing method”. Ring buffer (Rin) as AS (destination)
g Buffer), it is not necessary to specify the transfer destination address on the memory 120 in the destination PE 300.

On the other hand, AS (destination) is "Logica
When “l Memory” is designated, it is necessary to explicitly designate the storage address of the transfer data on the memory 120 for the destination PE 400.

Next, the "Message kind" will be described. The Message kind specifies the following command by its 3-bit value.

000: PUT 001: GET 010: Remote Write 011: SWAP 100: CSI 101: FOP 111: No Header PUT: The contents of the memory 120 of the self PE 300 are stored in another PE.
A data transmission command to be transferred to the memory 120 of 400.

GET: A data reception command (corresponding to the above remote read command) that transfers the contents of the memory 120 of another PE 300 to the memory 120 of its own PE 400 or returns it to the processor 310 of its own PE 300.

Remote Write: Own PE300
Command of the processor 310 of writing data to the memory 120 of another PE 300 (corresponding to the above remote write command).

SWAP: A command for exchanging data between memory contents and data (corresponding to the above remote swap command). CSI (Compare and Swap Instruction): Memory 120
Read the contents from and compare this with the specified comparison data. If they are equal, the store data is written in the target memory 120. Memory 120 read first
The content of is returned.

FOP (Fetch and Operation): Memory 1
The content is read from 20, and the operation (logical operation such as and, or) specified by the parameter is performed on the content. Then, the data after the operation is written in the memory 120. The contents of the memory 120 read first are returned.

No Header: A special command that does not create a message header (command part). Only data is sent. Among these commands, GET and Remote Wri
te and SWAP correspond to the remote access command. However, in the case of GET, the received data is stored in the memory 120.
What is transferred to is not a remote access command.

FIG. 13 is a diagram for explaining the difference between the data transfer by the "message passing method" using the ring buffer area 120B and the data transfer method for designating the storage destination addresses a and b of the transfer data.

FIG. 14A is a diagram for explaining the data transfer method by the “message passing method”. Data A and B are transferred to other PE3 by "message passing method"
In the case of transfer to 00, message A in which transfer data A and B are added immediately after the command as shown in FIG.
1, B1 may be transmitted to the destination PE 300. That is, it is not necessary to specify the storage address of the destination PE 300 on the memory 120. And the messages A1 and B1
The data A and B are sequentially stored in the ring buffer area 120B provided on the memory 120 in the order of arrival.

On the other hand, in the case of data transfer not according to the "message passing method" shown in FIG. 9B, when transferring the same data A and B to another PE 300, the message A
2 and B2, it is necessary to explicitly specify the storage addresses a and b of the data A and B on the memory 120 of the destination PE 300. The destination PE 300 is the message A
When 2 and B2 are received, the data A and B are stored in the addresses a and b on the own memory 120 designated by the messages A and B.

FIG. 14 shows the remote read command,
The contents of the command type information set in the first word of the message for issuing each remote access command of the remote write command and the remote swap command are shown.

Next, the reception controller 34 shown in FIG.
The configuration and operation of No. 5 will be described. Command interpreter 3451
Receives the message via multiplexer 345. And the AS of the first word of the received message
(destination) Determine the storage location of message data by referring to the information. If the value of the AS (destination) information is "00", that is, "Logical Memory" is specified, the parameters such as the data storage address and the transfer data number set in the received message are DMAed.
The controller 3452 is set and the DMA controller 3452 is activated. As a result, the DMA controller 3452 transfers the data of the received message to the relevant area on the memory 120 via the bus interface 341.

On the other hand, the command interpreter 3451 determines that the value of the AS (destination) information of the received message is "1".
If "0", that is, "Ring Buffer" is designated, the ring buffer management device 3453 is requested to transfer the data of the received message.

The ring buffer management device 3453 uses the write pointer (Writ) to which the storage address of the next data in the ring buffer area 120B on the memory 120 is set.
E-pointer) 34531, sequencer 345
While updating the value of the write pointer 34531 by 32, the data of the received message is continuously transferred to the ring buffer area 120B. The ring buffer management device 3453 includes a read pointer 34533 and a comparator 34534.

In the read pointer 34533, the address of the data to be read next from the ring buffer area 120B is set. This read pointer 34533
Are updated by the processor 310. The comparator 34534 uses the pointers 34531 and 34532 for both the pointers.
Of the ring buffer area 12 by comparing the values of
When the adjacent address of 0B is designated, the buffer full signal indicating that the ring buffer area 120B is full is activated to activate the bus interface 34.
Output to 1. The bus interface 341 outputs the activated buffer full signal to the processor 310 via the bus 130 as an interrupt signal.

The ring buffer management device 3453 is
Command interpreter 3451 and bus interface 341
Since it operates in cooperation with and the circuit scale thereof can be reduced, the increase in the hardware amount of the entire reception controller 345 can be small.

In this embodiment, the processor 310 of the PE 300 is used.
The following shows an example of a program that is executed to issue a communication command other than the remote access command. The following example is a program that issues the PUT command.

Putaddr is an address assigned to the PUT command on the command entry area 150. put (destination PE, source address, size, destination address, other parameter 1, other parameter 2 ...) {Write <destination PE> in putaddr.

Write <size> in putaddr. Write <destination address> in putaddr. Write <source address> in putaddr.

Write <other parameter 1> in putaddr. Write <other parameter 2> in putaddr. ...} The own PE 300 can be designated as the destination PE.

[0155]

According to the first aspect of the present invention, when issuing a desired command, the processor is pre-allocated to the desired command in the command entry area provided as a specific area in its own address space. The parameters of the command may be written in the address. Therefore, by allocating an address area for issuing a user level command to the command entry area and protecting the command entry area by the memory protect function, the processor can issue a command at the user level. Further, this eliminates the need to shift to the system level when issuing a command, so that the overhead can be reduced.

According to the second aspect of the present invention, the reception controller sends the above-mentioned data to the command of the received message via the bus interface 31 when a predetermined special buffer area is designated as a storage destination of the data. Since the data is stored in the buffer area according to the above, it is not necessary to explicitly set the data storage destination in the message, and the data can be transferred by the message passing method. In addition, the hardware to realize this data transfer,
Even if it is provided in the reception controller, since most of the transmission / reception mechanism can be shared, an increase in the amount of hardware can be suppressed.

According to the third aspect of the present invention, when a command requesting to transfer the contents of the memory 12 of the own processor element to another processor element 10 is received by the reception controller 34, the command is transmitted to the transmission controller. 32 is transmitted.

Therefore, the processing of the reply command can be executed by the transmission controller 32, and the amount of hardware can be reduced. In the invention according to claim 4, the bus interface 31 immediately transmits the generated command to the command queue 35.
Since the plurality of commands can be continuously written without waiting for the command processing of the transmission controller 32 to end, the processing efficiency is improved.

According to the fifth aspect of the present invention, a part of the area of the address space of the processor is allocated in advance as an area for issuing a remote access command.
Remote access commands can be generated from the hardware provided in the bus interface 31. Therefore,
The remote access function can be realized by adding a small amount of hardware.

According to the invention described in claim 6, the bus interface 31 writes the generated remote access command in the remote access transmission queue 35A. Therefore, it becomes possible to issue a plurality of remote access commands continuously without waiting for the completion of the command processing of the transmission controller 32.

According to the seventh aspect of the invention, the bus interface generates a system mode transmission command or a user mode transmission command according to the running level when the processor writes the command data string in the command entry area.

Therefore, the processor can control the issuance of the system mode command and the user mode command according to the running level. According to the invention of claim 8, by the bus interface,
The system mode and user mode transmission commands are written in the system transmission queue and the user transmission queue, respectively.

Therefore, by determining in advance which of the system transmission queue and the user transmission queue the transmission command is to be extracted, the transmission controller can process the system mode communication command and the user mode communication command. Can be prioritized. Also, system mode communication commands and user mode communication commands are stored in separate queues, so
Even if the running level of the processor is frequently switched by the user between the user level and the system level, the user mode communication command and the system mode communication command are correctly stored in the queue. Therefore, the processor can issue the above two commands independently at any time.

According to the invention described in claim 9, the message of the command whose processing is completed in the own processor element constructed by the transmission controller by the transfer means is received by the transfer means without passing through the mutual completion network interface. It is transferred to the controller.

Therefore, the processing completed within the own processor element can be performed at high speed. According to the tenth aspect of the invention, the reply command to the communication command requesting the transfer of the data stored in the area of the memory of the own processor element received by the receiving controller via the transfer means is the receiving controller. Written to the reply queue.

Therefore, the receiving controller can continuously issue the reply command without waiting for the completion of the processing of the transmitting controller. According to the eleventh aspect of the invention, the reply command to the message for which the remote access command is set, which is received by the receiving controller via the mutual connection network interface, is written in the remote access reply queue by the receiving controller.

Therefore, the receiving controller can continuously output the reply command to the remote access command requiring the reply message received via the mutual connection network interface without waiting for the completion of the processing of the sending controller.

According to the twelfth aspect of the invention, the type of command is determined by the bus interface according to the address of the command data string written in the command entry area by the processor.

Therefore, the command entry area can be divided into an area for issuing a user command and an area for issuing a system command. According to the thirteenth aspect of the present invention, a part of the area in the command entry area in which the processor can write the command data string when running at the user level is protected by the memory protection means. Can be limited to areas.

Therefore, the types of commands that can be issued at the user level can be restricted. According to the fourteenth aspect of the present invention, the bus interface counts the number of command data written in the command entry area according to the type of the command written in the command entry area by the processor by the detection means. Then, the end of the command data string is detected.

Therefore, by using this detection information, it is possible to suppress the issuance of uncompleted commands stored in the queue. Also, if multiple queues are prepared according to the type of command, it is sufficient to retrieve the completed command from the queue that stores the completed command and process it. Can be reduced and the processing efficiency can be improved.

According to the fifteenth aspect of the invention, the bus interface checks the validity of a portion of the command data string based on the count value of the command data by the checking means.

Therefore, the issuance of an illegal command can be prevented. According to the sixteenth aspect of the invention, the bus interface adds the information used in the system to a certain portion of the command data string based on the count value of the command data by the information adding means.

Therefore, various information can be embedded in any part of the command data string.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a principle diagram of the present invention.

FIG. 2 is a block diagram showing an overall configuration of a processor element according to the first exemplary embodiment of the present invention.

FIG. 3 is a diagram illustrating the concept of a command entry area.

FIG. 4 is a block diagram showing an overall configuration of a processor element according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing an overall configuration of a processor element according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing a circuit configuration of a portion for generating a system command and a user command in the bus interface of the third embodiment.

FIG. 7 is a diagram illustrating a format of a command data string output by the processor on the data bus in the third embodiment.

FIG. 8 is a diagram illustrating a format of a system level communication command generated by a bus interface in the third embodiment.

FIG. 9 is a block diagram showing a schematic configuration of a portion for generating a remote access command in the bus interface in the third embodiment.

FIG. 10 is a block diagram showing a circuit configuration of a bus interface to which a parameter check function is added.

FIG. 11 is a block diagram showing a circuit configuration of a reception controller having a data transfer function in a message passing system in the third embodiment.

FIG. 12 is a diagram showing a format of a remote access command.

FIG. 13 is a diagram illustrating a data transfer method using a message passing method and a data transfer method other than this.

FIG. 14 is a diagram showing the contents of command type information set in the first word of a message that issues a remote read command, a remote write command, and a remote swap command.

FIG. 15 is a diagram illustrating an overall configuration of a parallel computer.

[Explanation of symbols]

 10 processor elements 11 processor 12 memory 20 mutual communication network 30 communication control device 31 bus interface 31A detecting means 31B checking means 31C information adding means 32 transmission controller 33 mutual coupling network interface 34 reception controller 35 command queue 35A remote access transmission queue 35B system transmission Queue 35C User send queue 35D Reply queue 35E Remote access send queue

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Shimizu 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Hiroaki Ishihata 1015, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (16)

[Claims] 1. A parallel computer system in which a plurality of processor elements (10) are connected via an interconnection network (20), in a communication control device (30) mounted in each processor element (10), a processor element The writing of the command data string to the predetermined command entry area by the processor (11) in (10) is detected, the command is generated from the command data string, and the self processor element (1
0) a bus interface (31) for controlling reading / writing of data from / to the memory (12), and a transmission controller (32) for interpreting a command generated by the bus interface (31) and constructing a transmission message. Sending a send message constructed by the send controller (32) to the interconnection network (20),
From the mutual connection network (20) to its own processor element (10)
An interconnection network interface (33) for receiving a message addressed to the interconnection interface, interprets the message received by the interconnection network interface (33), and transfers the data transferred by the message via the bus interface (31). And a reception controller (34) for storing in a designated area of a memory (12) of its own processor element (10). 2. The reception controller (34), when a special buffer area predetermined as a data storage destination is designated in the command of the received message,
The communication control device according to claim 1, wherein the data of the received message is stored in the buffer area via the bus interface (31). 3. The reception controller (34), when receiving a command requesting to transfer the contents of the memory (12) of its own processor element (10) to another processor element (10), When transmitted to the transmission controller (32), the transmission controller (32) receives the command and is requested by the command from the memory (12) of its own processor element (10) via the bus interface (31). The communication control apparatus according to claim 1, wherein the data is read and a message for transmitting the data is constructed. 4. The communication control device according to claim 1, further comprising a command queue (35) in which a command generated by the bus interface (31) is written. 5. When the bus interface (31) detects an access to a certain address area by the processor (11), the processor (11) accesses the memory (12) of another processor element (10). The communication control device according to claim 3, further comprising a mechanism for generating a remote access command for performing the communication. 6. The communication control device according to claim 5, further comprising a remote access transmission queue (35A) in which the remote access command generated by the bus interface (31) is written. 7. The bus interface (31) generates a system mode communication command from a command data string written in the command entry area when the processor (11) is running at a system level,
The communication control device according to claim 1, wherein a communication command in a user mode is generated from a command data string written in the command entry area when the processor (11) is running at a user level. 8. A system transmission queue (35B) in which the communication command in the system mode generated by the bus interface (31) is written, and a user transmission queue (35C) in which the communication command in the user mode is written. The communication control device according to claim 7, further comprising: the transmission controller (32) extracting a communication command from the system transmission queue (35B) or the user transmission queue (35C) and executing the communication command. . 9. The reception controller (34) sends a message of a command whose processing is completed in its own processor element (10) constructed by the transmission controller (32) without passing through the mutual connection network interface (33). )
2. The communication control device according to claim 1, further comprising a transfer unit (36) for transferring to the. 10. The reception controller (34) requests transfer of data received via the transfer means (36) and stored in an area of a memory (12) of its own processor element (10). A reply queue (35) in which a reply command to a message for which a communication command is set is written by the reception controller (34).
D) is further provided, The said transmission controller (32) takes out the said communication command from the said reply queue, and performs the said communication command via the said bus interface (31), The said 9 characterized by the above-mentioned. The communication control device described. 11. The memory (12) contents of its own processor element (10), issued from another processor element (10), received by the reception controller (34) via the mutual connection network interface (33). The reply command to the message in which the remote access command requesting the reference of
4) A remote access reply queue (35E) written by the above is further provided, and the transmission controller (32) extracts the remote access command from the remote access reply queue (35E), and through the bus interface (31). 2. The content of the memory (12) of the own processor element (10) requested by the remote access command is read to construct a transmission message addressed to the other processor element (10). Communication control device. 12. The bus interface (31) comprises:
The communication control device according to claim 1, wherein the processor (10) determines the type of command according to an address of a command data string written in the command entry area. 13. The processor (11) further comprises memory protection means (37) for limiting an area in the command entry area in which the command data string can be written when running at a user level. 13. The communication control device according to claim 12, wherein: 14. The bus interface (31) comprises:
A detection unit (3) that detects the end of the command data string by counting the number of command data written in the command entry area according to the type of command written by the processor (11) into the command entry area.
1A) is provided, Claims 1, 4, 6, 8, 10,
Alternatively, the communication control device according to item 11. 15. The bus interface (31) comprises:
15. The communication control device according to claim 14, further comprising a check unit (31B) for checking the validity of a portion of the command data string based on the count value of the command data. 16. The bus interface (31) comprises:
15. The communication control device according to claim 14, further comprising an information adding unit (31C) for adding information used in the system to a certain portion of the command data string based on the count value of the command data. .