JP2009245005A - Data processor, data processing method and data processing program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce pressure on a band of a bus by transfer of data. <P>SOLUTION: This data processor has: a data storage part inputted with data from a storage device, temporarily storing the inputted data; an address information storage part storing address information for specifying data to be taken-in; and a data processing part processing the read data, and setting address information of next needed data in an address storage part. When the inputted data is transferred to the data storage part via the bus, the data processor monitors the data flowing on the bus, and takes the data in the data processing part when the data corresponding to the address information flows. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present case relates to a data processing device, a data processing method, and a data processing program. In particular, the present invention relates to a data processing device, a data processing method, and a data processing program that process a large amount of data such as moving images as input data.

  Conventionally, a data transfer method used in a computer system includes a transfer method called DMA (Direct Memory Access) (see Patent Document 1).

  There is a data processing device that uses DMA as a data transfer method and performs data processing (for example, image processing) on data stored in an external device (for example, a camera). The SRAM (Static Random Access Memory) of the CPU that executes data processing in this data processing device has a high data access speed, but the data storage capacity is usually larger than the data amount of data stored in the external device. Is also small. On the other hand, a storage device such as an SDRAM used for the main memory or a memory stored in another external device has a large amount of stored data but has a lower access speed than an SRAM.

  Therefore, the data processing device temporarily stores data stored in the external device in a storage medium such as an SDRAM (Synchronous Dynamic Random Access Memory) having a storage capacity capable of storing data stored in the external device. Transfer and store.

  The data processing apparatus generally divides and transfers data from the SDRAM to the SRAM according to the progress of data processing by the CPU, and completes the data processing.

  The data transfer method using DMA by the data processing apparatus will be specifically described below with reference to FIG. FIG. 8 is a diagram for explaining the outline of the prior art. As shown in FIG. 8A, the data processing apparatus includes input / output control units 11 to 13 connected by a bus.

  Here, the input / output control unit 11 is connected to an external device, and the input / output control unit 12 is connected to the SDRAM. The input / output control unit 13 is connected to a CPU having a data processing unit that executes data processing and an SRAM.

  Under such a configuration, first, the CPU transmits address information A to the DMA controller in order to transfer data stored in the external device to the SDRAM.

  Here, the address information A is information for causing the DMA controller to execute control for transferring data stored in the external device (see (1) in FIG. 8B) to the SDRAM. . For example, the address information A includes device information indicating that the device that executes the data reading process is the input / output control unit 11, and an address that specifies the start point of the storage area where the data is stored in the external device. The device information indicating that the device that executes the data writing process is the input / output control unit 12, the address specifying the start point of the storage area in the SDRAM where the data is to be stored, and the external device are transferred to the SDRAM. This information includes an address length indicating the length of data. Instead of the data length, an end address indicating the end of the transfer data may be used.

  The DMA controller that has received the address information A sends out the address information A-1 via the bus. Here, the address information A-1 is a part of the data specified by the address information A (see (2) in FIG. 8B) from the external device to the input / output control units 11 and 12. This is information for executing control to be transferred to the SDRAM.

  Subsequently, the DMA controller causes the input / output control unit 11 to send the data specified by the address information A-1 onto the bus. Then, the DMA controller causes the input / output control unit 12 to capture data flowing on the bus and store it in the SDRAM.

  Similarly, the DMA controller sends the address information A-2 and A-3 via the bus and transfers the data specified by the address information A by causing the external device to transfer the data to the SDRAM. .

  After the transfer of the data specified by the address information A is completed, the CPU transmits the address information B to the DMA controller in order to transfer the data stored in the SDRAM to the SRAM.

  Here, the address information B is information for causing the DMA controller to execute control to transfer a part of the data stored in the SDRAM (see (1) in FIG. 8C) to the SRAM. It is. For example, the address information B includes device information indicating that the device that executes the data reading process is the input / output control unit 12, an address that specifies the start point of the storage area in which data is stored in the SDRAM, Device information indicating that the device that executes the data writing process is the input / output control unit 13, an address that specifies the start point of the storage area in the SRAM where the data is to be stored, and the data to be transferred from the SDRAM to the SRAM This information includes an address length indicating the length.

  Subsequently, the DMA controller sends out address information B-1 via the bus. Then, the DMA controller causes the input / output control unit 12 to read the data specified by the address information B-1 and send the data onto the bus. Then, the DMA controller causes the input / output control unit 12 to capture data flowing on the bus and store it in the SRAM.

  Thereafter, the DMA controller sends address information B-2 and B-3 via the bus according to the progress of data processing by the CPU, and divides and transfers the data from the SDRAM to the SRAM. Complete the transfer of the data specified by B.

JP 2003-006139 A

  By the way, the above-described conventional technique has a problem of pressing the bandwidth of the bus. That is, the conventional data processing apparatus uses the same data on the bus in two situations when transferring data stored in the external device to the SDRAM and when dividing and transferring the data from the SDRAM to the SRAM. There is a problem of compressing the bus bandwidth in order to send out the message.

  Therefore, the data processing apparatus, the data transfer method, and the data processing program are made to solve the above-described problems of the prior art, and are data that can reduce the compression of the bus bandwidth due to the data transfer. It is an object to provide a processing device, a data transfer method, and a data processing program.

  In order to solve the above-described problems and achieve the object, the disclosed data processing apparatus is a data processing apparatus that processes data, and is a data that inputs data from a storage device and temporarily stores the input data A storage unit; an address information storage unit that stores address information that identifies data to be captured; a data processing unit that performs data processing on the read data and sets address information of the next necessary data in the address storage unit; When the input data is being transferred to the data storage unit via the bus, the data flowing on the bus is monitored, and when the data corresponding to the address information flows, the data is It is necessary to provide data fetching means for fetching into the data processing unit.

  Further, the disclosed data transfer method is a data processing method for processing data by a data processing device, wherein data is input from a storage device and the input data is temporarily stored; An address information storage unit for storing address information to be identified; a data processing unit for processing the read data and then setting address information of necessary data in the address storage unit; and the input data However, when data is transferred to the data storage unit via the bus, the data flowing on the bus is monitored, and when data corresponding to the address information flows, the data is transferred to the data processing unit. It is necessary to include a data fetching step to be fetched.

  Further, the disclosed data transfer program is a data processing program for causing a computer as a data processing device to process data, inputs data from a storage device, and temporarily stores the input data; An address information storage unit that stores address information that identifies data to be captured, data processing the read data, and then setting the address information of the necessary data in the address storage unit; When the input data is transferred to the data storage unit via the bus, the data flowing on the bus is monitored, and when the data corresponding to the address information flows, the data is The data acquisition procedure to be taken into the storage unit referenced by the data processing procedure is executed by the computer as the data processing device. It requires Rukoto.

  According to the disclosed data processing device, data transfer method, and data processing program, it is possible to reduce the compression of the bus bandwidth due to the data transfer.

  Exemplary embodiments of a data processing device, a data transfer method, and a data processing program according to the present invention will be explained below in detail with reference to the accompanying drawings. Hereinafter, a case where the present invention is applied to a data processing apparatus (for example, an image processing apparatus) that uses DMA as a data transfer method will be described as an embodiment.

  In the following first embodiment, the outline and features of the data processing apparatus according to the first embodiment, the configuration of the data processing apparatus, the processing flow of the data processing apparatus will be described in order, and finally the effects of the first embodiment will be described.

[Outline and Features of Data Processing Device According to Embodiment 1]
First, the outline and features of the data processing apparatus according to the first embodiment will be described with reference to FIG. FIG. 1 is a diagram for explaining the outline and features of the data processing apparatus according to the first embodiment.

  The data processing apparatus according to the first embodiment includes a data storage unit that inputs data from a storage device and temporarily stores the input data, and an address information storage unit that stores address information that specifies data to be captured. A data processing unit that processes the read data and sets address information of the next necessary data in the address storage unit.

  Under such a configuration, the data processing apparatus according to the first embodiment is mainly characterized by reducing the compression of the bus bandwidth due to the data transfer.

  That is, as shown in FIG. 1, the data processing apparatus according to the first embodiment monitors data flowing over the bus when input data is being transferred to the data storage unit via the bus. When data corresponding to the address information flows, this data is taken into the data processing unit.

  For this reason, the data processing apparatus according to the first embodiment can reduce the compression of the bus bandwidth due to the data transfer as described above.

[Data processor configuration]
Next, the configuration of the data processing apparatus shown in FIG. 1 will be described with reference to FIGS. FIG. 2 is a block diagram showing the configuration of the data processing apparatus. FIG. 3 is a diagram for explaining the situation of the first embodiment. As shown in FIG. 2, the data processing apparatus 10 includes input / output control units 11 to 13, a data storage unit 14, a CPU 15, a DMA controller 16, and a bus monitoring unit 17.

  Here, the input / output control units 11 to 13, the DMA controller 16, and the bus monitoring unit 17 are connected via a bus 18. The input / output control unit 11 is connected to a storage device (not shown) (for example, an external device installed outside the data processing device 10 or a built-in hard disk included in the data processing device 10). Connected to the storage unit 14, the input / output control unit 13 and the bus monitoring unit 17 are connected to the CPU 15.

  As particularly closely related to the present invention, the CPU 15 includes a memory 15a and a data processing unit 15b, and the bus monitoring unit 17 includes a register 17a and a data capturing unit 17b.

  The “data storage unit” described in the claims corresponds to, for example, the data storage unit 14, the “data processing unit” corresponds to, for example, the CPU 15, and the “data fetching unit” includes, for example, a bus Corresponding to the monitoring unit 17, the “address information storage unit” corresponds to the register 17a.

  Under such a configuration, in the following, when data specified by the address information A (see (1) in FIG. 3) is transferred from the external device to the data storage unit 14, the data specified by the address information A A situation in which a part of data specified by the address information A-1 (see (2) in FIG. 3) is stored in the memory 15a will be described in detail.

  Here, the address information A and the address information A-1 are the device information indicating that the device that executes the data reading process is the input / output control unit 11, and the storage area where the data is stored in the storage device. An address for specifying the start point, device information indicating that the device that executes the data writing process is the input / output control unit 12, and a start point of the storage area where the data storage unit 14 is to store data are specified. This is information including an address and an address length indicating the length of data transferred from the storage device to the data storage unit 14. The address information A-1 is information for specifying a part of the data specified by the address information A.

  Note that the configuration of the address information A-1 does not specify the present invention, and includes an input source start address, an output destination address of the memory 15a in the CPU 15, and an address length indicating the length of data to be extracted. Any information can be applied. Further, the address information A-1 may not include the address length when the length of data transferred to the data storage unit via the bus is constant.

  The input / output control units 11 to 13 shown in FIG. 2 have ports, adapters, VIN (Video Input), and the like. Under the control of the DMA controller 16, data input to the storage units connected to each of them is performed. Control the output.

  For example, when the input / output control unit 11 receives a read instruction including the address information A-1 flowing on the bus 18, the input / output control unit 11 sends data to the DMA controller 16 except when a failure such as a processing error has not occurred. An RDY signal indicating that preparation for reading is completed is returned. Then, the input / output control unit 11 reads the data specified by the address information A-1 from the storage unit of the storage device and sends it out on the bus 18.

  When the input / output control unit 12 receives the write instruction including the address information A-1 flowing on the bus 18, the input / output control unit 12 sends data to the DMA controller 16 except when a failure such as a processing error has not occurred. An RDY signal indicating that preparation for writing is completed is returned. The input / output control unit 12 takes in data flowing on the bus 18 and stores the data in the data storage unit 14.

  The data storage unit 14 inputs data from the storage device and temporarily stores the input data. Specifically, the data storage unit 14 corresponds to a main memory (for example, SDRAM) whose transfer speed is slower than that of the memory 15a, and stores data captured by the input / output control unit 12.

  The memory 15a stores data and programs necessary for various processes by the CPU 15. Specifically, the memory 15a corresponds to a cache memory (for example, SRAM (Static Random Access Memory)) having a high transfer rate, stores a data processing program that defines a processing procedure of data processing, and stores data. To do.

  The data processing unit 15b processes the data by a program that defines various processing procedures. Specifically, the data processing unit 15b corresponds to a CPU core chip, and when receiving a data processing start instruction, stores the address information A-1 in the register 17a. Subsequently, the data processing unit 15b transmits address information A to the DMA controller 16 and requests data transfer processing. Then, the data processing unit 15b performs data processing on the data stored in the memory 15a.

  The DMA controller 16 controls data flowing on the bus 18. Specifically, when the DMA controller 16 receives a request for data transfer processing including the address information A from the data processing unit 15b, the DMA controller 16 issues a write instruction to the input / output control unit 12 including the address information A-1 on the bus 18. Send it up. Subsequently, when the DMA controller 16 receives the RDY signal from the input / output control unit 12, the DMA controller 16 sends a read instruction to the input / output control unit 11 including the address information A- 1 onto the bus 18.

  Subsequently, when the DMA controller 16 receives the RDY signal from the input / output control unit 11, the DMA controller 16 controls the input / output control unit 11 to read data from the storage device, and controls the input / output control unit 12 on the bus 18. Control is performed to capture the flowing data and store the data in the data storage unit 14.

  The register 17a stores address information that specifies data to be captured. Specifically, the register 17a stores address information A-1.

  When the input data is being transferred to the data storage unit 14 via the bus, the data capturing unit 17b monitors the data flowing on the bus 18 and if data corresponding to the address information flows. This data is taken into the CPU 15.

  Specifically, when receiving a write instruction addressed to the input / output control unit 12 including the address information A-1 flowing on the bus 18, the data fetching unit 17b matches the address information stored in the register 17a. Make sure. Subsequently, the data fetch unit 17b monitors data flowing on the bus 18, fetches data flowing on the bus 18, and stores the data in the memory 15a.

  In other words, the data fetching unit 17b confirms that the address information included in the write instruction addressed to the input / output control unit 12 sent from the DMA controller 16 to the bus 18 matches the address information stored in the register 17a. Confirm. Then, the data fetching unit 17b stores the data addressed to the input / output control unit 12 sent to the bus 18 due to the write instruction in the memory 15a.

[Processing by data processing device]
Next, processing performed by the data processing apparatus 10 will be described with reference to FIG. FIG. 4 is a flowchart showing the flow of processing by the data processing apparatus.

  As shown in FIG. 4, when a data processing start instruction is accepted (step S1001: Yes), the data processing apparatus 10 stores address information in the register 17a (step S1002).

  Subsequently, the data processing apparatus 10 monitors the data flowing on the bus 18 when the input data is being transferred to the data storage unit 14 via the bus, and the data corresponding to the address information is displayed. When it flows, this data is taken into the CPU 15 (step S1003). Then, the data processing device 10 processes the data (step S1004) and ends the process.

[Effect of Example 1]
As described above, according to the first embodiment, it is possible to reduce the compression of the bus bandwidth due to the data transfer. For example, according to the first embodiment, in the data transferred from the storage device to the data storage unit 14, the remaining data that has not been taken into the memory 15a is changed according to the progress of data processing by the data processing unit 15b. Since it is sufficient to transfer the data from the data storage unit 14 to the memory 15a, it is possible to reduce the compression of the bus bandwidth due to the data transfer.

  Further, according to the first embodiment, it is possible to reduce the processing procedure for transferring data. For example, according to the first embodiment, when the data amount of data stored in the storage device is smaller than the data storage capacity of the memory 15a, the data processing unit 15b performs data processing according to the progress of data processing. The processing procedure transferred from the storage unit 14 to the memory 15a can be reduced.

  Further, according to the first embodiment, it is not necessary to change the data flow control method by the DMA controller 16, so that the mounting is easy.

  By the way, in the first embodiment, the bus monitoring unit 17 has a register 17a and a data capturing unit 17b, and the data capturing unit 17b of the bus monitoring unit 17 monitors the data flowing on the bus 18 to obtain an address. The case where data corresponding to information is taken into the CPU 15 has been described.

  However, the present invention can be realized even if the DMA controller 16 executes a process of preferentially extracting data corresponding to the address information and transferring it to the CPU 15. Therefore, in the second embodiment, a case will be described in which the DMA controller 16 preferentially takes out data corresponding to address information and transfers it to the CPU 15. In the second embodiment, the configuration of the data processing apparatus according to the second embodiment and the effects of the second embodiment will be described.

[Configuration of Data Processing Apparatus According to Second Embodiment]
As shown in FIG. 5, the configuration of the data processing apparatus 10 according to the second embodiment is similar to that of the first embodiment except that the DMA controller 16 includes a register 16a and a data fetching unit 16b. 1 differs from the data processing apparatus 10 according to 1 in the following points. FIG. 5 is a block diagram illustrating the configuration of the data processing apparatus according to the second embodiment.

  That is, when the input / output control unit 13 receives a write instruction including the address information A-1 flowing on the bus 18, the input / output control unit 13 sends data to the DMA controller 16 except when a failure such as a processing error has not occurred. An RDY signal indicating that preparation for writing is completed is returned. The input / output control unit 12 takes in data flowing on the bus 18 and stores the data in the data storage unit 14.

  When receiving the data processing start instruction, the data processing unit 15b stores the address information A-1 in the register 16a. The register 16a stores address information A-1.

  The data take-in unit 16b monitors the data flowing on the bus based on the address information, preferentially takes out the data, and transfers it to a predetermined address. Specifically, the data fetch unit 16b sends a write instruction to the input / output control unit 13 including the address information A-1 stored in the register 16a onto the bus 18.

[Effect of Example 2]
As described above, according to the second embodiment, the DMA controller 16 executes a process of preferentially extracting data corresponding to the address information and transferring it to the CPU 15 to reduce the compression of the bus bandwidth due to the data transfer. It is possible.

  Further, according to the second embodiment, by changing the processing by the DMA controller 16, it is possible to reduce the compression of the bus bandwidth due to the data transfer, so that the mounting is easy.

  The present invention may be implemented in various different forms other than the first and second embodiments described so far. Therefore, another embodiment will be described below as a third embodiment.

  For example, in the first and second embodiments, a case has been described in which input data is transferred from the storage device to the data storage unit 14 via the bus 18 and data monitored based on the address information is transferred to the CPU 15. However, the transfer destination of data flowing on the bus 18 is not limited to the data storage unit 14.

  For example, a dummy memory to which only an address is assigned is provided without storing data, and the DMA controller 16 transfers data to the dummy memory, and data flowing on the bus 18 is taken out based on the address information. The present invention can also be applied to the case where data is monitored and data to be extracted is preferentially extracted and transferred to the CPU 15.

  In the first embodiment, the case where the CPU 15 and the bus monitoring unit 17 are individually provided has been described. However, as shown in FIG. 6, the bus monitoring unit 17 may be included in the CPU 15. FIG. 6 is a block diagram illustrating the configuration of the data processing apparatus according to the third embodiment.

  A device for processing data is not limited to the CPU 15. For example, when an FPGA (Field Programmable Gate Array) is provided with a data processing function and the data read from the storage device is stored in the data storage unit 14, this FPGA has a part or all of the data. You may make it take in to a memory | storage part.

  In addition, it is assumed that input data input from the storage device is moving image data, and the CPU 15 performs object detection or tracking processing of the moving image. Here, the CPU 15 detects the object to be detected or tracked, estimates the next position of the object to be preferentially extracted from the moving image data, obtains address information of the portion of the moving image data to be preferentially extracted, and As information, the start address of the input source, the output destination address of the high-speed memory in the CPU 15, and the address length indicating the length of data to be extracted are set in the register 17a (or 16a). The DMA controller 16 preferentially transfers the corresponding data from the input data input from the storage device to the high-speed memory (such as the memory 15a) based on the address information from the data transmitted via the bus 18. To do. By doing so, it is also possible to preferentially transfer the data of the object to be detected or tracked to the high-speed memory.

  Further, the processing procedures, control procedures, specific names, information including various data and parameters shown in the above-mentioned documents and drawings can be arbitrarily changed unless otherwise specified.

  Further, each component of each illustrated apparatus is functionally conceptual, and does not necessarily need to be physically configured as illustrated. In other words, the specific form of distribution / integration of each device is not limited to that shown in the figure, and all or a part thereof may be functionally or physically distributed or arbitrarily distributed in arbitrary units according to various loads or usage conditions. Can be integrated and configured. For example, a plurality of CPUs 15 shown in FIG. 2 can be provided. Further, the input / output control unit 13 and the bus monitoring unit 17 shown in FIG.

  Furthermore, all or a part of each processing function performed in each device is realized by a CPU (not shown) different from the CPU 15 and a program analyzed and executed by the CPU, or wired. It can be realized as hardware by logic.

  By the way, the present invention may be realized by executing a program prepared in advance by a computer as the data processing apparatus 10. Therefore, in the following, a computer that executes a data processing program having the same function as that of the data processing apparatus 10 shown in the above embodiment will be described as an example with reference to FIG. FIG. 7 is a diagram illustrating a computer that executes a data processing program.

  As shown in the figure, the computer 110 as the data processing apparatus 10 includes an input / output control unit 111 to 113, a ROM 120, a CPU 130, a bus monitoring unit 140, a data storage unit 150, and a DMA controller 160 connected by a bus 170 or the like. Composed.

  In the ROM 120, a data processing program that exhibits the same function as that of the data processing apparatus 10 shown in the first embodiment, that is, a data processing program 121 and a data capturing program 122 as shown in FIG. It is remembered. Note that the data processing program 121 and the data capture program 122 may be appropriately integrated or distributed as in the case of each component of the data processing apparatus 10 shown in FIG.

  Then, the CPU 130 reads out the data processing program 121 from the ROM 120 and the bus monitoring unit 140 reads out and executes the data acquisition program 122 from the ROM 120, so that the data processing program 121 becomes the data processing process 131 as shown in FIG. In addition, the data capture program 122 functions as the data capture process 141. The data processing process 131 corresponds to the data processing unit 15b illustrated in FIG. 2, and the data capturing process 141 corresponds to the data capturing unit 17b illustrated in FIG.

  Note that the data processing program 121 and the data capturing program 122 are not necessarily stored in the ROM 120 from the beginning. For example, a flexible disk (FD), a CD-ROM, “Portable physical media” such as DVD discs, magneto-optical discs, IC cards, etc., or “fixed physical media” such as HDDs provided inside and outside of the computer 110, as well as public lines, the Internet, LAN, WAN, etc. Each program may be stored in “another computer (or server)” connected to the computer 110 via the computer 110, and the computer 110 may read and execute each program from this.

  The data processing method described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program can be distributed via a network such as the Internet. The program can also be executed by being recorded on a computer-readable recording medium such as a hard disk, a flexible disk (FD), a CD-ROM, an MO, and a DVD and being read from the recording medium by the computer.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining an overview and features of a data processing apparatus according to a first embodiment. It is a block diagram which shows the structure of a data processor. It is a figure for demonstrating the situation of Example 1. FIG. It is a flowchart figure which shows the flow of a process by a data processor. FIG. 10 is a block diagram illustrating a configuration of a data processing device according to a second embodiment. FIG. 10 is a block diagram illustrating a configuration of a data processing device according to a third embodiment. It is a figure which shows the computer which executes a data processing program. It is a figure for demonstrating the outline | summary of a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Data processor 11-13 Input / output control part 14 Data storage part 15 CPU
15a memory 15b data processing unit 16 DMA controller 16a register 16b data capturing unit 17 bus monitoring unit 17a register 17b data capturing unit 18 bus 110 computer 111 to 113 input / output control unit 120 ROM (Read Only Memory)
121 Data Processing Program 122 Data Acquisition Program 130 CPU (Central Processing Unit)
131 Data Processing Process 140 Bus Monitoring Unit 141 Data Acquisition Process 150 Data Storage Unit 160 DMA Controller 170 Bus

Claims (7)

A data processing device for processing data,
A data storage unit for inputting data from a storage device and temporarily storing the input data;
An address information storage unit storing address information for specifying data to be captured;
A data processing unit that processes the read data and sets address information of the next necessary data in the address storage unit;
When the input data is transferred to the data storage unit via the bus, the data flowing on the bus is monitored, and when the data corresponding to the address information flows, the data is A data processing apparatus comprising data fetching means for fetching into a data processing unit. The data processing device includes a CPU, a cache memory having a high transfer speed, a main memory having a transfer speed slower than the cache memory, and a DMA controller for transferring data from the storage device to the main memory,
The data storage unit for temporarily storing the input data is a main memory,
Transferring input data from the storage device to the data storage unit via the bus, monitoring based on the address information, preferentially retrieving the corresponding data, and transferring to a predetermined address is a DMA. The data processing apparatus according to claim 1, wherein the data processing apparatus is a controller. The data processing apparatus further includes a dummy memory assigned only an address without storing data,
According to the predetermined address, input data from the storage device is transferred to the data storage unit or the dummy storage unit via the bus, and monitored whether the data is extracted based on the address information. 2. A data processing apparatus according to claim 1, wherein the data controller is preferentially fetched and transferred to the main memory or the dummy address in accordance with the address information by a DMA controller. The address information includes an input source start address, an output destination address of a high-speed memory in the CPU, and an address length indicating the length of data to be extracted,
4. The data processing according to claim 2, wherein the DMA controller transfers input data from the storage device to the high-speed memory through the bus and data having the length of the address length. 5. apparatus. The input data is moving image data, and the data processing unit performs moving object detection or tracking processing,
The data processing unit detects the object to be detected or tracked, estimates the next position of the object to be preferentially extracted from the moving image data, and obtains address information of a portion of the moving image data to be preferentially extracted. As the address information, the input source start address, the output destination address of the high-speed memory in the CPU, and the address length indicating the length of the data to be extracted are set in the address information storage unit,
The DMA controller preferentially transfers corresponding data from the input data of the storage device to the high-speed memory based on the address information from among data transmitted via the bus. The data processing device according to any one of claims 2 to 4. A data processing method for processing data by a data processing device,
A data storage unit for inputting data from a storage device and temporarily storing the input data;
An address information storage unit storing address information for specifying data to be captured;
A data processing unit that processes the read data and then sets address information of the necessary data in the address storage unit;
When the input data is transferred to the data storage unit via the bus, the data flowing on the bus is monitored, and when the data corresponding to the address information flows, the data is A data processing method comprising a data fetching step for fetching into a data processing unit. A data processing program for causing a computer as a data processing device to process data,
A data storage unit for inputting data from a storage device and temporarily storing the input data;
An address information storage unit storing address information for specifying data to be captured;
A data processing procedure for processing the read data and then setting the address information of the necessary data in the address storage unit;
When the input data is transferred to the data storage unit via the bus, the data flowing on the bus is monitored, and when the data corresponding to the address information flows, the data is A data acquisition procedure to be taken into the storage unit referred to by the data processing procedure;
A data processing program executed by a computer as a data processing apparatus.

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