JPH08305563A - Data processing unit - Google Patents

Abstract

PURPOSE: To provide the data processing unit to support a conditional arithmetic instruction in which the processing efficiency is improved without causing problems such as performance deterioration due to a limit of a degree of freedom of operands or kinds of instructions and increase in program memory capacity due to increase in an instruction code length. CONSTITUTION: The processing unit is provided with a condition selection means selecting at least one condition among plural conditions to be used for a conditional arithmetic instruction, a conditional information storage means 103 (CSR) storing condition information selected by the condition selection means, and a means 104 (CCR) storing information denoting property of the result of arithmetic operation based on at least the selected condition and the conditional arithmetic instruction has a function to execute required arithmetic processing one of selected conditions is designated and the condition is established.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device that supports conditional operation instructions, and more particularly, by reducing the number of bits required for a branch condition specification field of a conditional operation instruction, the instruction type and operand The present invention relates to a data processing device capable of suppressing an increase in the memory capacity for storing a program due to a decrease in performance due to the limitation of the degree of freedom and an increase in instruction code length.

[0002]

2. Description of the Related Art In the highly advanced information processing society in recent years, digital signal processing is performed in various fields. As hardware therefor, a system LSI usually called a microprocessor or a digital signal processor (DSP) is used. It is used. These system LSIs are usually provided with a general-purpose instruction set in order to be applied to various purposes. Among various uses, there is a simple process that needs to be executed in accordance with a fixed order of a series of instructions, but the process contents to be executed generally differ depending on the conditions that are satisfied. In that case, it is necessary to first determine whether or not a predetermined condition is satisfied, and select an instruction to be processed according to the determination result. Therefore, the conventional general system LSI has a conditional branch instruction. FIG. 15 shows an example of a flowchart of branch processing by a conditional branch instruction.

In FIG. 15, first, a predetermined arithmetic operation 1 is executed in step 150, and then it is determined in step 151 whether the operation result of the previous step 150 is a positive number (including 0). If the determination result is a negative number (NO), the process directly proceeds to step 153 to execute the operation 3, but if the determination result of step 151 is a positive number (including 0) (YES), the step is performed. After performing the operation 2 in 152, the process proceeds to step 153. That is, in the processing example of FIG. 15, the subsequent processing procedure differs depending on the execution result in step 150. FIG. 16 shows a program example in which this processing is expressed by an assembler-like mnemonic.

In a normal system LSI, a conditional branch instruction is used in order to realize a process having a different processing procedure depending on the condition as shown in FIG. That is, as shown in FIG. 16, the arithmetic result is obtained by executing the arithmetic operation instruction inst.1 on the first line (corresponding to step 150 in FIG. 15). At this time, a normal system LSI simultaneously generates some codes representing the properties of the operation result. This is usually called a condition code. For example, a flag indicating that a carry or a borrow has occurred (carry), a flag indicating whether the result is positive or negative (negative), and the result can be expressed by the processor. Flags indicating that the data range has been exceeded (overflow), flags indicating whether the result is zero (zero), etc. are typical examples of the condition code flags.

In the second line of FIG. 16, a conditional branch instruction using a flag showing whether the operation result is positive or negative among these condition codes is written. If it is negative (ifN) label Branch to the line with L1 (determination in step 151 of FIG. 15; corresponding to NO). That is, if negative, the instruction in the third line is skipped without executing and the process branches to the fourth line (corresponding to step 153 in FIG. 15). If the result of the condition determination is positive (including 0), the conditional branch instruction on the second line is not executed and inst.3 on the third line is executed (see FIG. 15).
(Corresponding to step 152 of) and move to the fourth line. In this way, the processing shown in the flowchart of FIG. 15 can be executed.

What should be noted here is that a branch operation is always required when performing the processing shown in FIG. The role of the branch instruction is basically to forcibly change the execution order of the program, which is an operation that does not directly contribute to data processing. Moreover, in a system LSI performing pipeline control (advance control), which is a very general method for improving processing performance, if the flow of a program is disturbed by such a branch instruction, the processing efficiency is significantly reduced ( Overhead increases). Various techniques have been conventionally proposed in order to suppress such a decrease in processing efficiency as much as possible. One means is to reduce the overhead due to the execution of this conditional branch instruction. For example, there is known a method in which an instruction to be executed next in both cases is read in advance from a program memory and prepared so that the same processing can be performed regardless of whether the condition is satisfied or not satisfied. However, this method has a problem that the amount of hardware increases because the sequence control of the program becomes very complicated.

ADSP-2100 User's M is another means for suppressing the increase in hardware and improving the processing performance.
As disclosed in anual p4-4 to 4-15, add the same conditions as branch instructions to various instructions, execute only when the specified condition is satisfied, and if not, the specified action It is known that the process is moved to the next step without executing. FIG. 17 shows a program example in which the processing of FIG. 15 is expressed by an assembler-like mnemonic using this method.
Shown in That is, step 152 of FIG. 15 is executed only when the result of step 150 is positive.
As shown in the second line of 7 (if P inst.2), 1
Among the condition codes generated as the operation result of the line, the flag indicating whether the condition code is positive (including 0) or negative is positive (0
(Including), the branch instruction can be excluded from the program by providing an instruction to execute inst.2. The instruction on the second line satisfies the condition /
Regardless of the failure, the pipeline of program execution is not disturbed at all, so that the processing performance can be improved without increasing the number of complicated control circuits.

[0008]

However, although the above-mentioned conditional operation execution instruction method does not require complicated pipeline control hardware, various instruction codes must be provided with condition specifying fields. Therefore, some bits of the limited instruction code are used for that purpose, and there is a problem that the type of all supported instructions and the degree of freedom of operands are narrowed, and the performance as a processor deteriorates. . For example, a flag (carry) indicating that a carry or borrow has occurred as described above, a flag (negative) indicating whether the result is positive (including 0) or negative, and a range of data that the processor can represent When it is possible to specify the true / false condition of the four types of condition, that is, the flag indicating that it has exceeded (overflow) and the flag indicating whether the result is zero (zero), select from a total of eight conditions. Therefore, it is necessary to secure at least a 3-bit condition designation field 91 for each instruction code 90 as shown in FIG. A specific example of the 3-bit condition designation field 91 is 9
It is shown in 2. If this 3-bit condition specification field 91 is newly added to the conventional instruction code length in order to avoid the deterioration of the performance as a processor, another problem is that the memory capacity for storing the entire program will increase. There will be problems.

Generally speaking, program modules which should be operated under the above-mentioned conditions do not appear very often, but for example, in the case of digital signal processing, a certain processing routine is required. It is often executed repeatedly, and even if there is only one line in the processing routine, it is repeatedly executed many times, so that the effect of improving the processing performance of the conditional operation instruction becomes large. In addition, the conditions specified when the predetermined processing routine is repeatedly executed are the same. The present invention has been made in view of this situation, and an object of the present invention is to solve the problems as described above, to reduce the performance due to the limitation of the kind of the instruction and the degree of freedom of the operand, and to reduce the instruction code length. It is an object of the present invention to provide a data processing device that supports a conditional operation instruction that can improve processing efficiency without causing a problem such as an increase in program memory capacity accompanying the increase.

[0010]

In order to achieve the above object, the present invention supplies an arithmetic circuit (105 (ALU) in FIG. 1) for executing data processing and source data necessary for the data processing. Means (same register file 102)
And an operation result storage means (register,
In the data processing device including at least the file 102) and a control unit (control signal generation circuit 106) that executes a conditional operation instruction that executes an operation only when a specified condition is satisfied, the conditional operation Condition selecting means (for example, the first line in FIG. 4) for selecting at least one condition from a plurality of conditions to be used in the instruction, and condition information selected by the condition selecting means (for example, the first line in FIG. 4) Condition information holding means (condition, select,
A register 103 (CSR)) and a means (condition code register 104 (C) for holding information indicating the property of the operation result based on at least the selected condition.
CR)), and the conditional arithmetic instruction has a function of executing a required arithmetic processing only when one of the selected conditions is designated and the condition is satisfied. There is.

Further, holding means (condition code register 1) for holding information indicating the property of the operation result.
04 (CCR)) is information that constantly represents the property of the operation result (104 d in FIG. 2) other than the information that represents the property of the operation result (104 d (DC) in FIG. 2) based on the selected condition.
a (N), 104b (Z), 104c (V), etc.) are simultaneously held. Also,
The condition selecting means (for example, the first line in FIG. 4) is characterized by constantly selecting one from a plurality of pieces of information representing the property of the operation result.

Further, the conditional operation instruction (FIG. 5)
Is a field (51) that specifies the condition in the instruction code.
And a field (51) for designating the condition is provided only when the option (52 “0”) to be executed unconditionally and the condition held by the means for holding the selected condition information are true. It is characterized in that it has at least an option (“1” of 52) for executing a required arithmetic processing. Further, the conditional operation instruction (FIG. 10) has a field (81) for designating a condition in the instruction code, and the field (81) for designating the condition is an option to execute unconditionally (“00 of 82. )), And an option (“01” of 82) for executing required arithmetic processing when the condition held by the means for holding the selected condition information is “true”,
Option (82) to execute the required arithmetic processing in the case of "false"
"10") and at least. Further, a means for holding the selected condition information (103a (CS0), 103b (CS1), 10 in FIG. 14)
3c (CS2) is a means (104a (N), 104b in FIG. 14) for holding information indicating the property of the calculation result.
(Z), 104c (V) and the same register (1500
(CR)).

[0013]

In the structure of the present invention, the condition selecting means (for example, the first line in FIG. 4) stores the code (condition information) defining the condition to be selected in the condition information holding means (condition select register 103 (CSR)). The condition information is retained until the condition information is newly rewritten by another condition information or is initialized by a reset processing operation or the like. Further, the holding means (104d in FIG. 2) for holding the information indicating the property of the operation result for the conditional execution instruction is the condition information holding means (condition select) every time the instruction for updating the condition code is executed. The content is updated based on the information held in the register 103 (CSR).
On the other hand, each operation instruction has a bit for selecting whether to execute unconditionally or conditionally, as shown in FIG.
The processor has an option (52 in FIG. 5) to be executed conditionally, and when the operation instruction is executed conditionally, the processor holds the information indicating the nature of the operation result for the conditional execution instruction ( Condition code register 1
04 (CCR)) to determine whether the operation should be executed.

Alternatively, as shown in FIG. 10, in each operation instruction, an option to be executed unconditionally (“00” of 82) and a condition held by the means for holding the selected condition information are “ There is an option (“01” of 82) to execute the required arithmetic processing in the case of “true” and an option (“10” of 82) to execute the required arithmetic processing in the case of “false”.
When an arithmetic instruction is executed conditionally, the processor holds information (condition code register 104) that holds information indicating the nature of the arithmetic result for the conditional execution instruction.
(CCR)) is checked to determine whether or not the required arithmetic processing is to be executed. As a result, each operation instruction has a bit for selecting unconditional or conditional execution, or each operation instruction is unconditional or executed when the condition held in the condition information holding means is "true". Need only add a small number of bits to select whether to execute or to execute at the time of "false". It is not necessary to provide a long field for specifying all kinds of conditions for each operation instruction. It is possible to prevent the performance from deteriorating due to the limitation of the degree of freedom of and to reduce the capacity of the program memory.

[0015]

1 is a block diagram for explaining a first embodiment of the present invention. In the figure, 100 is a calculation execution circuit of an information processing apparatus to which the present invention is applied, 101 is a memory that stores data, 102 is a register file that stores source data and calculation results necessary for calculation, and 103 is conditional. A condition select that holds the condition code information selected for use in arithmetic instructions.
A register (CSR), 104 is a condition code register (CCR) that holds a condition code of an operation result and a condition code for a conditional execution instruction, and 105 is an arithmetic logic operation that executes various arithmetic operations and logical operations. A unit (ALU) 106 is a control signal generation circuit that generates a control signal necessary for executing an operation.

Further, 107 is a control signal sent from the control signal generation circuit 106 for controlling reading and writing of the memory 101, and 108 is a condition select register 103 (CS) sent from the control signal generation circuit 106.
R) control signal for controlling reading and writing, 109
Is a signal group for controlling the input / output of data to / from the data bus 121 or the arithmetic logic unit 105 for each register in the register file sent from the control signal generation circuit 106, and 110 is sent from the control signal generation circuit 106. A control signal group for selecting and executing an operation to be executed by the arithmetic logic operation unit 105, 111 is a data path connecting the memory 101 and the data bus 121, and 112 is a register file 102 and the data bus 121. Connected data path, 113 and 114 are register file 10
2 is the source data supplied to the arithmetic logic operator 105, 115 is the destination data to write the result of the arithmetic operation executed by the arithmetic logic operator 105 to the register file 102, and 116 is the arithmetic logic operator 105 It is a data signal group necessary for reflecting the condition code of the calculated operation result in the condition code register 104 (CCR).

Further, 117 is a data path connecting the condition select register 103 (CSR) and the data bus 121, and 118 is a selected condition code held in the condition select register 103 (CSR). A selection information signal 119 for transmitting information to the condition code register 104 (CCR) controls the information held in the condition code register 104 (CCR) for controlling the execution of conditional operation instructions and ordinary conditional branch instructions. Signal generation circuit 106
A signal for transmitting to the condition code register 104 (CCR) and a data path connecting the data bus 121 to the data bus 121, 121 to a data bus, and 122 to read and write to the condition code register 104 (CCR). Is a signal for controlling. Note that the above signal means a single signal or a plurality of signals, and the signal and the signal line may be referred to by the same symbol unless they are confused. Also, other element circuits naturally included in the original information processing apparatus, that is, addresses and address generation circuits to be supplied to the memory 101, instruction decoding circuits, flow control circuits, etc., are not directly related to the present invention, and are therefore omitted here. ing.

Next, a normal basic operation instruction execution procedure will be described. When the operation instruction is executed, first, the control signal generation circuit 106 outputs the source data necessary for the operation to the register files 102 to 113 and 114 through the control signal 109. Depending on the instruction included in the information processing device, it may be specified that the source data required for the operation be supplied from the memory, but since the present invention does not care where the output source of the source data is, In the description, the source data is the register file 102.
Assumed to be supplied from. Register file 10
Arithmetic logic unit 10 receiving source data from 2
5 executes the operation designated by the control signal 110 and outputs the operation result to the destination data 115.
, And input to the register file position (destination register) specified by the signal group 109. At this time, simultaneously, the condition code information of the operation result is sent to the condition code register 104 (CCR) through the data signal group 116.

FIG. 2 shows a detailed configuration example of the condition select register 103 (CSR), the condition code register 104 (CCR), and its peripheral portion. In FIG. 2, 103a (CS0) and 103b
(CS1) and 103c (CS2) are flag bits that form the condition select register 103 (CSR), and 200 is a condition that specifies a condition specified by a conditional operation instruction by decoding the information of each flag bit.
A circuit (decoder) that generates the selection information signal 118 to be sent to the code register 104 (CCR), 104a is a flag (N) that indicates whether the operation result is positive or negative, and 104b is a flag (Z that indicates whether the operation result is zero. ), 104c is a flag (V) indicating that the operation result exceeds the range of data that can be expressed by the processor, and 104d is a flag (DC) holding a condition code for a conditional execution instruction.

Further, 116a, 116b, 116c, 1
Reference numeral 16d is an individual data signal group necessary for reflecting the condition code of the operation result sent from the arithmetic logic operation circuit 105 in the condition code register 104 (CCR), 201 is the data signal group 116a,
116b, 116c, 116d and the condition
This is a condition generation / selection circuit that generates a state signal 202 to be input to the flag 104d by using the selection information signal 118 sent from the select register 103 (CSR). It should be noted that three types of flags are illustrated here as the normal condition code flags other than the flag 104d that holds the condition code for the conditional execution instruction. However, regarding the type and the number of this part,
It is clear that the number is not limited to a specific number and may be omitted altogether if unnecessary. It is also clear that the number of signals 116 for generating the status signal 202 may differ from the number of individually reflected condition code flags.

Next, FIG. 4 shows an example of a program in which the processing procedure of the flowchart of FIG. 15 described above is expressed by an assembler-like mnemonic according to the present invention. When executing a conditional operation instruction, the first line in Figure 4 (SET CSR [2: 0]
= 101), first, information that defines the condition to be selected is set in the condition select register 103 (CSR) (condition selecting means). here,
Condition select register 103 (CSR)
The second bit, the first bit, and the 0th bit of
The condition is 0, 1, that is, the result is a positive number (including 0). As an instruction for preselecting what kind of condition is reflected in the means for holding the condition code for the conditional execution instruction described above, a special data is set directly in each bit in the condition select register 103 (CSR). New instructions are provided. As a concrete operation, the selection information decoded from the new set instruction is condition selected,
Each bit 103a, 103 of the register 103 (CSR)
A method is conceivable in which encoding is performed corresponding to b and 103c, and the encoded data is output to the data bus to enable the control signal 108 and write.

However, the method of setting the information defining the condition to be selected in the condition select register 103 (CSR) is as described above, without adding a new set instruction in particular, to the register file 102 or the memory 101. It can also be realized by a method of sending the data stored in the memory by a data transfer command. Further, here, the flag bits constituting the condition select register 103 (CSR) are shown as 3 bits, but the number of bits may be any number as long as it can distinguish all kinds of conditions required by the information processing device for the conditional operation instruction. Absent. Here, as an example, the condition select register 103 (CSR) that selects one of eight kinds of conditions
FIG. 3 shows an example of definition of each bit constituting the. In this definition example, 000 when the result is not 0, 001 when the result is 0, 010 when the result overflows,
011 when the result does not overflow, 100 when the result is a negative number, 1 when the result is a positive number (including 0)
01, 110 when a carry is generated, and 111 when a carry is not generated.

Condition select register 10
3 (CSR) bits 103a (CS0) and 103b
The information written in (CS1) and 103c (CS2) continues to be held until it is newly rewritten by another information or initialized by a reset processing operation or the like. Condition select register 1
03 (CSR) bits 103a, 103b, 103
When the information defining the condition to be selected is set in c, the information on the condition selected by the decoder 200 is set.
The code information is stored in the condition code register 104.
(CCR) to select information signal 118. This conversion process is not always necessary, and is 103
The states held in a, 103b, and 103c may be directly output as the selection information signal 118. However, in that case, the condition code register 10
Status signal 2 to be stored in bit 104d in 4 (CCR)
The condition generation / selection circuit 201 performs all the processes for generating 02.
Will be done in.

Condition select register 10
3 (CSR) bits 103a, 103b, 103c
After the information defining the conditions to be selected is set, the bit 104d in the condition code register 104 (CCR) indicates that the condition code is updated each time an operation instruction is executed. The content is updated based on the information held in the select register 103 (CSR). That is, as shown in the second line of FIG. 4, when an arithmetic instruction (inst.1) whose condition code may be updated is executed by the arithmetic logic operation unit 105, the condition
The condition generation / selection circuit 201 in the code register 104 (CCR) uses the condition code information 116 of various operation results sent from the arithmetic logic operation circuit 105.
And the condition select register 103 (CS
Flag 104d according to the selection information signal 118 from R)
A state signal 202 to be input to

Since the processing procedure of FIG. 15 requires an operation instruction that determines whether the operation result is a positive number (including 0), the positive condition code "10" shown in FIG.
1 ”is held in each bit 103a, 103b, 103c, and the condition generation / selection circuit 201 outputs the inversion information of the signal 116a of the condition code information 116 of the operation result as the state signal 202. That is, when the negative signal 116a is "false", the status signal 202
Outputs a "true" state. The status signal 202 is directly input to the flag 104d. Condition code
Other flags 104a, 1 in register 104 (CCR)
04b and 104c have signals 116a and 116, respectively.
b and 116c are input. Subsequently, when the conditional operation instruction (if P inst.2) in the third line of FIG. 4 is executed, whether the operation result of the operation instruction in the second line is a positive number (including 0) as described above. Has already been held in the flag 104d, so if the flag 104d is in the "true" state, the specified operation is executed, and if it is in the "false" state, it is not executed and the next instruction in the fourth line (inst.3) is executed. Move on to.

FIG. 5 shows an example of conditional operation instructions according to the present invention. In the figure, 50 is an instruction code, 51 is a condition designation field, and 52 is a concrete code definition example of the condition designation field. Here, 1 bit is provided as a condition specifying field for specifying a condition in the instruction code, and whether the instruction is executed unconditionally (in the case of 0) or is executed conditionally depending on the value of the 1-bit condition specifying field. This is an example in which (in the case of 1) is designated. Executing conditionally means that the required arithmetic processing is executed only when the condition held in the means for holding the selected condition information (condition information holding means: condition select register 103 (CSR)) is true. It means to do.

FIG. 15 shows a flow in which the additional processing is executed only when the given condition is "true", and the additional processing is not executed when the given condition is "false". As shown in FIG. "false"
At the time of, there may be another process. FIG. 7 shows a program example in which the processing procedure of FIG. 6 is expressed by an assembler-like mnemonic. In FIG. 6, first, the arithmetic operation 1 is executed in step 60 (first line in FIG. 7), the operation result is determined in step 61, and if the operation result is a positive number (including 0) (that is, it is a negative number). If not) in step 62, operation 2a
Is executed (the third line in FIG. 7), and if the operation result is not a positive number (including 0) (that is, if it is a negative number), step 63
Then, the operation 2b different from step 62 is executed (5 in FIG. 7).
Line 6), after executing step 62 or step 63, operation 3 is executed in step 64 (6th line in FIG. 7). In the program example of FIG. 7, the branch instruction is always executed once regardless of whether the given condition is true or false.

The present invention can be applied to such an example. FIG. 8 is a program example in which the processing procedure of FIG. 6 according to the present invention is expressed by an assembler-like mnemonic.
Shown in According to the program example of FIG. 8, the second line (if
P inst.2a) and the third line (if N inst.2b) do not use branch instructions but use conditional operation instructions. It should be noted here that, when the conditional operation instruction (if P inst.2a) in the second line of FIG. 8 is executed with the condition being “true”, the condition code of the register 104 (CCR) depends on the operation result. Is not to update. This control is very easy. For example, when the conditional operation instruction is executed, the control signal 122 is disabled so that the condition code is not updated. There is no problem in performing such control in the same manner as in the processing shown in FIG. 15 described above. Therefore, the condition code is updated when executing the unconditional operation, and the condition is satisfied when executing the conditional operation. Regardless of failure,
If the code is not updated, the processing of both FIG. 15 and FIG. 6 can be realized by the same processor using the present invention.

FIG. 9 is another example of a conditional operation instruction, in which a plurality of conditions are set and a condition designation field 71 for designating the conditions is provided in the instruction. When a predetermined condition designated by the value of the condition designation field is "true", a required calculation corresponding to the condition is performed. As an example of the code definition of the condition designation field 71, for example, as shown at 72 in FIG. 9, an option to be executed unconditionally (“00” of 72) and a means for holding the selected condition information are held. Option 1 to execute the required arithmetic processing when the condition 1 is “true” (“0 of 72”).
1 ”) and an option (“ 10 ”of 72) for executing required arithmetic processing when the condition 2 held by the means for holding the selected condition information is“ true ”, and the selected The option (72) for executing the required arithmetic processing when the condition 3 held by the means for holding the condition information is “true”.
"11") and.

FIG. 10 shows another example of the conditional operation instruction. This conditional operation instruction has a condition specifying field 81 for specifying a condition in the instruction. An example of the code definition of the condition designation field 81 is shown in FIG.
As shown in 2, the unconditionally executed options (82 “0
0 ”) and the option (“ 01 ”of 82) for executing the required arithmetic processing when the condition 1 held by the means for holding the selected condition information is“ true ”. It has an option (“10” of 82) to execute the required arithmetic processing when the condition 1 is “false”.

Various other embodiments of the present invention are possible. For example, as shown in FIG. 11 as another embodiment of FIG. 2, the condition generation / selection circuit 201 of FIG.
00, and one of the signal groups 116 sent from the arithmetic logic operation circuit 105 may be selected by the selector 1100, output as the signal 202, and input to the flag 104d. In this case, an example of the code definition of the condition select register 103 (CSR) is shown in FIG.
As shown in FIG. 2, which of the signal groups 116 should be selected may be designated. In the definition example of FIG. 12, the value is 00 when the zero determination signal is selected, 01 when the overflow determination signal is selected, 10 when the positive / negative determination signal is selected, and 11 when the carry generation determination signal is selected. In the example of FIG. 11,
Condition select register 103 (CSR)
Is a 2-bit register, but the number of bits does not necessarily have to be 2 bits in this embodiment. For example, if it is desired to select from more conditions, the number of bits may be increased. That is clear.

Condition select register 10
3 (CSR) and condition code register 10
Various methods can be considered for the configuration method of 4 (CCR). 13 and 14 show an embodiment in which both are configured by a single register. 13, 1500 is the condition select register 103 (CSR) of FIG.
And condition code register 104 (CCR)
Is a control register CR that combines
01 is control register 1500 and data bus 1
21 is a data path connecting the control register 1500 and the control signal generating circuit 106. 1 and 2 for the rest
Is the same as In this embodiment, the specific operation is the same as that of the first embodiment described above except that the bit for condition select and the bit of the condition code are different in the same register.

In the above embodiments, the condition select register 103 (CSR), the condition code register 104 (CCR), and the control register 1500 (CR) are all assumed to be normal registers. Can obviously be a register mapped on a memory map, for example.

[0034]

As described above, according to the present invention, means for holding a condition code for a conditional execution instruction in addition to a normal condition code flag is provided, and the condition for the conditional execution instruction is provided. -By providing an instruction for preselecting what kind of condition is reflected in the means for holding the code and a means for holding the selection information, performance degradation due to the limitation of the instruction type and the degree of freedom of the operand, or the instruction code length It is possible to support a conditional operation instruction capable of improving processing efficiency without causing a problem such as an increase in program memory capacity due to the increase.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention.

FIG. 2 is a partial detailed block diagram of the first embodiment of the present invention.

FIG. 3 is a definition example of each bit of a condition select register.

FIG. 4 is an example of a program in which the processing content of FIG. 15 is expressed by an assembler-like mnemonic using the present invention.

FIG. 5 is an example of an instruction code having a 1-bit condition designation field.

FIG. 6 is a second flowchart including a conditional execution operation.

FIG. 7 is an example of a program in which the processing content of FIG. 6 is expressed by an assembler-like mnemonic.

FIG. 8 is an example of a program in which the processing contents of FIG. 6 are represented by an assembler-like mnemonic using the present invention.

FIG. 9 is an example of an instruction code having a 2-bit condition specification field.

FIG. 10 is a second instruction code example having a 2-bit condition designation field.

11 is another partial detailed block diagram of the embodiment of FIG. 1 of the present invention. FIG.

FIG. 12 is a second definition example of each bit of the condition select register.

FIG. 13 is a diagram showing a second embodiment of the present invention.

FIG. 14 is a partial detailed block diagram of a second embodiment of the present invention.

FIG. 15 is an exemplary flowchart including a conditional execution operation.

16 is an example of a program in which the processing content of FIG. 15 is expressed by an assembler-like mnemonic.

FIG. 17 is another program example in which the processing content of FIG. 15 is expressed by an assembler-like mnemonic.

FIG. 18 is an example of an instruction code having a 3-bit condition designation field.

[Explanation of symbols]

100: Operation execution circuit of information processing apparatus to which the present invention is applied 101: Memory for storing data 102: Register file for storing source data and operation result necessary for operation 103: For use in conditional operation instruction Condition select register (CSR) 104 that holds the selected condition code information: Condition code register (CCR) 105 that holds the condition code of the operation result and the condition code for the conditional execution instruction 105: Various Unit (ALU) 106 for executing various arithmetic and logical operations 106: Control signal generation circuit for generating control signals necessary for execution of arithmetic 107: Signal for controlling reading and writing of memory 101 108: Condition select register 103
Signals for controlling reading and writing of (CSR) 109: Signal group for controlling data input / output to / from the data bus 121 for each register in the register file or the arithmetic logic operation unit 105 110: In the arithmetic logic operation unit 105 Control signal group for selecting and executing operation to be executed 111: Data path connecting memory 101 and data bus 121 112: Register file 102 and data bus 121
A data path 113 and 114 connecting with and: Source data supplied from the register file 102 to the arithmetic logic unit 105. 115: A calculation result executed by the arithmetic logic unit 105 should be written to the register file 102. Destination data 116: Data signal group 117 required to reflect the condition code of the operation result executed by the arithmetic logic operator 105 in the condition code register 104 (CCR) 117: Condition select register 103
(CSR) and the data bus 121 are connected to each other. Data path 118: Condition select register 103
The selected condition code information held in (CSR) is stored in the condition code register 104.
(CCR) signal 119: Condition code register 10 for controlling execution of conditional arithmetic instructions and ordinary conditional branch instructions
4 (CCR) signal for transmitting the holding information to the control signal generation circuit 106: Condition code register 104 (C
CR) and the data path connecting the data bus 121: 121: data bus 122: condition code register 104 (C
(CR) read / write control signals 103a, 103b, 103c: flag bits constituting the condition select register 103 104a: flag (N) 104b indicating whether the operation result is positive or negative 104b: whether the operation result is zero Flag (Z) 104c: A flag (V) 104d indicating that the operation result exceeds the range of data that can be expressed by the processor 104d: A flag 116a, 116b, 116c, 116d holding a condition code for a conditional execution instruction : The condition code of the operation result sent from the arithmetic logic operation circuit 105 is stored in the condition code register 104.
Individual data signal necessary to reflect in (CCR) 200: Select information signal 118 for decoding the information of each flag bit and sending the condition designated by the conditional operation instruction to the condition code register 104 (CCR) Generating circuit 201: Data signal groups 116a, 116b, 116c,
116d and condition select register 1
03 (CSR) to generate a status signal 202 to be input to the flag 104d using the selection information signal 118 1500: Condition select bit, condition code of operation result and conditional Control register (CR) 1501 for holding condition code for execution instruction 1501: Data path connecting control register 1500 and data bus 121 1502: Signal for controlling read / write of control register 1500

Claims (6)

[Claims] 1. An arithmetic circuit for executing data processing, means for supplying source data necessary for the data processing, arithmetic result storage means for storing arithmetic results, and only when a specified condition is satisfied. In a data processing apparatus comprising at least a control means for executing a conditional operation instruction for executing an operation, a condition selecting means for selecting at least one condition from a plurality of conditions to be used for the conditional operation instruction, and the condition. The apparatus further comprises condition information holding means for holding the condition information selected by the selecting means, and means for holding at least information indicating the property of the operation result based on the selected condition, and the conditional operation instruction is the selection A data processing device having a function of executing a required arithmetic processing only when one of the specified conditions is specified and the condition is satisfied. 2. The holding means for holding the information representing the property of the operation result constantly holds the information representing the property of the operation result at the same time in addition to the information representing the property of the operation result based on the selected condition. The data processing device according to claim 1, further comprising: 3. The data processing apparatus according to claim 1, wherein the condition selecting means constantly selects one from a plurality of pieces of information representing the property of the operation result. 4. The conditional operation instruction has a field for specifying a condition in an instruction code, and the field for specifying the condition holds an option to be executed unconditionally and the selected condition information. 2. The data processing apparatus according to claim 1, wherein the data processing apparatus has at least an option to execute a required arithmetic processing only when the condition held in is true. 5. The conditional operation instruction has a field for specifying a condition in an instruction code, and the field for specifying the condition holds an option to be executed unconditionally and the selected condition information. The option to execute the required arithmetic processing when the condition held in is true,
The data processing device according to claim 1, wherein the data processing device has at least an option to execute a required arithmetic process in the case of "false". 6. The data processing according to claim 1, wherein the means for holding the selected condition information is composed of the same register as the means for holding the information indicating the property of the operation result. apparatus.