JPH0830459A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To mix fuzzy operation with normal microcomputer operation and to perform the fuzzy operation under normal microcomputer control by providing a fuzzy control part in a microcomputer access space. CONSTITUTION:On an internal data bus 10, a central control processor CPU 1, a random access memory RAM 2, a read-only memory ROM 3, a fuzzy control unit FCU4, and an analog-digital converter A/D8 and a digital-analog converter D/A9 which convert data for fuzzy inference are provided, and connected to the outside through an input/output port IO5. Further, fuzzy data for fuzzy inference are inputted to the unit FCU4 from an input port FI6 through the A/D8 and fuzzy data after the fuzzy inference are outputted to the outside from an output port F07 through the D/A9. Consequently, the semiconductor integrated circuit 100 can perform the normal microcomputer control operation and fuzzy control operation mixedly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a technique for adding a fuzzy reasoning function to a normal microcomputer.

[0002]

Fuzzy inference is a logic for fuzzy evaluation, and the logic is expressed by a fuzzy production rule of, for example, If-Then ... If
The part after ~ is called the conditional part, and the part after Then is called the conclusion part. The condition part and the conclusion part are described by a distribution function that generally indicates the certainty of an event, which is called a membership function. By fitting the data to which fuzzy reasoning is applied to the fuzzy production rule, the evaluation of the data is expressed as a distribution state indicating the likelihood of the event. Usually, the semiconductor integrated circuit having the fuzzy inference function is a semiconductor integrated circuit dedicated to fuzzy inference, or a fuzzy controller can be used for other logic control. It is limited to those which cannot perform the fuzzy control in parallel with the control of the normal microcomputer. These fuzzy inferences are described on page 36 of Introduction to Applied Fuzzy Systems (Ohm Co.).

[0003]

The semiconductor integrated circuit having the fuzzy reasoning function is expensive because a dedicated controller is used in the semiconductor integrated circuit because the dedicated controller is used for the fuzzy reasoning software. Therefore, a software development tool for fuzzy reasoning is needed. That is, the conventional semiconductor integrated circuit for fuzzy inference requires the development of fuzzy inference different from the development of normal microcomputer control, and does not have the function of performing fuzzy control under normal microcomputer control. Moreover, the fuzzy control by the conventional software cannot say that the fuzzy inference speed is sufficiently fast, and the use processing events of the software are limited.

An object of the present invention is to provide a semiconductor integrated circuit which can be developed using a conventional microcomputer software development tool and which performs fuzzy inference under normal microcomputer control.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, by providing a memory unit for storing a control program of a semiconductor integrated circuit including a fuzzy inference program module, a central control unit for instructing a fuzzy inference operation as needed and an external supply during the fuzzy inference operation are provided. The fuzzy input section that inputs the fuzzy input information that is the target of the fuzzy inference, the fuzzy control section that performs the fuzzy inference, the fuzzy output section that outputs the fuzzy inferred output information, and the input and output of external data A semiconductor integrated circuit is configured with a data input / output unit.
The fuzzy control unit stores first fuzzy inference rules composed of a conditional description and a conclusion description, and a second memory that stores fuzzy inference rules for performing fuzzy inference operations. Means, third storage means for storing fuzzy input information for performing fuzzy inference operation, and logical operation means for performing inference processing by the second storage means and the third storage means Consists of
As the second and third storage means, it is possible to use a surface register having a two-dimensional bit structure for collectively calculating the constituent bits. The first storage means can be composed of a random access memory that can be written and read by an instruction of the central control unit.

[0008]

According to the above means, the fuzzy control section is provided in the normal microcomputer access space, and the program module for controlling the fuzzy control section is incorporated in the microprogram, so that the fuzzy control operation is executed in the normal microcomputer control operation. be able to. That is, when the central control unit enters the program module for fuzzy inference, the fuzzy inference rule composed of the condition description and the conclusion description is externally or firstly applied in the fuzzy control unit.
Second storage means for performing a fuzzy inference operation from the storage means, and fuzzy input information for performing a fuzzy inference operation is stored in the third storage means, the second storage means and the third storage means. Inference operations are performed by the logical operation means using the information of the storage means. The second and third storage means may be plane registers having a two-dimensional bit structure, so that arithmetic processing can be executed collectively in all bit units constituting a plane without performing arithmetic operation in 1-bit units. By configuring the first storage means with a random access memory, the rule for fuzzy inference is stored in the first storage means from the outside and the data is transferred to the second storage means as necessary. And can be used for calculation. Further, the rules for fuzzy inference can be directly stored in the second storage means from the outside and the rules used for the calculation can be stored in the first storage means. That is, the first
Various fuzzy rules can be freely written in the storage means.

[0009]

FIG. 1 shows a semiconductor integrated circuit 100 having a fuzzy inference function according to an embodiment of the present invention. The semiconductor integrated circuit 100 shown in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique such as MOS or CMOS. Read-only memory ROM of the semiconductor integrated circuit 100
3 includes a program module for executing a fuzzy operation cycle as a program for instructing a normal microcomputer operation. Therefore, the semiconductor integrated circuit 100
Can perform a mixture of normal microcomputer control operation and fuzzy control operation. According to the figure, a central control processing unit CPU1, a random access memory RAM2, a read only memory ROM are arranged on an internal data bus 10.
3, a fuzzy control unit FCU4, an analog / digital converter A / D8 and a digital / analog converter D / A9 for converting fuzzy inference data are provided, and are connected to the outside via an input / output port IO5. Further, the fuzzy control unit FCU4 is inputted with fuzzy data for performing fuzzy inference from the input port FI6 through the A / D8, and the fuzzy data for which fuzzy inference is conducted is output through the output port FO7 through the D / A9. It is output to the outside.

FIG. 2 shows the fuzzy control unit FCU4.
An example block diagram is shown. According to the figure, the fuzzy control unit FCU4 includes a fuzzy memory unit 200 and an inference unit 3.
It consists of 00. The fuzzy memory unit 200 is a memory unit for storing a conditional description and a conclusion description expressed by a membership function that defines a fuzzy inference rule, an address decoder AD12 of the rule memory 11, and a rule. It is composed of the input / output buffer BM13 of the memory 11.

As the register mechanism of the inference unit 300, the control register CR16 for storing the condition description data and the conclusion description data, the fuzzy inference input data, and the output data created by the central processing unit CPU1 are stored in the control register CR16. A two-dimensional circuit SD17 for converting the input fuzzy inference input data, the conditional description and the conclusion description into two-dimensional data, input plane registers IR1 to IR4 for storing the two-dimensional fuzzy inference input data, and a rule The memory 11 and the knowledge plane register 14 in which the condition description and the conclusion description directly supplied from the outside are stored via the two-dimensionalization circuit SD17 are provided. Knowledge plane register 1 above
4 has an input / output buffer BR15.

Further, as the calculation mechanism of the inference unit 300,
Each input surface register IR1 to IR4 and knowledge surface register 14
AND operation part AND which performs AND operation with the condition description part
18 and a circuit MAX19 that forms a surface register from the maximum value of the data obtained by the AND operation section AND18, and the logical product and OR operation of the data of the circuit MAX19 and the conclusion description section of the knowledge surface register 14 corresponding to the data. AND / OR20 logical product / sum operation unit and AND / O AND / OR operation unit
There is provided a result register RR21 formed of a two-dimensional surface register for storing the result of R20 and a center of gravity calculation circuit GC22 for calculating the center of gravity of the result register RR21 from the bit arrangement. Here, the surface register is 4 × 256.
This is a register in which the two-dimensional configuration of bits is one unit, and operations between plane registers are performed in units, and operations by bits in the same configuration position are collectively performed in all bits that make up one unit.

The rule memory 11 is supplied with function data such as a membership function serving as a distribution function which expresses the degree of existence of each condition description and conclusion description from the outside and stored therein. This membership function is, for example, (x1)
(Y1) + (x2) (y2) + ... + (xn) (y
It is a function expressed as n). In the formula, x1 to xn indicate events, and y1 to yn indicate the degree of distribution of events.
It is a real number of 1, and the closer it is to 1, the higher the degree of distribution. That is, in the present embodiment, the address value of the rule memory 11 and the event of the membership function are in one-to-one correspondence, and the data actually stored in the rule memory 11 is the above distribution degree value. The one-dimensional data in the rule memory 11 is transferred to the plane register of the knowledge plane register 14 before the fuzzy inference operation is performed.

The fuzzy control unit FCU4 is not particularly limited, but in this embodiment, three types of rules 1 to 3 are supported. Therefore, in the rule memory 11, the condition parts A1 to A3 that store the condition descriptions of the rules 1 to 3, the conclusion parts B1 to B3 that store the conclusion descriptions of the rules 1 to 3, and the conclusion parts are arranged in parallel. An address decoder AD12 and an input / output buffer BM13 for addressing are provided. Rule 1 above is an operation to adjust the distribution of the input fuzzy data to the right when the events of the input fuzzy data are biased to the left. Rule 2 is that the event of the input fuzzy data is biased to the center of the distribution. If the events of the input fuzzy data are biased to the right on the distribution, the rule 3 is an operation to adjust the distribution of the events to the left when the distribution of the events is closer to the center. Means The distribution state of such events is expressed, for example, in such a manner that the value of the bit "1" formed in the surface register is formed into an isosceles triangle. The rule memory 11 is divided as a memory mat including the condition parts A1 to A3 and the conclusion parts B1 to B3,
For example, addresses from $ 0 to $ 255 are assigned to each of the condition parts A1 to A3, and each of the conclusion parts B1 to B3.
Are assigned addresses from $ 256 to $ 511. The rule memory 11 is composed of a random access memory that can be read / written from the outside via the data input / output port IO5.

FIG. 3 is a block diagram showing an example of the control register CR16. According to the figure, the control register CR
When the fuzzy inference rules 1 to 3 are formed by the central control processing unit CPU1, 16 stores three address values of the minimum, center and maximum of the above addresses corresponding to the event of the condition description of the rules 1 to 3. And an 8-bit register for storing the three address values of the minimum, center, and maximum of the above addresses corresponding to the events described in the conclusions of rules 1 to 3. The minimum, center, and maximum address values are elements for converting the rule description into two dimensions. Further, the control register CR16 has 8-bit register input values 1 to 4 for storing four fuzzy inference input data and 8-bit register output values 1 to 4 for storing corresponding output data. ing. Registers are added to the input values 1 to 4 in such a manner that a 3-bit correction value added by the CPU 1 and a 5-bit output destination address designating the input plane registers IR1 to 4 to be stored are added to the input values. Stored in. Here, the correction value means, for example, a percent error value before and after the input value. If the input value is interpreted as the center value stored in the register of the above rules 1 to 3, the correction value for the input value is given, so that the minimum and maximum values are determined for the corrected data. Therefore, the correction value is an element for making the input value two-dimensional like the setting values of the minimum, center, and maximum values of the above Rules 1 to 3.

The two-dimensionalization circuit SD17 has a function of converting data having a one-dimensional bit structure into data having a two-dimensional bit structure (plane register for one unit). For example, the central value stored in the control register CR16 is 4
By adding a logical value “1” for bits and adding a logical value “0” for 4 bits to the minimum and maximum values, 2
It is a dimension. The value between the center value and the minimum and maximum values is determined by the number of bits of the logical value "1" added to the center value. Here, since the number of bits of the logical value "1" added to the central value is 4, the logical value "1" is set in the order of three, two, and one in the left and right direction from the central value. To be done. That is, one-dimensional data is a two-dimensional isosceles three-dimensional shape consisting of 4 bits in height, which indicates a distribution degree value, and 9 bits in the bottom side, which indicates an event, among 4 × 256 bits which constitute one unit of surface register. Converted to rectangular data. The one-dimensional data of the input values 1 to 4 are also two-dimensionalized using the correction values in the same manner as above. In this case, the input value corresponds to the center, the negative correction value corresponds to the minimum value, and the positive correction value corresponds to the maximum value.

The knowledge plane register 14 has the rules 1 to 3 above.
Each condition description and each conclusion description are composed of 4 × 256 bits of 1-unit surface register, and in total are composed of 6-unit surface register. Further, each of the input surface registers IR1 to IR4 is composed of one unit of the surface register. FIG. 4 shows an example of the surface register. In the figure, the event address $
In the case of 0 to $ 255, it indicates the surface register and the input surface registers IR1 to IR4 in which the condition description is stored, and the address $ 25.
In the case of 6 to $ 511, the surface register in which the conclusion description is stored is shown.

The AND operation unit AND18 performs a logical product of the input surface registers IR1 to IR4 to which the input values are input and the surface registers to which the conditional descriptions of rules 1 to 3 of the knowledge surface register 14 are input. . This logical product is not performed in bit units, but is performed in plane units having the same addresses $ 0 to $ 255. Specifically, the input surface register IR
The logical product is performed by superimposing the 1 × 4 × 256-bit surface register with the knowledge surface register 14 conditional description of rule 1 4 × 256-bit surface register. That is, it becomes "1" only when the bits forming the same position in both surface registers become "1", and otherwise "1".
0 "is performed. This logical product operation is
In parallel with the operation of the input surface register IR1 and the surface register of the condition description of rule 1, the input surface register IR1 and the surface register of the condition description of rule 2 and the input surface register IR
The calculation of the area register of the condition description of 1 and rule 3 is performed. Further, at the same time, the operations of the other input surface registers IR2 to IR4 and the surface register of the condition description of the rules 1 to 3 are also performed in parallel.

The circuit MAX19 is a logical product operation unit AN.
It is a storage area for storing the maximum value of the distribution degree of the calculation result of D18, and is composed of a 4-unit plane register in which the calculation results of the input values 1 to 4 are stored. In this surface register, the maximum value MAX of the "distribution degree" of the above calculation result is obtained, and a surface register value having the distribution degree MAX for all events is formed. In addition, in the above calculation, the event from $ 0 to $ 255
Addresses up to the address were assigned, but here the address of the event is converted from the $ 256 address to the $ 511 address. This is because the next calculation is performed with the surface register in which the value of the conclusion description is stored, so that the calculation can be performed between the surface registers by matching the addresses.

AND / OR 20 for the logical product / sum operation unit
Performs a logical product operation of the surface register formed by the circuit MAX19 and the surface register of each conclusion description of rules 1 to 3 of the knowledge surface register, and three surface registers obtained by the logical product operation (each rule 1 Logical AND operation of 3 to 3) is performed in parallel for each input data for fuzzy inference. The result register RR21 is composed of a 4-unit plane register for storing the data obtained by the logical product / sum operation unit AND / OR20 corresponding to each fuzzy inference input data.

The center of gravity calculating circuit GC22 is a circuit for calculating the center of gravity of the distribution of bit "1" from the constituent bits of the surface register supplied by the value of the result register RR21. Here, the center of gravity is the bits that make up the surface register.
1 "is a value of an address having a high degree of existence. This center-of-gravity calculation is also performed in parallel for four unit plane registers supplied from the result register. The thus obtained center-of-gravity value address is the control register CR16. Output value 1
Stored in ~ 4. The stored value is read out as required by central control processing unit CPU1 and converted from an address value to a predetermined event value.

FIG. 5 shows an example of the calculation process of the plane register when fuzzy inference is performed in the above embodiment. The shaded triangle A shown in the figure is an example of the distribution state of the input values appearing on the input surface registers IR1 to IR4, and the open triangles B1 to B3 are the knowledge surface register rules 1 to 3. Is an example showing the distribution state of the conditional description, the white triangles C1 to C3 are examples showing the distribution state of the conclusion description of rules 1 to 3, and the shaded figure D shows the distribution state of the input data. It is an example showing the distribution state converted through the condition description and the conclusion description. Here, the surface register in which the condition description is stored is provided with addresses $ 0 to $ 255 at which events are fixedly set as the horizontal axis,
In the plane register that stores the conclusion description, events are fixedly set on the horizontal axis from addresses $ 256 to $ 511.
A street address is provided.

When the central control processing unit CPU1 enters a fuzzy inference operation cycle, fuzzy inference rules 1 to 3 are stored in the fuzzy control section 4. The method of storing the fuzzy inference rules 1 to 3 includes (1) fuzzy inference rules 1 to
3 is stored in the rule memory 11 from the outside,
(2) There is a method in which the central control processing unit CPU1 creates the fuzzy inference rules 1 to 3 and writes it in the control register, and (3) a method in which the fuzzy inference rules 1 to 3 are externally directly written in the knowledge plane register. Hereinafter, a case where fuzzy inference is performed by the method (1) will be described.
When the central control processing unit CPU1 enters a fuzzy inference operation cycle, fuzzy inference rules 1 to 3 are stored in the rule memory 11 from the outside. Fuzzy input data, which is analog data, is transferred from the input port FI6 through the analog / digital converter A / D8 to the control register CR16.
Are stored in the input values 1 to 4. At that time, the central control processing unit CPU1 adds the correction value and the address of the input surface register which is the calculation destination to each input value. Input value 1 to 4
Are two-dimensionalized by the two-dimensionalization circuit SD17 and stored in designated input plane registers IR1 to IR4. The distribution state of the input values is an isosceles triangle represented by A in FIG. Further, the rules 1 to 3 written in the rule memory 11 are
It is directly transferred to the knowledge surface register 14 and constitutes a surface register composed of the condition description of rules 1 to 3 and the conclusion description value. The distribution state of the conditional description values is an isosceles triangle represented by B1 to B3 in FIG. 5, and the distribution state of the conclusion description values is C in FIG.
It is an isosceles triangle represented by 1 to C3.

When a predetermined value is input to the input plane registers IR1 to IR4 and the knowledge plane register 14, for example, all three bits of the input plane register IR1 are added to the three-unit plane register for logical product calculation of the logical product calculation circuit AND18. Knowledge side register 1
All the bits of the surface register of the condition description of the rules 1 to 4 of 4 are read and the logical product operation is performed. Input side registers 2-4
With respect to the above, the same processing as described above is performed in parallel with the above arithmetic processing. The content of the arithmetic logic in the logical product arithmetic circuit AND18 is conceptually shown in the logical product with the conditional description of FIG. 5, and the portion where the figures A and B overlap is a bit "
The distribution range of 1 "is represented in this way. Thus, the maximum value of the distribution degree of the overlapping portion α1 (the value obtained by the operation with the conditional description of rule 1), α2 (the value obtained by the operation with the conditional description of rule 2) ), 0 (value obtained by calculation with the conditional description of rule 3).
Based on 0, the circuit MAX19 sets the horizontal axis data to the address $ 0.
Address- $ 255 to Address $ 256- $ 51
It is converted into the first address, and the vertical axis forms a three-unit surface register whose distribution degree is α1, α2, 0 regardless of the address value.

In the logical product / sum operation unit AND / OR20,
First, the logical product of the 3 unit plane register formed by the circuit MAX19 and the plane register of the conclusion description of the rules 1 to 3 of the knowledge plane register is taken. The result is the distribution area represented by the figure D in FIG. Then, the logical sum of the obtained distribution areas of the figure D is taken and stored in the result register RR21. The value of the result register RR21 is the center of gravity calculation circuit GC2.
In step 2, an address having a high degree of distribution of the bit "1" in the plane register is calculated and stored as output data in the output values 1 to 4 of the control register CR16. This output value 1
4 are read by the CPU 1 as required. The logical product / sum operation unit AND / OR20 is also operated in parallel for each fuzzy inference input data.

According to the embodiment described above, there are the following operational effects. (1) Fuzzy control unit F in normal microcomputer access space
By providing the CU4 and incorporating the program module for controlling the fuzzy control unit FCU4 in the ROM3, the fuzzy inference operation can be executed by using the conventional non-fuzzy inference dedicated microcomputer. (2) In the inference operation of the fuzzy control unit FCU4, by storing the data in the surface register and performing the operation, it is possible to perform the operation processing of all bits constituting the surface register by one cycle operation of the central control processing unit CPU1. Therefore, the bit-by-bit arithmetic processing becomes unnecessary, and the arithmetic processing of fuzzy inference can be speeded up. (3) By configuring the rule memory 11 with a random access memory, the rules 1 to 3 for fuzzy inference are:
It can be stored directly in the rule memory from the outside. In addition, rules 1 to 3 for fuzzy inference, which are directly stored from the outside in the knowledge plane register 14 and used in the calculation, are stored in the rule memory 1.
Can be stored in 1. Further, the rules 1 to 3 for fuzzy reasoning created by the central control processing unit CPU1 and written in the control memory CR16 are directly in the knowledge plane register 1
4 and stored in the rule memory 11 after being used for calculation. That is, since it is not necessary to hold a specific fuzzy inference rule in the semiconductor integrated circuit 100, versatility can be provided in the fuzzy inference rule to be used.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto and can be variously modified without departing from the gist thereof. For example, in the above-described embodiment, the one having a logical operation unit applied to fuzzy inference such as the barycentric method has been described, but the logical operation unit may be configured to apply other fuzzy inference methods.

In the above description, the invention made by the present inventor was mainly applied to a dedicated LSI for performing a fuzzy inference function, which is the field of application of the invention, but the present invention is not limited thereto. However, it can be configured as a peripheral circuit having a built-in DMAC, and can be widely applied to various other semiconductor integrated circuits. INDUSTRIAL APPLICABILITY The present invention can be applied to an effective condition by incorporating at least a fuzzy reasoning function.

[0029]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, by providing a fuzzy control unit in the microcomputer access space and incorporating a program module that controls fuzzy operations in the microprogram, it is possible to mix fuzzy operations with normal microcomputer operations, and fuzzy control can be performed with normal microcomputer control. The action can be performed. In addition, by using the plane register for fuzzy inference and performing all the arithmetic operations of all the bits composing the plane register in one cycle operation of the CPU, the fuzzy inference arithmetic processing is faster than in the case of bit-wise arithmetic processing. Can be converted.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a semiconductor integrated circuit of the present invention.

FIG. 2 is a block diagram of an example of a fuzzy control device.

FIG. 3 is a block diagram of an example of a control register.

FIG. 4 is an exemplary configuration diagram of a plane register.

FIG. 5 is a diagram showing a calculation process of a surface register in the inference unit.

[Explanation of symbols]

 1 Central control processing unit 3 Read only memory 4 Fuzzy control unit 6 Input port 7 Output port

Claims (3)

[Claims] 1. A semiconductor integrated circuit having a fuzzy inference function, a memory unit for storing an operation program of the semiconductor integrated circuit including a fuzzy inference operation program module, a central control unit for instructing the fuzzy inference operation, and an external device. A fuzzy input section for inputting fuzzy input information for fuzzy inference supplied from the first storage means, a first storage means for storing rules of fuzzy inference composed of conditional description and conclusion description, and for performing fuzzy inference operation Second storage means for storing the fuzzy inference rules of the above, third storage means for storing fuzzy input information for performing the fuzzy inference operation, the second storage means and the third storage A fuzzy control unit having a logical operation means for performing fuzzy inference using information of means, and outputting fuzzy inferred output information The semiconductor integrated circuit of the Ajii output unit, and a data output unit for inputting and outputting data, characterized in that it comprises a. 2. The semiconductor integrated circuit according to claim 1, wherein the second storage means and the third storage means are surface registers each having a two-dimensional bit arrangement. 3. The semiconductor integrated circuit according to claim 2, wherein the first storage means comprises a random access memory.