JPH08300711A - Method for inputting multi-gradation data into line head - Google Patents

Abstract

PURPOSE: To decrease the number of signal lines from a print control part to a line head base sheet. CONSTITUTION: Bleat generating resistance bodies R1-R1280 on a thermal head base sheet 11 are divided into the first blocks by 64 each and each heat generating resistance body of this each first block is respectively connected with head driving circuits 121-1220. Then, the second block is respectively formed by each heat generating resistance body connected with adjoining two head driving circuits. Each common data line M1-M10 is connected with the head driving circuit of each second block from a print control circuit provided outside of the base sheet and a common data inputting clock line DCL 1 is connected with one of the head driving circuit of each second block and a common data inputting clock line DCL 2 is connected with another head driving circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of inputting multi-gradation data to a line head such as a line thermal head or a line ink jet head.

[0002]

2. Description of the Related Art For example, a line thermal head is shown in FIG.
As shown in FIG. 1, 1280 heating resistors R1 to R1280 are arranged side by side on the thermal head substrate 1 and 64 blocks are connected as one block to the 64-dot head drive circuits 21 to 220, respectively. Each dot head drive circuit 2
As shown in FIG. 5, 1 to 220 are provided with a 64-bit shift register 3 and serial dot print data DA from the serial data input terminal SI is provided in the shift register 3 in synchronization with the clock CLK from the clock input terminal CLK. You are typing. That is, the timing of the clock CLK and the dot print data DA is as shown in FIG.

When 64-bit dot print data is set in the shift register 3, the dot print data in the shift register 3 is latched in the latch circuit 4 by the latch signal from the latch signal input terminal LAT / LAT, and further. It is supplied to the switching circuit 6 via the AND circuit 5. In this way, each heating resistor in one block is selectively energized and controlled. By the way, in the case of a binary line thermal head which does not express gradation, ten serial data input terminals S of the dot head drive circuits 21 to 210 among the dot head drive circuits 21 to 220 are selected.
I and the serial data output terminal S0 are serially connected, and the ten serial data input terminals SI and the serial data output terminal S0 of the dot head drive circuits 211 to 220 are serially connected.

From the print control circuit 7 to the data line K
64 for dot head drive circuits 21 to 210 by 1
Serial dot print data of 0 dots is supplied, and serial dot print data of 640 dots is supplied to the dot head drive circuits 211 to 220 by the data line K2. Further, the print control circuit 7 supplies a clock CLK to each of the dot head drive circuits 21 to 220 via a data input clock line DCL. As described above, in the binary line thermal head, the heating resistors R1 to R1280 are divided into R1 to R640 and R641 to R1280.
In order to divide into two blocks, the number of data input lines from the print control circuit 7 to the thermal head substrate 1 is line K1,
It will be K2. Further, the number of data input clock lines is one.

On the other hand, in the case of a line thermal head which performs multi-gradation expression, such a structure is not provided. For example, assuming that the maximum number of expression gradations is 64, as shown in Table 1, each expression gradation value is expanded into 63-bit “1” and “0” data. Then, for all dots, the data is transferred from the first gradation data to the dot head drive circuits 21 to 220.

[0006]

[Table 1]

Each heating resistor R1 to R1280 has data "1".
When the data is "0", power is supplied and printing is performed. When the data is "0", power is not supplied and printing is not performed. In the case of the binary value mentioned above, this data transfer is performed only once.
In the case of gradation, this data transfer is repeated 63 times. As for the data transfer time (input time) for printing one line, for example, if 6 MHz is used for the data input clock and the number of data input lines is two, as shown in FIG. 640 dots x 167ns = 1
Although it becomes 07 μs, it takes 640 dots × 167 ns × 63 times = 6.8 ms for 64-gradation expression.

When performing multi-gradation expression, it is necessary to shorten the minimum printing time per gradation in order to accurately correct the γ characteristic of the print density.
It is necessary to shorten the line printing time. It is impossible to meet such a demand with the configuration of FIG. Therefore, conventionally, when performing multi-gradation expression, as shown in FIG. 7, the print control circuit 7 drives the dot head drive circuits 21 ...
220 individual data lines L1, L2, ... L10, L11,
... L20 is connected and one data line supplies serial dot print data for 64 dots. In this way, the data transfer time is 64 dots per gradation × 167 ns = 10.7 μs, and the total 64 gradations is 10.7 μs × 63 times = 672 μs, which shortens the minimum printing time per gradation. In addition, it is possible to shorten the printing time for one line.

[0009]

However, in such a conventional configuration, there is a problem that the number of data input lines from the print control circuit 7 to the thermal head substrate 1 is as large as 20, and the thermal head substrate 1 has a problem. Thus, there is a problem that as many as 20 connectors must be arranged on a board having a small area. Therefore, the present invention can reduce the number of signal lines from the print controller to the line head substrate, and can sufficiently realize the reduction of the minimum printing time per gradation and the reduction of the one-line printing time. A method for inputting multi-gradation data of a line head is provided.

[0010]

SUMMARY OF THE INVENTION The present invention is directed to multi-tone dot printing in which each dot printing element is driven by a print control unit provided outside the board with respect to a line head substrate in which a large number of dot printing elements are arranged. When inputting data, each dot printing element is divided into a plurality of first blocks, and a plurality of second blocks are formed by combining a plurality of these first blocks. For each first block in each second block, The serial dot print data for each gradation is selectively input in synchronization with clocks having different phases to set data for driving each dot print element in each first block. As a result, the number of data input lines becomes the number of second blocks, and the number of data input clock lines becomes the second number.
This is the number of the first blocks in the block, and the number of signal lines is reduced as a whole.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, the present invention is applied to a line thermal head. As shown in Figure 1,
1280 heating resistors R1 to R, which are dot printing elements
1280 are arranged side by side on the thermal head substrate 11, and the first blocks R1 to R64 and R65 to R12 are arranged in 64 blocks each.
8, R129 to R192, R193 to R256, ... R1153 to R12
16 and R1217 to R1280, and each heating resistor of each first block is divided into a 64-dot head drive circuit 121.
It connects to ~ 1220. Each head drive circuit 121
The configuration of 1220 is similar to that of FIG.

A second block is formed by the heating resistors R1 to R64 connected to the head drive circuit 121 and the heating resistors R65 to R128 connected to the head drive circuit 122, and connected to the head drive circuit 123. Each heating resistor R12
9 to R192 and the heating resistors R193 to R256 connected to the head drive circuit 124 form a second block, and similarly, the heating resistors connected to the two head drive circuits form a second block. ing. That is, ten second blocks are formed as a whole.

A print control circuit 13 is provided outside the thermal head substrate 11. The print control circuit 13 connects a common data line M1 to the serial data input terminals SI of the head drive circuits 121 and 122. A common data line M2 is connected to the serial data input terminals SI of the head drive circuits 123 and 124, and a common data line M10 is connected to the serial data input terminals SI of the head drive circuits 1219 and 1220. . Also,
From the print control circuit 13 to the head drive circuits 121
, 123, ... 1219 clock input terminals CLK are connected to a common data input clock line DCL1, and the head drive circuits 122, 124, ... 1220 clock input terminals CLK are connected to a common data input clock line DCL2. ing.

As shown in FIG. 2, the print control circuit 13 includes a data generating circuit 141 for generating serial dot print data N1 for each gradation driving the heating resistors R1 to R64 and a heating resistor R65 to. A data generation circuit 142 for generating serial dot print data N2 for each gradation driving R128 is set as one set, and similarly, a serial for each gradation driving the heating resistor of the adjacent first block is performed. A set of data creating circuits for creating dot print data is made into 10 sets, and 10 sets of data creating circuits 141, 142, ... 141.
There are 9,1420. That is, as shown in Table 1, the data generation circuit 141 has the dot number. Data of the first to 63rd gradations of 1 to 64 are sequentially created, and the data creation circuit 142 dot No. 65-128 first
Data from the gray scale to the 63rd gray scale are sequentially created. Similarly, other data creation circuits-1419,1
420 also corresponds to the dot number. The first to 63rd gradation data are sequentially created.

The dot print data N1 created by the data creating circuit 141 and the data creating circuit 142
Dot printing data N2 created by the data selector 15
The data is selected by 1 and output to the data line M1, and then similarly selected by the data selector and output to the data lines M2 to M19. The final set is the data generation circuit 1419.
Dot print data N19 and data creation circuit 14 created by
Dot print data N20 created by 20 is selected by the data selector 1
The data is selected at 510 and output to the data line M10. The data selectors 151 to 1510 are switched by a data switching signal CH.

A clock CLK1 output from the print control circuit 13 to the data input clock line DCL1 and a clock CL output to the data input clock line DCL2
As shown in FIG. 3, the phases of K2 and K2 are 180 degrees out of phase with each other, and each has a period of 167 ns (6 MHz).

In the embodiment having such a structure, when attention is paid to, for example, the heating resistors R1 to R128, the data forming circuit 141 in the print control circuit 13 has the heating resistors R1 to R128.
16 serial dot print data N1 for driving R64
The data creating circuit 142 creates serial dot print data N2 for driving the heating resistors R65 to R128 at a cycle of 167 ns. The dot print data N1 and N2 are selected by the data selector 151. The data selector 151 selects the dot print data N1 and N2 by the data switching signal CH and outputs it to the data line M1.

When the dot print data N1 is selected and output to the data line M1, the dot print data N1 is taken into the head drive circuit 121 at the rising edge of the clock CLK1. When the dot print data N2 is selected and output to the data line M1, the clock CLK2
The dot print data N2 at the rising edge of the head drive circuit 1
Taken in 22. In this way, the dot print data N1 and N2 on the data line M1 are clocked by the clocks CLK1 and CL.
It is transferred in 83 ns (12 MHz), which is a half cycle of K2.

When this data transfer is performed for 64 cycles, the transfer of the first gradation data to the heating resistors R1 to R128 is completed. In the case of 64-gradation expression, this data transfer is repeated up to 63 gradations except the 0th gradation. The data transfer time per gradation at this time is 167 ns × 64 dots = 10.7 μs, which is 6
Since it is repeated three times, the total data transfer time for one line is 10.7 μs × 63 times = 672 μs.
Such control is simultaneously performed on the remaining heating resistors R129 to R1280 to perform one-line printing. In this way, the minimum printing time per gradation and the printing time per line can be shortened.

The number of signal lines connecting the print control circuit 13 and the thermal head substrate 11 is M for data lines.
1 to M10, data input clock line is DCL
There are 12 in total, that is, 1 and DCL2, which can be approximately half of the conventional configuration shown in FIG. Therefore, the connector can be arranged on the thermal head substrate 11 having a small area without any problem. In other words, the thermal head substrate 11 can be made smaller and the size can be reduced.

In the above embodiment, 1280 heating resistors are divided into blocks of 64 blocks each to form a first block, and a combination of two blocks is used as a second block to generate a clock for data input. Although two types are used, the present invention is not limited to this. For example, four types of clocks for data input may be used by combining four blocks of the first block as the second block. The second block may be formed by combining a plurality of combinations. Also, the first block is not limited to the combination of 64 heating resistors. When the first block is combined with four blocks to form the second block, the number of signal lines is five, that is, five data lines and four data input clock lines, which is nine in total, and the number of signal lines is further reduced. be able to.

Further, although the above-described embodiments have been described in which the present invention is applied to a line thermal head, the present invention is not necessarily limited to this, and can be applied to an inkjet type line head having an inkjet nozzle as a dot printing element. .

[0023]

As described above, according to the present invention, each dot printing element is divided into a plurality of first blocks, and a plurality of the first blocks are combined to form a plurality of second blocks. Since serial dot print data is selectively input to each first block in synchronization with clocks having different phases, it is possible to reduce the number of signal lines from the print control unit to the line head substrate. The minimum printing time per gradation and the printing time per line can be sufficiently realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a main configuration of a print control circuit of the embodiment.

FIG. 3 is a timing chart for explaining an operation of a main part of the print control circuit of the embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional binary line thermal head.

5 is a circuit diagram showing a configuration of a 64-dot head drive circuit in FIG.

FIG. 6 is a diagram showing a timing of a clock and dot print data in the conventional example.

FIG. 7 is a block diagram showing a configuration of a conventional multi-gradation line thermal head.

[Explanation of symbols]

 11 ... Thermal head substrate 121 to 1220 ... 64-dot head drive circuit 13 ... Print control circuit

Claims (1)

[Claims] 1. When inputting multi-tone dot print data for driving each dot print element from a print control unit provided outside the board to a line head substrate in which a large number of dot print elements are arranged, each dot is printed. The printing element is divided into a plurality of first blocks, a plurality of second blocks are formed by combining a plurality of the first blocks, and a plurality of second blocks are formed. A data input method for a line head, characterized in that dot print data is selectively input in synchronization with clocks having different phases to set data for driving each dot print element in each first block.