JPH08298493A - Frame synchronization method and frame synchronizer device - Google Patents

Abstract

PURPOSE: To make the time constant till established of synchronization is by providing a correlation means and a mode changeover means and deciding the establishment of frame synchronization based on the comparison result between 2nd correlation and a 2nd threshold level. CONSTITUTION: A correlation device 13 calculates the correlation between an allocated synchronization series ϕ and a sample value series of a reception signal in a calculation section with respect to sections of respective widths of search windows. When the calculation is finished, a mode changeover device 14 stops the operation of the correlation device 13 and decides whether or not the correlation value exceeds a 2nd threshold level every time the correlation device 13 reports the correlation value and grasps the detection interval of the correlation value in excess of the 2nd threshold level. When a received signal is sent for a frame period, the correlation value over the 1st threshold level is detected for plural number of times. The frame period is recognized from the detection interval of the correlation value in excess of the 2nd threshold level and a transmission rate is found out. For example, when the interval is consecutive, the mean value of the intervals is decided to be a frame period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to TDMA (Time
Division Multiple Access) The present invention relates to a frame synchronization device and a frame synchronization method in a cellular telephone system. It also relates to a correlator therefor.

[0002]

2. Description of the Related Art As the number of subscribers to mobile phone services has increased, more efficient use of frequencies has become a challenge.
One of the technologies for this (effective use) is TDMA (Time
Division Multiple Access). In the TDMA communication system, one frame is divided into a plurality of time slots. The subscriber receives and transmits a radio signal using the time slot assigned by the base station. In this way, one channel is shared by multiple subscribers. At the beginning of each time slot, for slot identification,
A known pattern called a synchronization sequence is arranged.
This synchronization sequence is set to have good autocorrelation characteristics and cross-correlation characteristics. That is, a large correlation value is obtained between the same or similar synchronous sequences,
On the other hand, the correlation value is small between different synchronization sequences. Each terminal detects the exact position of the slot within the frame by calculating the correlation between the synchronization sequence of the time slot assigned by the base station and the sample value sequence of the received signal.

However, in an actual system, the detection accuracy may decrease due to frequency Doppler shift and multipath fading. Further, even when a frequency offset occurs, the accuracy of synchronization detection may decrease. To compensate for frequency offset, use USP-
The method described in 5121414 is used.

In order to improve the accuracy of synchronization detection, it is desirable to detect the time slot a plurality of times. As an actual procedure, first, the correlation between the synchronization sequence of the allocation slot and the sample value sequence of the received signal is continuously calculated, and the position estimated to be the position of the allocation slot in the frame is detected. Next, the correlation is calculated with respect to the received signals before and after that, centering on the time one frame time after that timing. Based on the detection result of this correlation, the timing detected earlier is corrected and the start position of the frame is determined.

[0005]

By the way, as a voice coding method applied to a TDMA cellular telephone system,
In addition to the full rate so far, the half rate has come to be adopted. That is, in the future, a plurality of transmission rates will be mixed in the TDMA service. In Figure 2,
Examples of full-rate and half-rate frame configurations are shown.
2A shows a full-rate frame structure, and FIG. 2B shows a half-rate frame structure. As shown in these figures, one frame is divided into three time slots at full rate, and one frame is divided into six time slots at half rate. T
In the DMA system, the transmission rate per channel is defined by the transmission bit rate and the number of slots per frame allocated to one channel. In a system in which a plurality of transmission rates are mixed, FIG.
As shown in (b) and (b), it is convenient to change the frame period only by increasing or decreasing the number of slots allocated to one channel without changing the transmission bit rate and the time slot configuration.

However, the conventional frame synchronization method presupposes that the transmission rate, that is, the frame period, is a known single value. Therefore, when there are a plurality of transmission rates and the current transmission rate is known after the line is connected and the signal is actually received, frame synchronization may be erroneously established.

Further, in the example shown in FIGS. 2A and 2B, the frame period of the transmission rate B is twice the frame period of the transmission rate A. TD standardized in North America
In the case of MA cellular telephone system, the full-rate frame period T1 is 20 msec and the half-rate frame period T2 is
40 msec. In such a case, the correlation value between the synchronization sequence corresponding to the time slot assigned to the mobile station and the sample value sequence of the received signal is calculated. For example, if the synchronization sequence of the assigned time slot is SYNC1, the result of this calculation is SYNC of frame 1 in FIG. 2 (a).
At a position of 1, the specified threshold is exceeded. Using this position as a reference, the correlation is calculated twice more at the frame cycle interval of the transmission rate A using only this SYNC1. If the result of this calculation is that the correlation value exceeds the threshold value both times, it can be determined that SYNC1 of frame 2 and frame 3 in FIG. 2A has been detected. Therefore, it is determined that synchronization has been achieved at the transmission rate A. If only the second correlation value exceeds the threshold as a result of the calculation, it can be determined that SYNC1 of frame 2 in FIG. 2B is detected. Therefore, it is determined that synchronization has been achieved at the transmission rate B. In other cases, it is determined that synchronization has not been achieved.

With such a method, synchronization can be established even when there are a plurality of transmission rates. However, in this case, the time required until the correlation value between the synchronization sequence of the slot used by itself and the sample value sequence of the received signal first exceeds the threshold depends on the applied transmission rate. Therefore, the time required until frame synchronization is established is not constant.

Therefore, an object of the present invention is to provide a frame synchronization device capable of establishing more accurate frame synchronization. It is another object of the present invention to provide a frame synchronization device in which a time required until frame synchronization is established is constant in a TDMA system having a plurality of transmission rates.

[0010]

According to a first aspect of the invention, in a TDMA system having a plurality of transmission rates, a frame synchronizer executes the following processing. That is, the correlation value between the sample value sequence of the received signal and the assigned synchronization sequence is calculated during the longest frame period of the plurality of assumed transmission rates. Then, all positions where the correlation value exceeds the predetermined threshold value are recorded (first step search mode processing).
Next, for all positions where the correlation value exceeds a predetermined threshold value, a search window is set after the longest frame period from that position. Then, the correlation between the synchronization sequence and the sample value sequence of the received signal is calculated for each search window. This (of calculation)
As a result, the position where the correlation value equal to or larger than the second threshold value is detected is searched (second step search mode processing). Furthermore, the actual transmission rate is determined from among a plurality of assumed transmission rates from the time interval of the position where the correlation value equal to or greater than the second threshold value is detected. In this way, synchronization is established (transmission rate determination processing).

According to the second aspect of the invention, in the TDMA system having a plurality of transmission rates, the frame synchronizer executes the following processing. That is, the correlation value between the sample value sequence of the received signal and the assigned synchronization sequence is calculated during the longest frame period of the plurality of assumed transmission rates.
Then, all positions where the correlation value exceeds the predetermined threshold value are recorded (first step search mode processing). Next, for all positions where the correlation value exceeds a predetermined threshold value, a search window is set after the shortest frame period from that position. Then, for each search window, the correlation between the synchronization sequence φ and the sample value sequence of the received signal and the correlation between another synchronization sequence φ ′ and the sample value sequence of the received signal are calculated. As a result of this (calculation), the position where the correlation value equal to or greater than the second threshold value is detected is searched (second step search mode processing). Furthermore, the actual transmission rate is determined from among a plurality of assumed transmission rates from the time interval of the position where the correlation value equal to or greater than the second threshold value is detected. In this way, synchronization is established (transmission rate determination processing).

In the third invention, in a TDMA system having a plurality of transmission rates, the frame synchronizer executes the following processing. That is, the correlation value between the sample value sequence of the received signal and the assigned synchronization sequence is calculated during the shortest frame period of a plurality of assumed transmission rates.
(First stage search mode processing). When the correlation value exceeds the predetermined threshold value in the first stage, the search window is set after the shortest frame period from that position. And regarding that search window,
The maximum value of the correlation is obtained for each synchronization sequence by calculating the correlation between the synchronization sequence φ and the sample value sequence of the received signal, and the correlation between another synchronization sequence φ ′ and the sample value sequence of the received signal. The maximum value of the correlation thus obtained is compared with the second threshold value. Further, when any one of the maximum correlation values exceeds the second threshold value, it is determined that the frame synchronization is established, and the actual transmission rate is determined.

[0013]

FIG. 1 shows a frame synchronizer according to a first embodiment of the present invention. The frame synchronizer is controlled by the control unit 1.

A received signal received from a base station (not shown) is input to the AD converter 11. The received signal is this A
It is converted into a digital signal by the D converter. AD converter 1
The output of 1 is connected to the reception buffer 12. The output of the reception buffer 12 is connected to the correlator 13.
The correlator 13 calculates the correlation between the sample value sequence of the received signal and the synchronization sequence φ according to the instructions from the reception buffer 12 and the mode switching unit 14. The mode switch 14 has
A timer 16 that notifies the elapse of a designated time and a synchronization sequence table 17 are connected. The synchronization sequence table 17 stores in advance all the synchronization sequence patterns to be used and the transmission sequence of the synchronization sequences used at each of the plurality of transmission rates. Therefore, the relative positional relationship of any synchronization sequence in the frame can be understood.

The operation of the frame synchronizer shown in FIG. 1 will be described below. In this embodiment, a case where two types of transmission rates as shown in FIG. 2 are assumed will be described. First,
The symbols used in the following description are defined as follows.

(A) 1 slot time: Ts (b) 2 (kind) transmission rate frame periods T1 and T2
Relationship: T1 = Ts × N1 T2 = Ts × N2 (T1 ≦ T2) (c) Transmission order of the frame sequence T1 and the synchronization sequence transmitted in the frame period T2: φ1 = {φ1 (0), φ1 (1) , ・ ・ ・, Φ1 (N1-1)} φ2 = {φ2 (0), φ2 (1), ..., φ2 (N2-1)}

First, data wirelessly transmitted by a TDMA method from a base station (not shown) is input to an AD converter 11 via an antenna (not shown), an AGC amplifier, a quadrature detector, etc. of a mobile station. The reception signal input to the AD converter 11 is sampled using a sampling clock (not shown) as a timing signal. The sampled value sequence of the received signal is output to the reception buffer 12.

First, the control unit 1 instructs the mode switching unit 14 to start frame synchronization. Upon receiving this instruction, the mode of the mode switch 14 is set to the first stage. The mode switching unit 14 initializes the reception buffer 12 when set in the first stage. Then, the reception buffer 12 waits until a reception signal of a length necessary for calculating the correlation (for example, a data time corresponding to the number of symbols forming the synchronization sequence) is accumulated. The reception buffer 12 receives the sample value of the reception signal from the AD converter 11 each time the mode switching unit 1 receives the sample value.
4 is reported. Therefore, by counting the number of times (reporting), it can be determined whether or not the data of the required length has been accumulated in the reception buffer 12. The predetermined number of times is set to, for example, the number of symbols in the synchronization sequence × the number of oversamples.

When the data is accumulated in the reception buffer 12, the mode switching unit 14 retrieves the pattern of the synchronization sequence φ of the allocation slot from the synchronization sequence table 13 and sets the synchronization sequence φ in the correlator 12. Then, in the correlator 13,
It is instructed to calculate the correlation between the set synchronization sequence φ and the sample value sequence of the received signal. The correlator 13 synchronizes with the synchronization sequence φ each time new reception data enters the reception buffer 12.
And the correlation with the sample value series of the received signal in the calculation section are calculated. More specifically, each time new reception data is input to the reception buffer 12, the correlation calculation interval is set to 1
Synchronous series φ shifted by the sampling clock cycle
The correlation is calculated by taking the complex correlation between the symbol and the symbol interval of the sampled sequence of the received signal. The correlator 13 reports the value to the mode switcher 14 every time the correlation value is obtained. Each time the mode switching unit 14 reports the calculated value of the correlation from the correlator 13, the mode switching unit 14 determines whether or not the value exceeds the preset first threshold value. When the correlation value exceeds the first threshold value, the mode switching unit 14 records the detected position.

The above process is repeated for the longest frame period (hereinafter, simply referred to as "longest frame period") of the plurality of assumed transmission rates. That is, in this embodiment, the above processing is performed during the frame period T2. In this connection, the shortest frame period among the plurality of assumed transmission rates will be hereinafter referred to as "shortest frame period". After the longest frame period has elapsed, the mode of the mode switcher 14 is set to the second stage.

The mode switch 14 set in the second stage
First stops the operation of the correlator 13. Then, with respect to all the detection positions whose correlation values exceed the first threshold value in the first stage, the correlation is calculated again around the time T2 after each detection position. That is, the search window is set around T2 hours after each detection position. This search window has a certain time width before and after the time T2 after each detection position. The number of search windows to be set matches the number of times the correlation value exceeds the first threshold in the first stage.

The mode switch 14 sets the synchronization sequence φ of the assigned slot in the correlator 13. Next, mode switcher 1
4 instructs the correlator 13 to calculate the correlation between the synchronization sequence φ of the allocation slot and the sample value sequence of the received signal for all the set search window width sections. The correlator 13 calculates the correlation between the assigned synchronization sequence φ and the sample value sequence of the received signal in the calculation period for each search window width section. This calculation is performed while shifting the correlation calculation section by the period of one sampling clock, as in the calculation in the first stage. The result is reported to the mode switcher 14.

When the correlator 13 finishes calculating the correlation for all the search window sections, the mode switching unit 14 stops the operation of the correlator 13. Each time the mode switching unit 14 reports the correlation value from the correlator 13, the mode switching unit 14 determines whether or not the value exceeds the second threshold value. Then, the detection interval of the correlation value exceeding the second threshold is grasped. If the received signal is transmitted in the frame period T1, the correlation value equal to or higher than the first threshold can be detected multiple times in the first stage. For example, in the case of the transmission rate A shown in FIG. 2A, it is assumed that the detection is performed twice or more in the first stage.

From the detection interval of the correlation value exceeding the second threshold value, the frame period is known and the transmission rate is known. For example, when the intervals are continuous, the average value of the intervals can be determined as the frame period. In this way, the mode switching unit 14 reports to the control unit 1 that the frame synchronization has been established. At the time of this report, the transmission rate found together is reported. Further, the start position of the next frame is calculated and reported.

In the second step, if the correlation value never exceeds the second threshold value, the process returns to the first step and the processing is repeated.

The processing procedure of this embodiment will be described below with reference to FIGS. 3 and 4.

[First Step Search Mode Processing] Step S1
At, the mode switch 14 initializes the reception buffer 12. In step S2, the sample value of the reception signal output from the AD converter 11 is stored in the reception buffer 12. In step S3, the correlation calculation section of the reception sequence for calculating the correlation value between the synchronization sequence φ of the allocation slot and the sample value sequence of the reception signal is initialized. In step S4, the correlator 13 calculates the correlation value between the sample value series of the received signal and the synchronization series φ within the set correlation calculation section. In step S5, the correlation value and the first threshold value are compared. If the correlation value exceeds the first threshold value, the process proceeds to step S6. If the correlation value does not exceed the first threshold value, the process proceeds to step S8.

In step S6, the position of the sampled value sequence of the received signal whose correlation value exceeds the first threshold value is stored.
In step S8, it is determined whether the calculation for the longest frame cycle time has been completed. If the calculation for the longest frame period has not been completed, the process proceeds to step S7. If the calculation for the longest frame period has been completed, step S
Proceed to 9. In step S7, the correlation calculation section of the reception sequence is shifted by the period of one sampling clock, and the process returns to step S4.

[Second Step Search Mode Processing] Step S9
In, the search window width section is set around the position after the longest frame cycle time from the position where the correlation value that first exceeds the first threshold value is detected. In step S10, the process waits until the sample value series of the received signal in the first search window section is accumulated in the reception buffer 4. In step S11, the correlation value between the synchronization sequence φ of the assigned slot and the sample value sequence of the received signal in the search window section is calculated. Step S12
At, it is determined whether the calculation of the search window section is completed. If the calculation of the search window section is not completed, the process proceeds to step S13, and if the calculation of the window search section is completed, the process proceeds to step S15. In step S13,
The correlation calculation section of the sample value series of the received signal is shifted by the period of one sample clock, and the process returns to step S11.

In step S14, it is judged whether or not the calculation of the correlation value in the search window section at all the detection points is completed. If the calculation of the correlation value has not been completed for all the detection points, the process proceeds to step S15, and if the calculation of the correlation value has been completed for all the detection points, step S15.
Proceed to 17. In step 15, a search window section is set for the next detection point, centered after the longest frame period. In step S16, the sample value series of the received signal in the next search window section is accumulated in the reception buffer 12. When the sample value series of the received signal is accumulated in the reception buffer 12, the process returns to step S11. In step S17, it is determined whether the correlation value exceeds the second threshold value in all the search windows in the second stage. If the correlation value does not exceed the second threshold value, the process returns to step S3, and if the correlation value exceeds the second threshold value, the process proceeds to step S18.

[Transmission Rate Judgment Processing] In step S18, the actual transmission rate is judged from a plurality of assumed transmission rates according to the time interval between the detection positions of the correlation value exceeding the second threshold value. Further, the start position of the next frame is calculated from the determined transmission rate and the position where the calculation result of the correlation exceeds the second threshold value. In step S19, the control unit 1 is notified that frame synchronization has been established. The start position of the next frame is also reported.

FIG. 5 is a block diagram of a frame synchronizer showing a second embodiment of the present invention. Elements common to those of the frame synchronizer of the embodiment shown in FIG. 1 are designated by common reference numerals. In this embodiment, the output of the reception buffer 12 is given to the correlators 42 and 43.

When a base station (not shown) gives an instruction to establish frame synchronization, the control unit 1 causes the mode switching unit 14 to operate.
Instruct to establish frame synchronization. Upon receiving this instruction, the mode of the mode switch 14 is set to the first stage. The mode switch 14 set in the first stage initializes the reception buffer 12. Then, the reception buffer 12
Wait until the sample value sequence of the received signal of the length necessary for calculating the correlation is accumulated. When the data is accumulated in the reception buffer 12, the mode switching unit 14 takes out the pattern of the synchronization sequence φ of the allocation slot from the synchronization sequence table 44, and sets the synchronization sequence φ in the correlator 42.
Then, the correlator 42 is instructed to calculate the correlation between the set synchronization sequence φ and the sample value sequence of the received signal. The correlator 42 that has received the instruction shifts the correlation calculation section by one sampling clock cycle each time new reception data enters the reception buffer 12, and the correlation series φ and the sample value series of the reception signal in the calculation section are shifted. Calculate the correlation. Then, the calculation result is reported to the mode switching unit 14. Each time the mode switcher 14 reports the calculated value of the correlation from the correlator 42, the mode switcher 14 determines whether or not the correlation value exceeds a preset first threshold value. When the correlation value exceeds the first threshold value, the detected position is recorded.

The above processing is performed during the longest frame period T2. After the elapse of the longest frame period T2, the mode of the mode switch 14 is set to the second stage.

The mode switch 14 set in the second stage
First stops the operation of the correlator 42. Then, the following processing is performed. That is, the mode switching unit 14 sets the synchronizing sequence φ in the correlator 42 and the synchronizing sequence φ ′ shown in the following equation (1) in the correlator 43.

Φ ′ = φ2 ((s2 + N1) mod N2) (1) where φ = φ2 (s2)

The mode switch 14 further sets a search window for all the detection positions whose correlation value exceeds the first threshold value in the first step, centered after the shortest frame period from each detection position. That is, a search window having a constant time width is set before and after the time T1 after each detection position.

The correlator 42 and the correlator 43 set the synchronization sequences φ and φ ′ for the respective search window periods.
And the correlation with the sampled sequence of the received signal are calculated. Similar to the correlation calculation in the first stage, this calculation is performed while shifting the correlation calculation section by the period of one sampling clock. The correlator 42 and the correlator 43 are
The calculated correlation value is reported to the mode switcher 14. When the correlators 42 and 43 have finished calculating the correlations for all the search window sections, the mode switcher 14
Stop the operation of the correlator. The mode switcher 14
It is determined whether the correlation value calculated by the correlators 42 and 43 exceeds the preset second threshold value.
And the detection interval of the correlation value exceeding the second threshold, and
It is determined whether the synchronization sequence φ or φ ′ was used at the time of detection.

If φ is used to detect the detected value exceeding the second threshold value, the frame period can be determined to be T1, and if φ'is used, the frame period can be determined to be T2. As a result, the mode switcher 14 determines the transmission rate and reports to the controller 1 that the frame synchronization has been established. In addition, the transmission rate found in this report will also be reported. Furthermore, the start position of the next frame is calculated and this is also reported.

The processing procedure of this embodiment will be described below with reference to FIGS. 6 and 7.

[First Step Search Mode Processing] In steps S31 to S39 of FIG. 6, the same processing as steps S1 to S9 in FIG. 3 is performed to execute the first step search mode processing.

[Second Stage Search Mode Processing] In step S40 in FIG. 7, the search is performed centering after the shortest frame period from the first position where the correlation value exceeding the first threshold value is detected in the first stage mode. The window is set. Then, the data of the sample value series of the received signal in the section of this search window width is accumulated in the buffer. In step S41, the correlation between the synchronization sequence φ and the sample value sequence of the received signal in the search window section is calculated. In step S42, equation (1)
The correlation between the synchronization sequence φ ′ indicated by and the sample value sequence of the received signal in the same window search section as in step S41 is calculated. In step S43, it is determined whether the calculation of the correlation in the window search section is completed. If the calculation of the correlation is not completed, the process proceeds to step S48, and if the calculation of the correlation is completed, the process proceeds to step S44. Step S44
In step 1, the correlation calculation section is shifted by one sampling clock cycle in the window search section, and the process returns to step 41.

In step S45, it is determined whether or not the calculation of the window search section is completed for all the detection points whose correlation value exceeds the first threshold value. If the calculation of the correlation has not been completed for all the detection points, step S3
Returning to step 3, if the correlation calculation has been completed for all the detection points, the process proceeds to step S49. In step S46, the window search section regarding the next detection point is set. In step S47, the data of the sample value series of the reception signal in the next window search section is accumulated in the reception buffer. Then, it returns to step S41. In step S48,
It is determined whether the correlation value calculated in steps S41 and S42 exceeds the second threshold value in a certain search window section. If the detected value does not exceed the second threshold value in all search window sections, the process returns to step S33, and if the detected value exceeds the second threshold value in a certain search window section, the process proceeds to step S49.

[Transmission Rate Judgment Processing] In step S49, the transmission rate is judged by the time interval of the position where the correlation value exceeding the second threshold value is detected and the synchronization sequence where the correlation value is detected. Then, the start position of the next frame is calculated from the position where the correlation value exceeding the second threshold value is detected and the used synchronization sequence. Finally, in step S50, the control unit 1 is notified that frame synchronization has been established.

Further, a third embodiment of the present invention will be described below. The third embodiment has the same hardware configuration as that of the second embodiment. Therefore, with reference to FIG.
The operation of this embodiment will be described.

[First Stage Search Mode Processing] Also in the third embodiment, as in steps S1 to S3 in FIG. 3, the correlation calculation section is initialized (step S).
51-S53). Then, in step S54, the mode switching unit 14 instructs the correlator 42 to determine the correlation value C42 between the synchronization sequence φ of the assigned slot and the sample value sequence of the received signal.
Instruct to calculate. The correlator 42 shifts the correlation calculation section by one sampling clock cycle each time new reception data enters the reception buffer 12, and obtains the correlation value C42 between the synchronization sequence φ and the sample value series of the reception signal in the calculation section. calculate. Then, the calculation result is reported to the mode switching unit 14. In step S55, the mode switching unit 14 determines whether the correlation value C42 reported from the correlator 42 exceeds the predetermined first threshold value. When the correlation value C42 exceeds the first threshold value, the mode of the mode switch 14 is set to the second stage. If the correlation value C42 does not exceed the first threshold value, the process proceeds to step S5a. In step S5a, the calculation section of the correlation is shifted, and the process returns to step S54.

[Second-stage search mode processing] The mode switch 14 set in the second stage first stops the operation of the correlator 42. Subsequently, the mode switcher 14 sets the search window centered after the shortest frame period from the timing when the correlation value C42 exceeds the first threshold value in the first step. That is, a search window having a fixed time width is set before and after the time T1 after the detection timing (step S56,
S57). In steps S58 and S59, the mode switcher 14 supplies the synchronization sequence φ to the correlator 42,
The synchronization sequence φ ′ is set in the correlator 43, respectively. Then, the reception buffer 12 is initialized.

After the data is stored in the reception buffer 12, the mode switcher 14 instructs the correlators 42 and 43 to calculate the correlation value. The correlator 42 calculates a correlation value C42 between the set synchronization sequence φ and the sample value sequence of the received signal. Further, the correlator 43 has a correlation value C4 between the set synchronization sequence φ ′ and the sample value sequence of the received signal.
Calculate 3. Similar to the correlation calculation in the first stage, these calculations are performed while shifting the correlation calculation section by the period of one sampling clock. Correlator 42
And the correlator 43 reports the calculated correlation values C42 and C43 to the mode switcher 14, respectively. Step S
At 60, the mode switcher 14 determines whether the calculation of the correlation in the window search section is completed. If the calculation of the correlation is not completed, the process returns to step S58, and if the calculation of the correlation is completed, the process proceeds to step S61.

[Comparison Processing] In step S61, the maximum value C of the correlation values calculated by the correlators 42 and 43 is calculated.
42max and C43max are obtained for each correlator. Then, the maximum correlation values C42max and C43max of the respective
Is compared with a second predetermined threshold. As a result of this comparison, it is determined whether either C42max or C43max exceeds the second threshold value. If any of the maximum correlation values exceeds the second threshold value, step S
Proceed to 62. If none of the maximum correlation values exceeds the second threshold value, the process returns to step S53 and the process is restarted from the beginning.

[Transmission Rate Judgment Process] In step S62, if any of the maximum correlation values exceeds the second threshold value, the transmission rate is found from the synchronization sequence used by the correlator that calculated the correlation value. Therefore, in step S63, the fact that frame synchronization has been established is reported to the control unit 1.

Hereinafter, the correlator applied to the embodiment of the present invention will be described in more detail with reference to FIG. In FIG. 9, a case where this correlator is applied to the frame synchronizer of the first embodiment will be described as an example.

The received signal supplied from the reception buffer 12 is supplied to the frequency offset estimation unit 131. At the same time, it is given to the frequency offset compensating unit 133 via the delay circuit 132. Frequency offset estimation unit 131
Estimates the frequency offset of the input received signal. The value of the estimated frequency offset is sent to the frequency offset compensator 133 via the estimated value limiter 134.
Given to. The frequency offset compensating unit 133 compensates the frequency offset of the received signal from the given frequency offset. The output of the frequency offset compensator 133 is given to the correlation calculator 135. Correlation calculator 135
Calculates the correlation using the received signal whose frequency offset is compensated and the synchronization sequence. Then, the calculation result is reported to the mode switcher 14.

The frequency offset estimated by the frequency offset estimation unit 131 is limited by the estimated value limiter 134. The limited value is input to the frequency offset compensator 133. The control unit 1 determines the limiter value from the carrier frequency stability on both the transmitting side and the receiving side and the information on the frequency band. Then, this limiter value is given to the estimated value limiter 134 via the mode switching unit 14 at the start of a call and at the time of handoff. By using the estimated value limiter 134 in this way, an abnormal estimated frequency offset value can be eliminated in advance. Therefore, it is possible to prevent erroneous establishment of frame synchronization.

FIG. 10 shows another structure of the correlator. The reception signal provided from the reception buffer 12 is provided to the frequency offset estimation unit 131. At the same time, the delay circuit 13
2 to the frequency offset compensator 133. The frequency offset estimation unit 131 estimates the frequency offset of the input received signal. The value of the estimated frequency offset is the frequency offset compensator 133.
Given to. The estimated frequency offset value is also given to the mode switch 14.

The frequency offset compensating unit 133 compensates the frequency offset of the received signal from the given frequency offset. The output of the frequency offset compensator 133 is given to the correlation calculator 135. The correlation calculation unit 134
Correlation is calculated using the received signal whose frequency offset is compensated and the synchronization sequence. Then, the calculation result is reported to the mode switcher 14. Every time the correlation calculation unit 134 reports the correlation calculation result, the mode switching unit 14 compares the calculation result with a predetermined threshold value. When the correlation calculation result exceeds the threshold value, the estimated frequency offset at that time is set to the frequency offset estimation unit 13
Read from 1 and record.

As described above, the correlation calculation result is reported from the correlator 13 to the mode switcher 14. When the mode of the mode switch 14 is set to the first stage, the calculation result of the box of the mode switch 14 is compared with the first threshold value. When the calculation result of the correlation exceeds the first threshold value, the estimated frequency offset f1 at that time is read from the frequency offset estimation unit 131 and recorded. Further, when the mode of the mode switcher 14 is set to the second stage, the mode switcher 14 compares the calculation result with the second threshold value. When the calculation result of the correlation exceeds the second threshold value, the estimated frequency offset f2 at that time is read from the frequency offset estimation unit 131 and recorded.

Next, the mode switch 14 obtains the difference between the estimated frequency offset f1 and the estimated frequency offset f2 at each point where the correlation calculation result exceeds the first threshold in the first mode. At a detection point where this difference is larger than the second threshold value, there is a high possibility that an erroneous correlation is detected due to frequency Doppler shift, frequency offset, or the like.
Therefore, this detection point is ignored when establishing synchronization.

The present invention is not limited to the above embodiment, but various modifications can be made. The following are examples of such modifications. (A) The components such as the reception buffer, the timer, and the mode switch shown in each of the above embodiments are general components for controlling frame synchronization, and other components are used. The present invention can also be applied to a frame synchronization device that controls by using the above method. (B) In the first embodiment, two transmission rates have been described, but the present invention can be applied even when three or more transmission rates are assumed. (C) In the second embodiment, the case where the reference frame has the short frame period T1 has been described, but the present invention can be applied to the case where the reference frame has the longest frame period T2. When the frame period T2 is used as the reference frame, the correlation value may be calculated by the correlator 22-2 using the synchronization sequence φ ′ shown in the following equation (2). φ '= φ1 ((s1 + N2) mod N1) (2) where φ = φ1 (s1)

(D) Further, the case where two transmission rates are assumed has been described, but the second embodiment is applicable even when three or more transmission rates are assumed. In this case, in the second step, the correlation value may be calculated using the synchronization sequence of the frames other than the reference frame, which is obtained in the same manner as the equation (1). (E) In the second embodiment, the case where the synchronization sequence φ ′ is used as the synchronization sequence having the longest frame period T2 has been described, but the synchronization sequence φ ′ may not be found in some cases. In such a case, the correlator 43 is instructed to calculate the correlation value using a pattern having a low correlation value with any of the synchronization sequences of the longest frame period, or the correlator 43 It is also possible not to give an instruction to calculate the correlation value.

[0060]

As described above, the present invention reduces the possibility of false detection of synchronization. Further, even in a system to which a plurality of communication rates are applied, the time required until the synchronization is established becomes constant.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a frame synchronization device of the present invention.

FIG. 2 is a diagram showing a frame structure of a TDMA transmission system.

FIG. 3 is a flowchart (I) showing an operation of the frame synchronization device shown in FIG.

4 is a flowchart (II) showing the operation of the frame synchronization device shown in FIG.

FIG. 5 is a block diagram showing another embodiment of the frame synchronization device of the present invention.

6 is a flowchart (I) showing the operation of the frame synchronization device shown in FIG.

7 is a flowchart (II) showing the operation of the frame synchronization device shown in FIG.

FIG. 8 is a flowchart showing another operation of the frame synchronization device shown in FIG.

FIG. 9 is a block diagram showing a configuration of a correlator 13.

FIG. 10 is a block diagram showing another configuration of a correlator 13.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Control part 11 ... AD converter 12 ... Reception buffer 13 ... Correlator 14 ... Mode switching device 17 ... Sync sequence table

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04L 29/08 H04L 13/00 307C (72) Inventor Ryoichi Miyamoto 1-7 Toranomon, Minato-ku, Tokyo No. 12 Oki Electric Industry Co., Ltd.

Claims (5)

[Claims] 1. A frame synchronization device of a receiver used in a TDMA communication system having a plurality of communication rates, wherein a synchronization sequence of time slots assigned to the receiver,
Correlation means for obtaining a correlation with a synchronization sequence included in the received signal, and mode switching means for switching the frame synchronization device between a first mode and a second mode, wherein the plurality of modes assumed in the first mode are used. During the longest one of the communication rates, the positions exceeding the first threshold detected by the correlating means are recorded, and in the second mode, predetermined positions are recorded with respect to all the positions where the correlation exceeding the first threshold is recorded. After a lapse of time, a mode switching unit that compares the correlation between the synchronization sequence of the time slot and the synchronization sequence included in the received signal with a second threshold value is provided again. A frame synchronization device characterized by determining the establishment of frame synchronization based on a result of comparison with a threshold value. 2. The frame synchronization device according to claim 1, wherein the predetermined period is the longest one of the plurality of assumed communication rates. 3. The frame synchronizer according to claim 1, wherein the predetermined period is the shortest one of the plurality of assumed communication rates. 4. In a frame synchronization device of a receiver used in a TDMA communication system having a plurality of communication rates, a synchronization sequence of time slots assigned to the receiver,
Correlation means for obtaining a correlation with a synchronization sequence included in the received signal, and mode switching means for switching the frame synchronization device between a first mode and a second mode, wherein the plurality of modes assumed in the first mode are used. During the shortest communication rate, the positions exceeding the first threshold detected by the correlating means are recorded, and in the second mode, predetermined positions are recorded with respect to all positions where the correlation exceeding the first threshold is recorded. After a lapse of time, a mode switching unit that compares the correlation between the synchronization sequence of the time slot and the synchronization sequence included in the received signal with a second threshold value is provided again. A frame synchronization device characterized by determining the establishment of frame synchronization based on a result of comparison with a threshold value. 5. A frame synchronization method applied to a receiver used in a TDMA communication system having a plurality of communication rates, comprising: (a) in the first mode, a time slot assigned to the receiver for a predetermined period. Obtaining a first correlation between the synchronization sequence of the first synchronization sequence and a synchronization sequence included in the received signal; recording a position where the first correlation exceeds a first threshold; With respect to the position exceeding the threshold value, a step of setting a search window after a predetermined time is provided, and (b) in the second mode, within the interval of the search window, a synchronization sequence of time slots assigned to the receiver. And a step of obtaining a second correlation with a synchronization sequence included in the received signal, a step of determining whether the second correlation exceeds a second threshold value, and whether frame synchronization is established. or not It characterized by having a determining frame synchronization method.