JPH08298000A - Semiconductor memory - Google Patents

Abstract

PURPOSE: To obtain a semiconductor device in which conflict and floating are prevented and a conversion is made easily from a test pattern for logic simulation to a test program for LSI tester. CONSTITUTION: A flip-flop 14 takes in a signal S, outputted from a logic circuit performing a predetermined circuit operation, in synchronism with a clock signal CLK. The flip-flop 14 delivers a mode switch signal ENB to the mode switch signal input of an output buffer 12 having output side connected with the input side of an input buffer 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which can be easily tested.

[0002]

2. Description of the Related Art Conventionally, as a part of a semiconductor device test, a test pattern generated by a test program for an LSI tester is applied to a semiconductor device, and a value output from the semiconductor device and a test program for the LSI tester are applied. There is widely adopted a method of judging the quality of a semiconductor device by comparing it with the expected value of. Here, if a test program for the LSI tester is created by converting it from a test pattern for logic simulation used for designing a semiconductor device, the labor for creating the test program for the LSI tester is reduced.

However, in the logic simulation, a test pattern is applied to a semiconductor device that is logically simulated at each simulation time. On the other hand, in the LSI tester, the test pattern is obtained every cycle due to the hardware limitation of the LSI tester. Is applied to the semiconductor device with a specific waveform. Therefore, in order to convert the test pattern for the logic simulation into the test program for the LSI tester, information on the cycle and the waveform format is required.

FIG. 4 is a diagram showing a correspondence between a test pattern for logic simulation and a test program for an LSI tester created by converting the test pattern for logic simulation. To convert the test pattern for logic simulation into a test program for LSI tester, the test pattern for logic simulation is divided into predetermined cycles as shown in FIG. 4, and the waveform value of each cycle is determined according to the waveform format. It is sampled and converted into a test program for the LSI tester.

By the way, when converting a test pattern for logic simulation into a test program for an LSI tester, it is possible to switch between an input mode and an output mode.
An input / output buffer having a bidirectional input / output terminal (hereinafter abbreviated as a bidirectional terminal) may be used. FIG. 5 is a diagram showing the input / output buffer.

The input / output buffer 10 shown in FIG. 5 comprises a pad 13 as a bidirectional terminal, an input buffer 11 and an output buffer 12. Output buffer 12
The output side of is connected to the input side of the input buffer 11 and the pad 13. The output buffer 12 also has a mode switching signal input terminal to which a mode switching signal ENB_ for switching between a mode in which the output side is held in a high impedance state and a mode in which a signal on the input side is transmitted to the output side is input. When the “H” level mode switching signal ENB_ is input to the mode switching signal input terminal of the output buffer 12, the input / output buffer 10 enters the input mode in which the output side of the output buffer 12 is held in the high impedance state, and the pad 13 Input signal to the input buffer 1
1 is input to a logic circuit (not shown). On the other hand, when the'L 'level mode switching signal ENB_ is input to the mode switching signal input terminal, the input / output buffer 10 enters the output mode in which the signal on the input side of the output buffer 12 is transmitted to the output side and is not shown. The output signal of the logic circuit is output to the pad 13 via the output buffer 12.

FIG. 6 is a diagram showing a correspondence between a test pattern for logic simulation in the input / output buffer shown in FIG. 5 and a test program for an LSI tester created by converting the test pattern for logic simulation. Is. Input / output buffer 10 shown in FIG.
In order to convert the test pattern for the logic simulation into the test program for the LSI tester, the test pattern for the logic simulation is divided at a predetermined cycle, and the waveform value of each cycle is sampled in accordance with the waveform format. It is necessary to determine whether the sampling timing is the input mode for inputting data or the output mode for outputting data.

The signal PAD shown in FIG. 6 is applied to the pad 13 as a test pattern for logic simulation. The signal PAD is divided into periods N, N + 1, N + 2, and the mode switching signal EN of the'H 'level, the'L' level, and the'H 'level is divided in accordance with the divided periods.
B_ is input. Here, the mode of each cycle is determined from the level of the mode switching signal ENB_. In cycle N,
Since the "H" level is input as the mode switching signal ENB_, the cycle N is determined to be the input mode, the input / output buffer 10 is switched to the input mode, and the "H" level of the signal PAD input to the pad 13 is changed. The'level waveform is sampled and converted into the input value '1' for the LSI tester. Next, in the cycle N + 1, since the'L 'level is input as the mode switching signal ENB_,
The cycle N + 1 is determined to be the output mode, the input / output buffer 10 is switched to the output mode, and the output buffer 12
An “L” level signal is output from the pad 13 via the, and this “L” level signal is converted to the expected value “0” for the LSI tester. Further, in the cycle N + 2, the cycle N
Similarly, since the “H” level is input as the mode switching signal ENB_, the input mode is determined, and the “H” level waveform of the signal PAD input to the pad 13 is sampled. Converted to input value '1' for tester. In this way, the test pattern for logic simulation is converted into the test program for LSI.

In addition to the method shown in FIG. 6, the cycle is divided according to the'H 'level or'L' level of the mode switching signal ENB_, and the mode of each divided cycle is determined by the level of the mode switching signal ENB_. There is also a method of making a judgment and converting a test pattern for logic simulation into a test program for an LSI tester.

[0010]

The mode switching signal ENB_ shown in FIG. 6 is generally a signal from a logic circuit in the semiconductor device which performs a predetermined circuit operation.
The mode switching signal E is generated during one cycle divided by a predetermined cycle.
The level of NB_ may change multiple times. Then
Within the period, the input / output buffer 10 is switched to the input mode or the output mode and the waveform is sampled in a state where the input mode or the output mode is determined. When converting to a test program, a conversion error may occur, and when a test is performed using such a test test program for an LSI tester, the test pattern output from the LSI tester and the input / output buffer 10 are output. There may be a conflict with the signal output from the. When both the LSI tester and the input / output buffer 10 are in the input mode, floating occurs. When such a conflict or floating occurs, the design intention is not reflected in the test, and an unexpected value may sneak into the logic circuit.

On the other hand, when determining the mode of each cycle according to the'H 'level or'L' level of the mode switching signal ENB_, the LSI tester side makes the'H 'level or'L' level of the mode switching signal ENB_. It is necessary to define the timing set and the waveform according to the above, and the LSI tester is restricted accordingly. Furthermore, the mode switching signal E
It is also necessary to design a circuit to prevent the occurrence of conflict or floating due to the delay of NB_.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor device in which a conflict or floating is prevented and a test pattern for logic simulation is easily converted into a test program for an LSI tester. .

[0013]

According to another aspect of the present invention, there is provided a semiconductor device including: (1) an input buffer, (2) an output side connected to an input side of the input buffer,
An output buffer having a mode switching signal input terminal to which a mode switching signal for switching between a mode in which its output side is held in a high impedance state and a mode in which a signal on the input side is transmitted to its output side is input (3) Predetermined circuit operation And a mode switching circuit for inputting the signal output from the logic circuit for performing the operation in synchronization with a predetermined clock signal and inputting the input signal to the mode switching signal input terminal.

[0014]

According to the semiconductor device of the present invention, a mode in which a signal output from a logic circuit performing a predetermined circuit operation is taken in in synchronization with a predetermined clock signal and the taken signal is input to a mode switching signal input terminal of an output buffer Since a switching circuit is provided, the mode of the output buffer is changed within each cycle when the logic simulation test pattern is divided into predetermined cycles when converting from the logic simulation test pattern to the LSI tester test program. The level of the mode switching signal input to the switching signal input terminal can be set so as not to change a plurality of times. Therefore, it is possible to prevent the occurrence of a conflict or a floating caused by the mode switching signal changing a plurality of times within one cycle in the conventional technique. Also, compared with the case where the mode of each cycle is determined and converted according to the level of the mode switching signal,
The restrictions imposed on LSI testers are relaxed.

Furthermore, since the signal output from the logic circuit is taken in in synchronization with a predetermined clock signal, there is no need to design the circuit in consideration of the delay of the mode switching signal, and the LSI tester can be used from the test pattern for logic simulation. Conversion to a test program for use is easy.

[0016]

Embodiments of the present invention will be described below. FIG. 1 is a circuit diagram of an input / output circuit portion of a semiconductor device according to an embodiment of the present invention. In addition to the input / output buffer 10 described in FIG. 4, FIG. 1 shows a flip-flop 14 (mode switching circuit according to the invention) and a pad 15 to which a clock signal CLK is input. The pad 15 is connected to the clock terminal CK of the flip-flop 14. The output terminal Q of the flip-flop 14 is connected to the mode switching signal input terminal of the output buffer 12.

A signal S from a logic circuit (not shown) that performs a predetermined circuit operation is input to the data terminal D of the flip-flop 14. Further, the clock signal C is supplied to the clock terminal CK of the flip-flop 14 via the pad 15.
LK is input. FIG. 2 is a timing chart of the semiconductor device shown in FIG. 3 is a diagram showing a test program for the LSI tester converted based on the timing chart shown in FIG.

The signal PAD shown in FIG. 2 is input to the pad 13 as a test pattern for logic simulation. The signal PAD has cycles N, N + 1, N + 2, N + 3.
It is separated by N + 4. Clock signal CL at time T ₁
When K falls, the flip-flop 14 receives the'H 'level signal S input to the data terminal D. The captured “H” level signal S is output from the output terminal Q as an “H” level mode switching signal ENB_. Output "H" level mode switching signal E
NB_ is input to the mode switching signal input terminal of the output buffer 12, the input / output buffer 10 is set to the input mode, the'H 'level waveform of the signal PAD in the cycle N is sampled, and it is used for the LSI tester shown in FIG. Converted to input value '1'. Here, as shown in FIG.
In, the input / output buffer 10 is maintained in the input mode during the period N even if the level of the signal S changes a plurality of times.

Next, when the clock signal CLK falls at time T ₂ , the flip-flop 14 takes in the signal S of the'L 'level which is inputted to the data terminal D this time. The captured “L” level signal S is output from the output terminal Q of the flip-flop 14 as an “L” level mode switching signal ENB_. The output “L” level mode switching signal ENB_ is input to the mode switching signal input terminal of the output buffer 12, and the input / output buffer 10
Becomes an output mode, and an'L 'level signal is output to the pad 13 via the output buffer 12. This'L 'level signal is converted into the expected value' 0 'for the LSI tester shown in FIG. Even if the level a of the signal S shown in FIG. 2 is indefinite, the input / output buffer 10
Are maintained in the output mode and the input / output buffer 10 is prevented from changing to the input mode. Similarly, the clock signal CLK sequentially falls at times T ₃ , T ₄ , and T ₅ , so that the input values “1”, “1”, and expected value “1” for the LSI tester shown in FIG. 3 are sequentially output. To be converted. In this conversion, the mode of the input / output buffer 10 can be determined only by the value of the mode switching signal ENB_ immediately before the end of each cycle. When performing a test using the converted test program for the LSI tester shown in FIG. 3,
In the cycle N shown in FIG. 3, an “H” level signal as an input value “1” is input to the pad 13 from the LSI tester via the driver IC of the LSI tester. Next, in the cycle N + 1, the output buffer 12 and the pad 1
The signal output via 3 is input to the comparator IC of the LSI tester and compared with the expected value "0" for determination. Hereinafter, the same test is performed in the cycles N + 2, N + 3, N + 4.

[0020]

As described above, in the semiconductor device of the present invention, conflicts and floating are prevented, and it is not necessary to consider the delay of the mode switching signal when designing a circuit, and a test pattern for logic simulation is used. To the test program for the LSI tester is easily performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an input / output circuit portion of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a timing chart of the semiconductor device shown in FIG.

FIG. 3 is a diagram showing a test program for an LSI tester converted based on the timing chart shown in FIG.

FIG. 4 is a test pattern for logic simulation,
It is a figure which shows the correspondence with the test program for LSI testers created by converting the test pattern for the logic simulation.

FIG. 5 is a diagram showing an input / output buffer.

6 is a diagram showing the correspondence between a test pattern for logical simulation in the input / output buffer shown in FIG. 5 and a test program for an LSI tester created by converting the test pattern for logical simulation.

[Explanation of symbols]

 10 Input / Output Buffer 11 Input Buffer 12 Output Buffer 13,15 Pad 14 Flip-Flop

Claims (1)

[Claims] 1. A mode switch for switching between an input buffer and a mode in which an output side is connected to the input side of the input buffer and the output side is held in a high impedance state and a mode in which a signal on the input side is transmitted to the output side. An output buffer having a mode switching signal input terminal to which a signal is input, and a signal output from a logic circuit that performs a predetermined circuit operation is captured in synchronization with a predetermined clock signal, and the captured signal is the mode switching signal input terminal. And a mode switching circuit for inputting to the semiconductor device.