JPH08297596A - Sampling trace circuit - Google Patents

Abstract

PURPOSE: To obtain a sampling trace circuit of an emulator which can confirm the transition of data and its time interval without recording any unnecessary data. CONSTITUTION: A change detection means 16 monitors trace data 4 from an MCU applied system 1 and when the trace data do not change, a write inhibiting means 18 inhibits a write permission signal 12 outputted by a judging means 9 when sampling trace conditions are met from being inputted to a trace memory 5 and a trace memory 8 for time data to prevent the trace data from being recorded, and only when a change of the inputted trace data is detected and meets the sampling trace conditions, the trace data are recorded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling trace circuit in an emulator used when developing a program for a microcomputer (hereinafter referred to as MCU).

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a conventional sampling trace circuit. In the figure, 1 is an MCU application system using an MCU, 2 is an MCU in the MCU application system 1, and 3 is a resource such as a memory and an input / output port connected to the MCU 2. 4 is MCU2
And a resource 3 are MCU input / output signals as trace data, and 5 is an MCU input / output signal trace memory as a trace memory in which the MCU input / output signal 4 is recorded. 6 is a time data generation circuit for generating time data, 7 is time data generated by the time data generation circuit 6, and 8 is a time data trace memory in which the time data 7 is recorded.

Reference numeral 9 is a sampling trace circuit as a judging means for judging whether or not the target MCU 2 satisfies a predetermined sampling trace condition. Reference numeral 10 is in the sampling trace circuit 9 and is sent to the MCU. The MCU input / output signal storage unit 11 in which the input / output signal 4 is stored is also a sampling trace condition storage unit in the sampling trace circuit 9 in which preset sampling trace conditions are stored. 12 is when the sampling trace conditions match,
The write enable signal is sent from the sampling trace circuit 9 to the MCU input / output signal trace memory 5 and the time data trace memory 8. Reference numeral 13 is also from the sampling trace circuit 9 to the MCU input / output signal trace memory 5 and the time data trace. It is a write memory address sent to the memory 8.

Next, the operation will be described. With the trace function, the emulator records the MCU input / output signal 4 transmitted / received between the MCU 2 in the MCU application system 1 and various resources 3 such as memory and input / output port.
The history of the internal operation of U2 and the information of each resource 3 can be referred to from the outside. The recording of the MCU input / output signal 4 is performed only when the target MCU 2 in the sampling trace mode satisfies a certain condition.

The time data generation circuit 6 always outputs the time data 7
And the time data 7 is input to the time data trace memory 8. On the other hand, the MCU input / output signal 4 exchanged between the MCU 2 and the resource 3 in the MCU application system 1 is always input to the MCU input / output signal trace memory 5 and the sampling trace circuit 9. In the sampling trace circuit 9, the MC
The MCU input / output signal 4 from the U application system 1 is temporarily stored in the MCU input / output signal storage unit 10, and the contents of the MCU input / output signal storage unit 10 are constantly compared with the contents of the sampling trace condition storage unit 11.

When the contents of the MCU input / output signal storage unit 10 and the sampling trace condition storage unit 11 match each other, the sampling trace circuit 9 causes the MCU input / output signal trace memory 5 and the time data trace memory 8 to operate.
In response, the write enable signal 12 and the write memory address 13 are output. MC sent by this
The U input / output signal 4 is the sampling trace condition storage unit 11
Only when the sampling trace conditions set in are matched, the MCU input / output signal trace memory 5 has M
The CU input / output signal 4 is recorded, and the time data 7 at that time is recorded in the time data trace memory 8.

In the above sampling trace circuit, the MCU input / output signal trace memory 5 and the time data trace memory 8 are connected to the MCU only when the contents of the MCU input / output signal storage unit 10 and the sampling trace condition storage unit 11 match. Input / output signal 4 or time data 7
However, the MCU input / output signal storage unit 10
And the contents of the sampling trace condition storage unit 11 do not match, or whether the writing to the MCU input / output signal trace memory 5 and the time data trace memory 8 is determined based on the comparison result of the specific bit or the comparison result of the magnitude relationship. You may do it.

Here, as a document describing a technique related to a sampling trace circuit in such a conventional emulator, for example, Japanese Patent Laid-Open No. 6-959 is known.
13 and Japanese Patent Laid-Open No. 5-313947.

[0009]

Since the conventional sampling trace circuit is configured as described above, the MCU
Whether or not the input / output signal 4 matches the data written immediately before has not been determined. Therefore, if the sampling trace conditions match, the MCU input / output signal 4 and the time data are irrespective of whether the data changes. 7 is recorded. On the other hand, since the MCU input / output signal trace memory 5 on the recording side has a limited capacity, if only the data change is desired to be referred to, only the same data is recorded in the MCU input / output signal trace memory 5. However, there is a problem in that there are cases where changes in data cannot be referenced.

The present invention has been made in order to solve the above problems, focusing on the transition of data,
It is an object of the present invention to provide a sampling trace circuit capable of surely referring to data transitions and time intervals thereof by providing a mode for recording only when there is a change in the MCU input / output signal.

[0011]

The sampling trace circuit according to the present invention monitors the trace data from the MCU application system by the change detecting means, and when the change is not detected in the trace data, by the write inhibiting means,
When the sampling trace condition is satisfied, the write enable signal output by the judging means is blocked from being input to the trace memory and the time data trace memory, and there is a change in the input trace data. The trace data is recorded only when it matches.

[0012]

The sampling trace circuit according to the present invention determines whether the input trace data matches the trace data recorded immediately before, and traces the trace data satisfying the sampling trace condition only when the trace data does not match. By recording the time data at that time in the time data trace memory while recording in the memory, it is possible to prevent the same data from being recorded in the trace memory and to refer to the data transition of the trace memory capacity. It is also possible to refer to the time interval during data transition.

[0013]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a sampling trace circuit according to a first embodiment of the present invention. In the figure, 1 is an MCU application system, 2 is an MCU, 3 is a resource, 4 is an MCU input / output signal as trace data, 5 is an MCU input / output signal trace memory as trace memory, 6 is a time data generation circuit, and 7 is a time data generation circuit. Is time data, 8 is a time data trace memory, 9 is a sampling trace circuit as a determination means, 10 is an MCU input / output signal storage unit, 11 is a sampling trace condition storage unit, 12 is a write enable signal, and 13 is a write memory address. Since these are the same as or equivalent to those of the conventional one shown by attaching the same reference numerals in FIG. 2, detailed description thereof will be omitted.

Reference numeral 14 is an immediately preceding recording data latch circuit that holds the MCU input / output signal 4 recorded in the MCU input / output signal trace memory 5 immediately before, and 15 is output from the immediately preceding recording data latch circuit 14. This is the immediately preceding recording data latch signal. Reference numeral 16 is an MCU input / output as change detecting means for detecting a change in the MCU input / output signal 4 by comparing the immediately preceding recording data latch signal 15 with the MCU input / output signal 4 newly sent from the MCU application system 1. It is a signal comparison circuit. Reference numeral 17 indicates when the MCU input / output signal comparison circuit 16 detects a change in the MCU input / output signal 4.
That is, the immediately preceding recording data latch signal 15 and the new MCU
This is a comparison result mismatch signal output when a mismatch with the input / output signal 4 is detected.

Reference numeral 18 calculates the logical product of the comparison result mismatch signal 17 and the write permission signal 12 output from the sampling trace condition judging means 9, and passes the write permission signal 12 until a change in the MCU input / output signal 4 is detected. It is a gate circuit as a write blocking means for blocking. Reference numeral 19 denotes a write enable signal that has passed through the gate circuit 18, and is input to the MCU input / output signal trace memory 5 and the time data trace memory 8 to write the MCU input / output signal 4 or the time data 7, and The MCU input / output signal 4 input to the immediately preceding recording data latch circuit 14 and recorded in the MCU input / output signal trace memory 5 at that time is also used as the immediately preceding recording data latch circuit 14.
To hold.

Next, the operation will be described. Also in this embodiment, as in the conventional case, the time data 7 constantly generated by the time data generation circuit 6 is input to the time data trace memory 8 and the M data from within the MCU application system 1 is transmitted.
The CU input / output signal 4 is input to the MCU input / output signal trace memory 5 and the sampling trace circuit 9. In this embodiment, the MCU input / output signal 4 is also input to the MCU input / output signal comparison circuit 16.

The immediately preceding recording data latch circuit 14 is M
The MCU input / output signal 4 last recorded in the CU input / output signal trace memory 5 is held and is always output as the immediately preceding recording data latch signal 15. The immediately preceding recording data latch signal 15 is the MCU input / output signal. It is input to the comparison circuit 16. The MCU input / output signal comparison circuit 16 compares the immediately preceding recording data latch signal 15 with the newly sent MCU input / output signal 4 and they do not match, that is, if there is a change in the MCU input / output signal 4, the comparison result does not match. The signal 17 is output.

On the other hand, in the sampling trace circuit 9, M
The MCU input / output signal 4 from the MCU application system 1 once stored in the CU input / output signal storage unit 10 is constantly compared with the contents of the sampling trace condition storage unit 11. When the contents of the MCU input / output signal storage unit 10 and the sampling trace condition storage unit 11 match, the sampling trace circuit 9 outputs the memory address 13 to the MCU input / output signal trace memory 5 and the time data trace memory 8. , Write enable signal 12 to gate circuit 1
Output to 8.

The gate circuit 18 uses the write enable signal 1
2 and the comparison result disagreement signal 17 from the MCU input / output signal comparison circuit 16 are ANDed, and the input write enable signal 12 is passed as the write enable signal 19 only when the comparison result disagreement signal 17 is generated. Let Therefore, the MCU input / output signal trace memory 5, the time data trace memory 8 and the immediately preceding recording data latch circuit 1
4, the write enable signal 19 is input only when the comparison result mismatch signal 17 is output from the MCU input / output signal comparison circuit 16.

When the write enable signal 19 is received, M
The CU input / output signal trace memory 5 receives the MCU input / output signal 4 sent from the MCU application system 1 as a write memory address 13 from the sampling trace circuit 9.
The time data trace memory 8 records the time data 7 generated by the time data generation circuit 6 at that time in the area specified by the write memory address 13. Upon receiving the write enable signal 19, the immediately preceding recording data latch circuit 14 updates the contents to the MCU input / output signal 4 newly recorded in the MCU input / output signal trace memory 5.

As a result, the MCU input / output signal 4 and the time data 7 are recorded in the MCU input / output signal trace memory 5 and the time data trace memory 8 only when the following conditions are satisfied. If there is no change in 4, the recording is not done. -MCU input / output signal storage area 10 and sampling trace condition storage section 11 contents match-Previous recording data latch signal 15 and input / output signal 4 mismatch

In the above embodiment, the sampling trace circuit 9 is provided only when the contents of the MCU input / output signal storage unit 10 and the sampling trace condition storage unit 11 match.
Although the case where the write permission signal 12 is generated has been described above, when the contents of the MCU input / output signal storage unit 10 and the sampling trace condition storage unit 11 do not match, or the comparison result of the specific bit or the comparison result of the magnitude relationship, etc. The write enable signal 12 may be generated based on the above.

[0023]

As described above, according to the present invention, it is determined whether the input trace data matches the trace data recorded immediately before, and only when the trace data does not match,
Since the trace data that satisfies the sampling trace conditions is recorded in the trace memory and the time data at that time is recorded in the trace memory for time data, unnecessary and unchanged data can be recorded in the trace memory. The effect is that the data transition corresponding to the trace memory capacity can be referred to, and the time interval at the time of data transition can also be referred to.

[Brief description of drawings]

FIG. 1 is a block diagram showing a sampling trace circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional sampling trace circuit.

[Explanation of symbols]

1 MCU application system, 2 MCU, 4 MCU input / output signal (trace data), 5 MCU input / output signal trace memory (trace memory), 7 time data, 8
Time data trace memory, 9 sampling trace circuit (determination means), 12, 19 write permission signal, 16 MCU input / output signal comparison circuit (change detection means), 18 gate circuit (write blocking means).

Claims (1)

[Claims] 1. A determination means for determining whether or not trace data input / output by a microcomputer in a microcomputer application system is input, and the trace data satisfies a certain sampling trace condition, and the sampling trace. A trace memory that records the trace data according to the write permission signal output from the determination unit when the conditions are satisfied, and a time data that records time data according to the write permission signal output from the determination unit. In a sampling trace circuit including a trace memory for use, change detection means for detecting a change in the trace data, and write permission output from the determination means until a change in the trace data is detected by the change detection means. Signal of
A sampling trace circuit, which is provided with write blocking means for blocking input to the trace memory and the time data trace memory.