JPH08297301A - Liquid crystal display device - Google Patents

Liquid crystal display device

Info

Publication number
JPH08297301A
JPH08297301A JP3462996A JP3462996A JPH08297301A JP H08297301 A JPH08297301 A JP H08297301A JP 3462996 A JP3462996 A JP 3462996A JP 3462996 A JP3462996 A JP 3462996A JP H08297301 A JPH08297301 A JP H08297301A
Authority
JP
Japan
Prior art keywords
electrode
liquid crystal
wiring
drain
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3462996A
Other languages
Japanese (ja)
Inventor
Masaatsu Ito
正厚 伊藤
Susumu Oi
進 大井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3462996A priority Critical patent/JPH08297301A/en
Publication of JPH08297301A publication Critical patent/JPH08297301A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE: To decrease disclinations and to improve the opening rate of a liquid crystal display device. CONSTITUTION: Drain wirings functioning as signal lines are obtd. by forming first drain wirings 3 formed at the same layer as the layer of gate wirings 1 in regions not intersecting the gate wirings 1 functioning as scanning lines and forming second drain wirings 4a formed at the same layer as the layer of drain electrodes 4 in regions intersecting the gate wirings 1. The first drain wirings 3 and the second drain wirings 4a are electrically connected via through- holes 6. Transparent pixel electrodes 8 are formed on the upper layer above the drain wirings 3, thereby, the transverse direction electric fields occurring by the drain wirings 3 are decreased, the reverse tilt regions by the transverse direction electric fields are narrowed, the advance of the disclinations into the pixel electrodes is suppressed and the opening rate is improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は液晶表示装置、特に
薄膜トランジスタをスイッチング素子として用いるアク
ティブマトリックス型液晶表示装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an active matrix type liquid crystal display device using thin film transistors as switching elements.

【0002】[0002]

【従来の技術】薄膜トランジスタ(以下TFTと記す)
駆動のアクティブマトリックス型液晶表示装置(以下L
CDと記す)には、逆スタガ(またはボトムゲート型)
構造のTFTが一般的に用いられている。
2. Description of the Related Art Thin film transistor (hereinafter referred to as TFT)
Driven active matrix liquid crystal display device (hereinafter L
Reverse stagger (or bottom gate type) for CD)
A structured TFT is generally used.

【0003】図5(a)は従来の液晶表示装置の一例を
示す平面図、図5(b)は図5(a)のA−A′線断面
図、図5(c)は図5(a)のB−B′線断面図であ
る。
FIG. 5A is a plan view showing an example of a conventional liquid crystal display device, FIG. 5B is a sectional view taken along the line AA 'of FIG. 5A, and FIG. It is a BB 'sectional view taken on the line a).

【0004】図5(a),(b),(c)に示すよう
に、透明絶縁基板12の上に形成したゲート電極2およ
びゲート電極2に接続したゲート配線1と、絶縁膜10
を介してゲート電極2の上に形成した半導体薄膜5と、
半導体薄膜5に接続して設けたドレイン電極4およびソ
ース電極7と、ドレイン電極4と一体化して形成し且つ
絶縁膜10を介してゲート配線1と交差するドレイン配
線3と、ソース電極7に接続して形成した透明画素電極
8とを有して構成される。
As shown in FIGS. 5A, 5B and 5C, a gate electrode 2 formed on a transparent insulating substrate 12, a gate wiring 1 connected to the gate electrode 2 and an insulating film 10 are formed.
A semiconductor thin film 5 formed on the gate electrode 2 via
The drain electrode 4 and the source electrode 7 connected to the semiconductor thin film 5, the drain wiring 3 formed integrally with the drain electrode 4 and intersecting the gate wiring 1 through the insulating film 10 and the source electrode 7 are connected. And the transparent pixel electrode 8 formed in this way.

【0005】[0005]

【発明が解決しようとする課題】この従来のLCDで
は、透明画素電極とドレイン配線は同層に形成されてい
るために、透明画素電極とドレイン配線間に横方向電界
(TFT基板上の画素電極と対向電極間で液晶に電圧を
印加する方向を縦方向と定義)が生じる。この電界は画
素電極とドレイン配線の間隔を狭くする必要がある高精
細ディスプレイほど強くなる。通常、電圧印加時の液晶
は配向膜のラビング方向に誘起されるプレチルト方向に
立ち上がるが、プレチルト方向と逆方向に前述の強い横
方向電界が存在すると、液晶はこの電界方向に配向す
る。この結果、逆方向電界の強い領域では、液晶は通常
とは逆方向に立ち上がる(リバースチルト状態)。この
リバースチルトが形成されると、図2に示すように、通
常のチルト(ノーマルチルト状態)領域との境界にディ
スクリネーションと呼ばれる配向の遷移領域が発生す
る。このディスクリネーション領域は、ノーマリブラッ
クのLCDの黒表示の際には光を透過してしまい、表示
コントラストの低下をもたらす。
In this conventional LCD, since the transparent pixel electrode and the drain wiring are formed in the same layer, a lateral electric field (pixel electrode on the TFT substrate is formed between the transparent pixel electrode and the drain wiring). And the direction in which a voltage is applied to the liquid crystal between the opposite electrodes is defined as the vertical direction). This electric field becomes stronger in a high-definition display in which it is necessary to narrow the gap between the pixel electrode and the drain wiring. Normally, when a voltage is applied, the liquid crystal rises in the pretilt direction induced in the rubbing direction of the alignment film, but when the above-mentioned strong lateral electric field exists in the direction opposite to the pretilt direction, the liquid crystal is aligned in this electric field direction. As a result, in a region where the reverse electric field is strong, the liquid crystal rises in the direction opposite to the normal direction (reverse tilt state). When this reverse tilt is formed, as shown in FIG. 2, an alignment transition region called disclination occurs at the boundary with the normal tilt (normal tilt state) region. This disclination region transmits light during black display on a normally black LCD, resulting in a reduction in display contrast.

【0006】このディスクリネーション領域を遮蔽する
ため、従来はTFTと対向するカラーフィルタ基板上に
形成されたクロム金属層などからなるブラックマトリッ
クス(以降BMと記す)層が形成されていた。この対向
基板上のBM層は、対向基板とTFTとの重ね合わせ精
度の制約から、ディスクリネーション領域を遮光するた
めに画素電極とかなりの幅の重ね合わせマージンをもっ
て形成されている。そのためBM層の開口面積比率(開
口率)は下がり、表示輝度低下、あるいはそれを補うた
めにLCDの消費電力の増大をもたらすといった問題が
ある。また、前述の横方向電界が強いとディスクリネー
ションが画素電極内部まで深く進入するので、それを遮
蔽するためにBM領域を広くとらなければならないの
で、開口率のいっそうの低下を招くという問題がある。
In order to shield the disclination region, a black matrix (hereinafter referred to as BM) layer formed of a chromium metal layer or the like formed on a color filter substrate facing the TFT has been conventionally formed. The BM layer on the counter substrate is formed with a considerable overlapping margin with the pixel electrode in order to shield the disclination region from the light due to the restriction of the overlay accuracy of the counter substrate and the TFT. Therefore, there is a problem that the aperture area ratio (aperture ratio) of the BM layer is lowered, and the display brightness is lowered, or the power consumption of the LCD is increased to compensate for it. In addition, since the disclination deeply penetrates into the pixel electrode when the lateral electric field is strong, the BM region must be wide to shield the disclination, which causes a problem that the aperture ratio is further reduced. is there.

【0007】本発明の目的は、ディスクリネーションの
画素電極内の進入を抑制して、開口率を向上させた液晶
表示装置を提供することにある。
An object of the present invention is to provide a liquid crystal display device in which disclination is prevented from entering the pixel electrode and the aperture ratio is improved.

【0008】[0008]

【課題を解決するための手段】本発明の液体表示装置
は、透明絶縁基板上に配置したゲート電極に接続し且つ
前記ゲート電極と同じ層に形成したゲート配線と、前記
ゲート電極を含む表面に形成した絶縁膜を介して前記ゲ
ート電極上に配置した半導体薄膜、ソース電極、ドレイ
ン電極のそれぞれを有する逆スタガー構造の薄膜トラン
ジスタと、前記ソース電極に接続した透明画素電極とを
含んで構成されるアクティブマトリックス型の液晶表示
装置において、前記ドレイン電極に接続して前記ゲート
配線と交差するドレイン配線が前記ゲート配線と交差す
る領域以外の前記透明画素電極の周縁部と近接する領域
で前記ゲート配線と同じ層に配置した第1のドレイン配
線と、前記ゲート配線と交差する領域で前記ドレイン電
極と同じ層に配置され且つ前記絶縁膜に設けたスルーホ
ールを介して前記第1のドレイン配線と接続した第2の
ドレイン配線とを有する。
According to another aspect of the present invention, there is provided a liquid crystal display device, comprising: a gate wiring connected to a gate electrode arranged on a transparent insulating substrate and formed in the same layer as the gate electrode; and a surface including the gate electrode. An active structure including a thin film transistor having an inverted staggered structure having a semiconductor thin film, a source electrode, and a drain electrode arranged on the gate electrode via the formed insulating film, and a transparent pixel electrode connected to the source electrode. In the matrix type liquid crystal display device, the drain wiring which is connected to the drain electrode and intersects with the gate wiring is the same as the gate wiring in a region close to a peripheral portion of the transparent pixel electrode except a region intersecting with the gate wiring. The first drain wiring arranged in a layer and the drain electrode in the same layer as the drain electrode in a region intersecting with the gate wiring. And and a second drain wiring via a through hole provided in the insulating film connected to the first drain wire.

【0009】[0009]

【発明の実施の形態】本発明では、透明画素電極と隣接
するドレイン配線をゲート配線と同層に形成して透明画
素電極をドレイン配線層より上層に配置することで、ド
レイン配線に起因する横方向電界を軽減し、その結果横
方向電界によるリバースチルト領域は狭くなり、ディス
クリネーションの画素電極内への進入が抑制される。
BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, the drain wiring adjacent to the transparent pixel electrode is formed in the same layer as the gate wiring, and the transparent pixel electrode is arranged above the drain wiring layer. The directional electric field is reduced, and as a result, the reverse tilt region due to the lateral electric field is narrowed, and the disclination is prevented from entering the pixel electrode.

【0010】また、画素電極の端とドレイン配線とを重
ねることにより、ドレイン配線をCr、Ta、Alなど
の遮光性の金属で形成すれば遮光膜としても機能するの
で、対向基板のBMはその領域では不要となり、従来の
完全対向膜遮光方式に比べ開口率を向上させることがで
きる。
If the drain wiring is formed of a light-shielding metal such as Cr, Ta, or Al by overlapping the end of the pixel electrode and the drain wiring, it also functions as a light-shielding film. It becomes unnecessary in the area, and the aperture ratio can be improved as compared with the conventional completely opposed film light-shielding method.

【0011】次に、本発明の実施の形態について図面を
参照して説明する。
Next, an embodiment of the present invention will be described with reference to the drawings.

【0012】図1(a)は本発明の第1の実施の形態例
を示す平面図、図1(b)は図1(a)のC−C′線断
面図、図1(c)は図1(a)のD−D′線断面図、図
1(d)は図1(a)のE−E′線断面図である。
FIG. 1A is a plan view showing a first embodiment of the present invention, FIG. 1B is a sectional view taken along the line CC ′ of FIG. 1A, and FIG. 1A is a cross-sectional view taken along the line DD ′, and FIG. 1D is a cross-sectional view taken along the line EE ′ of FIG.

【0013】図1(a)〜(d)に示すように、透明絶
縁基板12上にスパッタ法でCr膜を堆積してパターニ
ングし、ゲート電極2および各ゲート電極2に接続し且
つ付加容量素子9の下部電極を備えるゲート配線1と、
ドレイン配線3とをそれぞれ形成する。次に、これらの
各電極を含む全面にCVD法で窒化シリコン(Si
X )膜からなる絶縁膜10を堆積した後絶縁膜10の
上にアモルファスシリコン(a−Si)膜を堆積してパ
ターニングしゲート電極2の上の絶縁膜10の上に半導
体薄膜5を形成する。次に、絶縁膜10を選択的にエッ
チングしてドレイン配線3上にスルーホール6を形成す
る。
As shown in FIGS. 1A to 1D, a Cr film is deposited on the transparent insulating substrate 12 by a sputtering method and patterned, and the gate electrode 2 and each of the gate electrodes 2 are connected to the additional capacitance element. A gate wiring 1 having 9 lower electrodes;
The drain wiring 3 is formed respectively. Next, the silicon nitride (Si
N X) forming a semiconductor thin film 5 on the amorphous silicon (a-Si) film is deposited and patterned insulating film 10 above the gate electrode 2 on the insulating film 10 after depositing an insulating film 10 made of film To do. Next, the insulating film 10 is selectively etched to form the through hole 6 on the drain wiring 3.

【0014】次に、半導体薄膜5およびスルーホール6
を含む表面にスパッタ法でCr膜を堆積してパターニン
グし、スルーホール6を介して下層のドレイン配線3と
接続するドレイン電極4、スルーホール6を介してドレ
イン配線3と接続し且つ下層のゲート配線1上を跨ぎド
レイン電極4に接続する上層のドレイン配線4aと、ソ
ース電極7のそれぞれを形成する。次に、スパッタ法で
堆積した酸化インジウム錫(ITO)膜を選択的にエッ
チングしてソース電極7に接続した透明画素電極8を形
成し、同時に付加容量素子9を形成する。次に全面に窒
化シリコン膜を堆積して保護膜11を形成する。
Next, the semiconductor thin film 5 and the through hole 6
A Cr film is deposited on the surface including the silicon by a sputtering method and patterned, and the drain electrode 4 connected to the drain wiring 3 in the lower layer through the through hole 6 and the drain wiring 3 connected through the through hole 6 and the gate in the lower layer An upper-layer drain wiring 4a connected to the drain electrode 4 over the wiring 1 and a source electrode 7 are formed. Next, the indium tin oxide (ITO) film deposited by the sputtering method is selectively etched to form the transparent pixel electrode 8 connected to the source electrode 7, and at the same time, the additional capacitance element 9 is formed. Next, a silicon nitride film is deposited on the entire surface to form a protective film 11.

【0015】図2は本実施の形態例により形成した液晶
表示装置のドレイン配線と透明画素電極間に生じる電気
力線と液晶の配向を示す模式図である。
FIG. 2 is a schematic diagram showing the lines of electric force generated between the drain wiring and the transparent pixel electrode of the liquid crystal display device formed according to this embodiment and the alignment of the liquid crystal.

【0016】図2に示すように、電気力線14は図6の
従来例と比較して、横方向電界が軽減され、液晶の配向
は、対向電極と画素電極間の縦方向電界が強く影響する
ようになる。その結果、リバースチルト領域17は狭く
なり、ディスクリネーションライン16の範囲が狭くな
る。
As shown in FIG. 2, the lines of electric force 14 reduce the lateral electric field as compared with the conventional example of FIG. 6, and the liquid crystal alignment is strongly affected by the vertical electric field between the counter electrode and the pixel electrode. Come to do. As a result, the reverse tilt region 17 becomes narrower and the range of the disclination line 16 becomes narrower.

【0017】液晶シミュレーションプログラムにより、
本実施例の液晶装置と、従来の液晶装置の液晶の配向を
シミュレートした結果をそれぞれ図3、図7に示す。こ
のとき対向電極、透明画素電極、ドレイン配線の電位は
それぞれ9V,14V,4Vである。図7の従来例に比
較して、図3の本実施例の方がリバースチルト領域が狭
く、ドレイン配線の端から透明画素電極に進入したディ
スクリネーションラインの距離は、従来例が5.1μm
であるのに対して、本実施例では3.8μmとなり1.
8μm短くなっている。このように本発明の方がディス
クリネーションの画素電極内への進入抑制の効果が大き
いといえる。
According to the liquid crystal simulation program,
The results of simulating the alignment of the liquid crystals of the liquid crystal device of this example and the conventional liquid crystal device are shown in FIGS. 3 and 7, respectively. At this time, the potentials of the counter electrode, the transparent pixel electrode and the drain wiring are 9V, 14V and 4V, respectively. As compared with the conventional example of FIG. 7, the reverse tilt region of the present example of FIG. 3 is narrower, and the distance of the disclination line entering the transparent pixel electrode from the end of the drain wiring is 5.1 μm in the conventional example.
On the other hand, in the present embodiment, it becomes 3.8 μm.
8 μm shorter. Thus, it can be said that the present invention is more effective in suppressing the invasion of disclination into the pixel electrode.

【0018】図4(a)は本発明の第2の実施の形態例
を示す平面図、図4(b)は図4(a)のF−F′線拡
大断面図である。
FIG. 4A is a plan view showing a second embodiment of the present invention, and FIG. 4B is an enlarged sectional view taken along the line FF 'of FIG. 4A.

【0019】図4(a),(b)に示すように、透明画
素電極8の周辺の一部をドレイン配線3の上に重ねて形
成し、ドレイン配線を遮光性の金属で形成した以外は第
1の実施例と同様の構成を有しており、この部分の対向
基板のカラーフィルターに設けたディスクリネーション
を遮光するためのBMを省略できる利点がある。この対
向基板上のBM層は、対向基板とTFT基板の重ね合わ
せ精度の制約から大きな重ねマージンをもって形成され
ているが、透明画素電極の端とドレイン配線を重ねるこ
とにより、ドレイン配線が遮光層としても機能するの
で、対向基板のBMはその領域では不要となり、従来よ
りも開口率を向上させることができる。
As shown in FIGS. 4A and 4B, except that a part of the periphery of the transparent pixel electrode 8 is formed on the drain wiring 3 and the drain wiring is made of a light-shielding metal. The structure is similar to that of the first embodiment, and there is an advantage that the BM for shielding the disclination provided in the color filter of the counter substrate in this portion can be omitted. The BM layer on the counter substrate is formed with a large stacking margin due to the constraint of the stacking accuracy of the counter substrate and the TFT substrate. However, by overlapping the end of the transparent pixel electrode and the drain wiring, the drain wiring serves as a light shielding layer. Also, since the BM of the counter substrate is not necessary in that region, the aperture ratio can be improved more than in the past.

【0020】[0020]

【発明の効果】以上説明したように本発明は、透明画素
電極に近接する領域のドレイン配線を絶縁膜の下のゲー
ト配線と同じ層に配置し、ゲート配線と交差する領域の
ドレイン配線をドレイン電極と同じ層に配置してゲート
配線上を跨ぐことにより、ディスクリネーションの画素
電極進入の抑制をする事ができる。また、ドレイン配線
と透明画素電極を重なるように形成することでディスク
リネーションをドレイン配線で遮蔽することでその部分
のBMを省略することができ、透明画素電極の面積が大
きくなるため開口率を大きくできるという効果を有す
る。
As described above, according to the present invention, the drain wiring in the region close to the transparent pixel electrode is arranged in the same layer as the gate wiring under the insulating film, and the drain wiring in the region intersecting the gate wiring is drained. It is possible to suppress the disclination from entering the pixel electrode by disposing it in the same layer as the electrode and straddling the gate wiring. Further, by forming the drain wiring and the transparent pixel electrode so as to overlap with each other, the disclination is shielded by the drain wiring, so that the BM in that portion can be omitted, and the area of the transparent pixel electrode becomes large, so that the aperture ratio is increased. It has the effect of increasing the size.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1(a)は本発明の第1の形態例を示す平面
図であり、図1(b)は図1(a)におけるC−C′線
断面図、図1(c)は図1(a)におけるD−D′線断
面図、図1(d)は図1(a)におけるE−E′線断面
図である。
1 (a) is a plan view showing a first embodiment of the present invention, FIG. 1 (b) is a sectional view taken along the line CC ′ in FIG. 1 (a), and FIG. 1 (c). 1A is a sectional view taken along the line DD ′ in FIG. 1A, and FIG. 1D is a sectional view taken along the line EE ′ in FIG.

【図2】本発明の第1の実施の形態例のドレイン配線と
透明画素電極間に生じる電気力線と液晶分子の配向を示
す模式図である。
FIG. 2 is a schematic view showing lines of electric force generated between the drain wiring and the transparent pixel electrode and alignment of liquid crystal molecules according to the first embodiment of the present invention.

【図3】本発明の第1の実施の形態例の液晶装置の液晶
分子の配向をシミュレートした結果を示す模式図であ
る。
FIG. 3 is a schematic diagram showing a result of simulating the alignment of liquid crystal molecules in the liquid crystal device according to the first embodiment of the present invention.

【図4】図4(a)は本発明の第2の実施の形態例を示
す平面図であり、図4(b)は図4(a)におけるF−
F′線断面図。
4 (a) is a plan view showing a second embodiment of the present invention, and FIG. 4 (b) is an F- line in FIG. 4 (a).
F'line sectional drawing.

【図5】図5(a)は従来の液晶表示装置を示す平面図
であり、図5(b)は図5(a)におけるA−A′線断
面図、図5(c)は図5(a)におけるB−B′線断面
図である。
5A is a plan view showing a conventional liquid crystal display device, FIG. 5B is a sectional view taken along the line AA ′ in FIG. 5A, and FIG. It is a BB 'sectional view taken on the line in (a).

【図6】従来例のドレイン配線と透明画素電極間に生じ
る電気力線と液晶分子の配向を示す模式図である。
FIG. 6 is a schematic diagram showing lines of electric force generated between a drain wiring and a transparent pixel electrode and alignment of liquid crystal molecules in a conventional example.

【図7】従来の液晶装置の液晶分子の配向をシミュレー
トした結果を示す模式図である。
FIG. 7 is a schematic diagram showing a result of simulating the alignment of liquid crystal molecules in a conventional liquid crystal device.

【符号の説明】[Explanation of symbols]

1 ゲート配線 2 ゲート電極 3,4a ドレイン配線 4 ドレイン電極 5 半導体薄膜 6 スルーホール 7 ソース電極 8 透明画素電極 9 付加容量素子 10 絶縁膜 11 保護膜 12 透明絶縁基板 13 液晶分子 14 電気力線 15 ラビング方向 16 ディスクリネーションライン 17 リバースチルト領域 18 対向電極 19 対向基板 20 ブラックマトリックス層 21 カラーフィルタ DESCRIPTION OF SYMBOLS 1 gate wiring 2 gate electrode 3,4a drain wiring 4 drain electrode 5 semiconductor thin film 6 through hole 7 source electrode 8 transparent pixel electrode 9 additional capacitance element 10 insulating film 11 protective film 12 transparent insulating substrate 13 liquid crystal molecule 14 electric force line 15 rubbing Direction 16 Disclination line 17 Reverse tilt area 18 Counter electrode 19 Counter substrate 20 Black matrix layer 21 Color filter

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 透明絶縁基板上に配置したゲート電極に
接続し且つ前記ゲート電極と同じ層に形成したゲート配
線と、前記ゲート電極を含む表面に形成した絶縁膜を介
して前記ゲート電極上に配置した半導体薄膜、ソース電
極、ドレイン電極のそれぞれを有する逆スタガー構造の
薄膜トランジスタと、前記ソース電極に接続した透明画
素電極とを含んで構成されるアクティブマトリックス型
の液晶表示装置において、前記ドレイン電極に接続して
前記ゲート配線と交差するドレイン配線が前記ゲート配
線と交差する領域以外の前記透明画素電極の周縁部と近
接する領域で前記ゲート配線と同じ層に配置した第1の
ドレイン配線と、前記ゲート配線と交差する領域で前記
ドレイン電極と同じ層に配置され且つ前記絶縁膜に設け
たスルーホールを介して前記第1のドレイン配線と接続
した第2のドレイン配線とを有することを特徴とする液
晶表示装置。
1. A gate wiring connected to a gate electrode arranged on a transparent insulating substrate and formed in the same layer as the gate electrode, and an insulating film formed on a surface including the gate electrode, on the gate electrode. In an active matrix type liquid crystal display device including an inverted staggered thin film transistor having a semiconductor thin film arranged, a source electrode and a drain electrode, and a transparent pixel electrode connected to the source electrode, in the drain electrode A first drain wiring arranged in the same layer as the gate wiring in a region adjacent to a peripheral portion of the transparent pixel electrode other than a region in which a drain wiring connected to intersect the gate wiring intersects the gate wiring; Via a through hole provided in the insulating film in the same layer as the drain electrode in a region intersecting with the gate wiring. And a second drain wiring connected to the first drain wiring.
【請求項2】 第1のドレイン配線の上に絶縁膜を介し
て透明画素電極の周縁部を重ねて形成した請求項1記載
の液晶表示装置。
2. The liquid crystal display device according to claim 1, wherein the peripheral portion of the transparent pixel electrode is formed on the first drain wiring with an insulating film interposed therebetween.
【請求項3】 透明基板上にゲート電極、ドレイン配線
及び前記ゲート電極に接続されたゲート配線を有し、前
記ゲート電極、前記ゲート配線及び前記ドレイン配線上
に絶縁膜を有し、前記絶縁膜上に前記ゲート電極上に配
置された半導体薄膜を有し、前記絶縁膜上に前記半導体
薄膜と接続されたソース電極とドレイン電極を有し、前
記絶縁膜上に前記ソース電極と接続された透明画素電極
を有し、前記ドレイン電極はコンタクトホールを介して
前記ドレイン配線と接続され、表面に透明電極を有する
対向基板と前記透明基板とで液晶を挟持することを特徴
とする液晶表示装置。
3. A gate electrode, a drain wiring, and a gate wiring connected to the gate electrode are provided on a transparent substrate, and an insulating film is provided on the gate electrode, the gate wiring, and the drain wiring. A semiconductor thin film disposed on the gate electrode, a source electrode and a drain electrode connected to the semiconductor thin film on the insulating film, and a transparent thin film connected to the source electrode on the insulating film. A liquid crystal display device comprising a pixel electrode, the drain electrode being connected to the drain wiring through a contact hole, and a liquid crystal being sandwiched between a counter substrate having a transparent electrode on a surface thereof and the transparent substrate.
【請求項4】 前記ドレイン配線は遮光性の金属からな
ることを特徴とする請求項3に記載の液晶表示装置。
4. The liquid crystal display device according to claim 3, wherein the drain wiring is made of a light-shielding metal.
【請求項5】 前記ドレイン配線は、前記絶縁膜を介し
て前記透明画素電極と一部重なっていることを特徴とす
る請求項4記載の液晶表示装置。
5. The liquid crystal display device according to claim 4, wherein the drain wiring partly overlaps the transparent pixel electrode via the insulating film.
【請求項6】 前記ドレイン配線の幅は片側が前記絶縁
膜を介して、前記透明画素電極と重なり、他の側が前記
絶縁膜を介して他の透明画素電極の前記ドレイン配線側
の端部まで有るように設定されていることを特徴とする
請求項4記載の液晶表示装置。
6. The width of the drain wiring is overlapped on one side with the transparent pixel electrode through the insulating film, and on the other side through the insulating film to an end portion of the other transparent pixel electrode on the drain wiring side. The liquid crystal display device according to claim 4, wherein the liquid crystal display device is set to be present.
【請求項7】 第1の透明基板上にスイッチング素子
と、前記スイッチング素子の第1の電極に接続された配
線と、絶縁膜と、前記スイッチング素子の第2の電極に
接続された透明画素電極とを有し、対向電極を有する第
2の透明基板と前記第1の透明基板とで液晶を挟持する
液晶表示装置において、前記透明画素電極は前記絶縁膜
上に有り、前記配線は前記透明画素電極と隣接する領域
において前記絶縁膜の下に有ることを特徴とする液晶表
示装置。
7. A switching element, a wiring connected to a first electrode of the switching element, an insulating film, and a transparent pixel electrode connected to a second electrode of the switching element on a first transparent substrate. A liquid crystal display device in which a liquid crystal is sandwiched between a second transparent substrate having a counter electrode and a first transparent substrate, and the transparent pixel electrode is on the insulating film, and the wiring is the transparent pixel. A liquid crystal display device, which is below the insulating film in a region adjacent to an electrode.
【請求項8】 前記配線は遮光性の金属からなることを
特徴とする請求項7記載の液晶表示装置。
8. The liquid crystal display device according to claim 7, wherein the wiring is made of a light-shielding metal.
【請求項9】 前記配線は、前記絶縁膜を介して前記透
明画素電極と一部重なっていることを特徴とする請求項
8記載の液晶表示装置。
9. The liquid crystal display device according to claim 8, wherein the wiring partially overlaps the transparent pixel electrode with the insulating film interposed therebetween.
【請求項10】 前記配線の幅は、片側が前記絶縁膜を
介して、前記透明画素電極と重なり、他の側が前記絶縁
膜を介して他の透明画素電極の前記ドレイン配線側の端
部まで有るように設定されていることを特徴とする請求
項8記載の液晶表示装置。
10. The width of the wiring is such that one side overlaps with the transparent pixel electrode via the insulating film, and the other side extends to the end of the other transparent pixel electrode on the drain wiring side via the insulating film. 9. The liquid crystal display device according to claim 8, wherein the liquid crystal display device is set to be present.
JP3462996A 1995-02-28 1996-02-22 Liquid crystal display device Pending JPH08297301A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3462996A JPH08297301A (en) 1995-02-28 1996-02-22 Liquid crystal display device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP7-40224 1995-02-28
JP4022495 1995-02-28
JP3462996A JPH08297301A (en) 1995-02-28 1996-02-22 Liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH08297301A true JPH08297301A (en) 1996-11-12

Family

ID=26373455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3462996A Pending JPH08297301A (en) 1995-02-28 1996-02-22 Liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH08297301A (en)

Cited By (5)

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Publication number Priority date Publication date Assignee Title
JP2008304951A (en) * 2002-12-27 2008-12-18 Sharp Corp Display device substrate and liquid crystal display device having same
US8605016B2 (en) 2002-12-27 2013-12-10 Sharp Kabushiki Kaisha Display device substrate and liquid crystal display device having the same
JP2014123137A (en) * 2000-08-14 2014-07-03 Semiconductor Energy Lab Co Ltd Display device
JP2014167641A (en) * 2010-02-05 2014-09-11 Semiconductor Energy Lab Co Ltd Display device
JP2020064287A (en) * 2018-10-16 2020-04-23 群創光電股▲ふん▼有限公司Innolux Corporation Electronic modulating device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014123137A (en) * 2000-08-14 2014-07-03 Semiconductor Energy Lab Co Ltd Display device
JP2008304951A (en) * 2002-12-27 2008-12-18 Sharp Corp Display device substrate and liquid crystal display device having same
US8605016B2 (en) 2002-12-27 2013-12-10 Sharp Kabushiki Kaisha Display device substrate and liquid crystal display device having the same
JP2014167641A (en) * 2010-02-05 2014-09-11 Semiconductor Energy Lab Co Ltd Display device
US9057918B2 (en) 2010-02-05 2015-06-16 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device comprising first and second pixel electrodes that overlap each other with an insulating layer interposed therebetween
US9541803B2 (en) 2010-02-05 2017-01-10 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device comprising first and second reflective pixel electrodes that overlap each other with an insulating layer having a tapered first end portion interposed therebetween
JP2020064287A (en) * 2018-10-16 2020-04-23 群創光電股▲ふん▼有限公司Innolux Corporation Electronic modulating device
US11876104B2 (en) 2018-10-16 2024-01-16 Nnolux Corporation Electronic modulating device

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