JPH08292366A - Sensor controller for focus detection - Google Patents

Abstract

PURPOSE: To provide a sensor controller for focus detection with which clock speed during an operation can be varied or switched synchronously with control timing. CONSTITUTION: This device is provided with an AF sensor unit equipped with a CCD transfer part 303 for independently stepwise and serially transferring electric charges stored in 1st, 2nd and 3rd sensor 304A, 304B and 304C, which is provided with plural photoreceptor elements for storing the electric charges by receiving object light and photoelectrically converting it, corresponding transfer/read clocks ϕ1 and ϕ2 and for outputting those electric charges for the unit of a photoreceptor element, CPU 11 for outputting a fixed basic clock ϕM, and timing generation/driver circuit 33 for generating 1st and 2nd basic clocks ϕM0 and ϕM1 at different speed and the correspondent transfer/read clocks ϕ1 and ϕ2 synchronously with the basic clock ϕM, and the CPU 11 switches the 1st and 2nd basic clocks ϕM0 and ϕM1 so that the transfer/read clocks ϕ1 and ϕ2 for driving the AF sensor unit can be turned to high speed when reading unwanted charges but can be turned to low speed when reading signal charges.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sensor control device, and more specifically, it can control the clock speed of a focus detection sensor of a camera which sequentially transfers a plurality of pixel signals of a line sensor which receives subject light. Regarding the control device.

[0002]

2. Description of the Related Art Conventionally, a phase-difference-type CCD image sensor for focus detection used in a single-lens reflex camera or the like has at least a pair of light receiving regions, and each light receiving region is arranged in a line. Multiple pixels (light receiving element)
It has. The signal charges accumulated by these pixels are transferred to one transfer section, serially transferred in stages through this transfer section, and read out pixel by pixel. This transfer is performed by a read clock (pulse signal) which is synchronized with the supply clock, but during one control, the read clock is one and constant with respect to the supply clock. For example, when sweeping out as unnecessary charges from the transfer unit, driving is performed by a high-speed read clock, and when reading out as signal charges, driving is performed by a low-speed read clock, and the high-speed and low-speed read clocks are one and constant.
Therefore, even if there is an unnecessary charge group in the middle of the signal charges that are serially read, they are also swept out by the low-speed read clock. However, it is difficult to change the read clock by changing the supply clock because the control timing and the read clock are not synchronized during sensor control.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems of the conventional AF sensor control device, and a focus detection sensor control capable of variably or switching the operating clock speed in synchronization with the control timing. It is intended to provide a device.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in the AF sensor processing provided with a line sensor, paying attention to the fact that the readout time can be shortened if unnecessary charges can be swept out by a high-speed clock during signal charge readout. It is a thing. The present invention, which has been made based on this point of view, transfers / reads out a light receiving unit including a plurality of light receiving means for receiving subject light, photoelectrically converting the light, and accumulating the electric charges, and the electric charges accumulated by the respective light receiving means. A line sensor having a transfer unit that transfers and outputs in stages by a clock, a clock unit that outputs a constant basic clock, and a plurality of transfer / read clocks of different speeds are generated in synchronization with the basic clock. It is characterized in that it is provided with timing signal generating means and clock switching means for switching the transfer / read clock for driving the line sensor.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
FIG. 1 is a block circuit diagram showing an embodiment of a main circuit of a single-lens reflex camera to which the present invention is applied. This single-lens reflex camera is a CPU that controls the overall functions of the camera.
11 is provided. This CPU 11 has a battery 13
From the regulator 15 and the supercapacitor 17, the constant voltage VDD1 is supplied. Also, CPU1
1 is a predetermined constant voltage VA via the DC / DC converter 19.
A and VDD are lens ROM 51 of a photographing lens (not shown)
Are being supplied to The CPU 11 and the lens ROM 51 are connected via a pin provided on the mount to read data.

AF motor 2 constituting an automatic focus adjustment device
Although not shown in the figure, 3 adjusts the focus by moving the focusing lens of the taking lens through a joint mechanism. The AF motor 23 is drive-controlled by the CPU 11 via the AF motor control circuit 21.
The rotation speed of is detected by the AF motor interlocking pulsar 25.

Switches for the input of the CPU 11,
Metering switch SWS, release switch SWR, lock switch SWLOCK, and other camera modes,
Various information switches 27 for changing and selecting the shutter speed, aperture value, etc. are connected. Metering switch SW
S is a switch for calculating the exposure and operating the automatic focus adjustment device, which is turned on when a release button (not shown) is half-pressed.

This single-lens reflex camera is equipped with a CCD image (line) sensor unit (AF sensor unit) 30 for detecting a focused state as a defocus amount.
The AF sensor unit 30 includes a CCD drive circuit 3
Driven by two. In addition, the AF sensor unit 30
As is well known, although not shown in the figure, the light enters through the taking lens, passes through the half mirror part in the central part of the main mirror,
Further, the subject light reflected by the sub mirror enters. The incident subject light is imaged on the sensor portions (see FIG. 2) in which the light fluxes included in the three different field regions are different. It should be noted that each of the light fluxes contained in each of the three field areas is divided into two by a division optical system (not shown) and imaged on each sensor unit.

The structure of the AF sensor unit 30 will be described in more detail with reference to FIG. Image sensor 301
Is a single CCD transfer unit 303 and a CCD transfer unit 303
It is provided with three first, second and third sensors 304A, 304B and 304C which are provided adjacent to each other and separated from each other. Each first sensor 304A, second sensor 304
B and the third sensor 304C include a pair of light receiving portions A1 and A2, B1 and B2, and C1 and C2, respectively.

Each sensor 304A, 304B, 304C
As is well known, although not shown in detail, are a large number of light receiving elements (photodiodes) arranged in a line independently of each other.
An array, a storage unit that stores the charges generated by each light receiving element, and a memory unit that temporarily stores the charges stored in the storage unit when the integration is completed. The light from the subject is received, the light receiving element photoelectrically converts it, and the storage unit stores it.
It is transferred to the transfer unit 303. Then, the CCD transfer unit 3
03 in a fixed direction is transferred stepwise in pixel units by two-phase transfer clocks φ1 and φ2.
The reading unit 303a of No. 03 outputs the data in pixel units.

FIG. 2 shows the charge arrangement of the CCD transfer unit 303 immediately after the signal charges are transferred from the sensors 304A, 304B and 304C to the CCD transfer unit 303 all at once. In the CCD transfer unit 303, a large number of electrodes (not shown) are formed at regular intervals. In other words, the sensors 304A and 30 are provided to the CCD transfer unit 303 by these electrodes.
4B, 304C corresponding to the first, second, and third sensor pixel groups 404A, 404B, 404C, and the first dummy pixel group 404Ad on the read side with respect to the first sensor pixel group 404A.
And a second dummy pixel group 404Bd between the first and second sensor pixel groups 404A and 404B, and a third dummy pixel group 404C between the second and third sensor pixel groups 404B and 404C.
d and are formed. Therefore, at the time of reading, the first dummy pixel group 404Ad and the first sensor pixel group 4
04A, the second dummy pixel group 404Bd, the second sensor pixel group 404B, the third dummy pixel group 404Cd, and the third sensor pixel group 404C all at once in the CCD unit 303.
And is output in this order from the reading unit 303a in pixel units.

Then, the output signal charge is transferred to the amplifier 3
The signal is amplified by 25 and is output by the clamp circuit 327 as a video signal VIDEO which is an output signal from the reference level. The output video signal VIDEO is taken in by the CPU 11, A / D converted, stored in the RAM, and used for defocus calculation. In addition, the dummy pixel group 404A
The pixel signals of d, 404Bd, and 404Cd are the CPU 11
Is not taken into.

Each pixel group 4 is stored in the internal ROM of the CPU 11.
04Ad, 404A, 404Bd, 404B, 404C
The number of pixels of d and 404C is stored in the memory, and the CPU 11
Selects valid / invalid reading of each transferred pixel signal based on these pixel number data. In the present embodiment, the number of pixels from the read (transfer) start to the read start point of the first sensor pixel group 404A is Ast.
art, the number of pixels until the reading start point of the second sensor pixel group 404B is Bstart, and the third sensor pixel group 404C
Is written in the internal ROM of the CPU 11 with Cstart as the number of pixels up to the reading start point.

Further, each sensor 304A, 304B, 30
Adjacent to 4C, monitor sensors M1, M2, M3, monitor sensors M4, M5, M6, monitor sensors M7, M8, M
9 is provided, and the shielded monitor dark sensor MD is provided adjacent to the first light receiving portion B1 of the second sensor 304B. The monitor sensors M1 to M9 are sensors that detect the brightness of the subject in order to control the integration time (end of integration) according to the brightness of the subject. On the other hand, the monitor dark sensor MD is a sensor that obtains a signal for removing the dark current components of the monitor sensors M1 to M9 and is shielded from light.

The above-mentioned first, second and third sensors 304A,
304B, 304C integration operation (charge accumulation), first, second, third sensors 304A, 304B, 304C to CC
The charge (integrated value) transfer to the D transfer unit 303, the charge transfer in the CCD transfer unit 303, the clamp processing by the clamp circuit 327, etc.
Clock (pulse signal) output by the driver circuit 33
Driven by. Further, the monitor sensors M1 to M3 are monitor control circuits 311, the monitor sensors M4 to M6 are monitor control circuits 313, the monitor sensors M7 to 9 are monitor control circuits 315, and the dark sensors MD are AGC control circuits 323.
It is used to control each.

The automatic focus adjustment process of the single-lens reflex camera is started on condition that the photometric switch SWS is turned on. When the photometric switch SWS is turned on, the CPU 11 raises the integration start signal φINT to start integration. When the integration value of the predetermined monitor sensors M1 to M9 exceeds the preset integration end level VRM and the integration end signal φAD is output, or when the integration is forcibly ended when a predetermined integration time elapses. The integration is completed.

When the integration is completed, a transfer pulse φTG is output and the signal charge integrated by each light receiving section is transferred to the CCD transfer section 303.
Transfer to. The signal charges transferred to the CCD transfer unit 303 are transferred to the CCD transfer unit 303 pixel by pixel by the transfer / read clocks φ1 and φ2 generated in synchronization with the reference clock φM. Then, it is output (read out) pixel by pixel from the reading end portion 303a, amplified by the amplifier 325, clamped by the clamp circuit 327, and output as a pixel-based VIDEO signal. Clamp circuit 327
Clamps the reset field through level in synchronization with the reset field through clamp pulse φCL,
The output is sampled and held in synchronism with the sample hold pulse φSH, OB clamp is performed only during the output period of the optical black (OB) clamp signal φOB, and the signal is output as a Video signal. The reset field through clamp pulse φCL, the sample hold pulse φSH, and the OB clamp signal φOB are the reference clocks φM and φM ′.
It is generated based on.

The above is the normal AF sensor unit control operation, but the sensor control operation, which is a feature of the present embodiment, will be described with reference to FIGS. 3 to 7. First,
This will be described with reference to the timing charts shown in FIGS. 6 and 7. FIG. 6 is a timing chart relating to a normal AF operation, and FIG. 7 is a timing chart of an embodiment in which the clock is changed. In addition, each symbol in the illustrated embodiment indicates the following clock or signal. Signal generated by CPU 11 φM: Reference clock φINT: Integration start signal SPEED1, SPEED2: Clock selection signal S / HCTL: Sample hold signal Timing generation / driver circuit 33 generated signal φM ′: Reference clock φ1 synchronized with reference clock φM , Φ2: Internal reference clock (transfer, read pulse) φSH: Sample hold pulse φAD: Integration end signal / transfer read count pulse φOB: Optical black signal (dark current) φCL: Reset field through clamp pulse φTG: Transfer gate (transfer) Signals generated by other components VAGC: Reference voltage for integration stop VOUT: Integration output voltage (VIDEO signal) VRM: Integration end level M1, M2: Monitor sensor signal MD: Monitor dark sensor signal

FIG. 3 shows a timing signal generating means which is a feature of this embodiment. This timing signal generation means is one of the circuits that constitute the timing generation / driver circuit 33 in the present embodiment.

The timing signal generating means selects one of the frequency output circuit 35, which divides the basic clock φM into a through output and two types to output a total of three types of clocks, and a clock output from the frequency dividing circuit 35. And a flip-flop circuit 37 for generating the basic clock .phi.M 'and the transfer clocks .phi.1 and .phi.2 from the clock selected by the selection circuit.

Basic clock φ input to the frequency dividing circuit 35
M is branched into three, one is directly output to the selection circuit 36, and the other two are D flip-flop circuits 351 and
352 is input to the C input of the D flip-flop circuit 3
The Q bar outputs of 51 and 352 are output to the selection circuit 36.

D flip-flop circuit 3 of the selection circuit 36
Clock selection signals SPEED1 and SPEED2 are input to the D inputs of 61 and 362 as clock switching signals. D
Q output and Q of flip-flop circuits 361 and 362
The bar output is input to the 363 NAND matrix. The Q output and Q bar output of the first D flip-flop circuit 361 are input to one input of the NAND circuit, and the Q output and Q bar output of the second D flip-flop circuit 362 are input to the other input of the NAND circuit. There is. FIG.
In the above, the symbol "?" Indicates one input of the NAND circuit, and the two symbols "?" In the column direction indicate a pair of inputs of one NAND circuit. That is, the selection circuit 36 of the present embodiment includes four NAND circuits. Each NAND
The output of the circuit is sent through the inverter 364 to the inverters 366, 367, 368, 36 of the numbers 0-3.
9 is used as a control signal for controlling the output. And each inverter 366, 367, 368, 36
One of the nine outputs (φM0 to φM3) is selected and output to the flip-flop circuit 37.

The relationship between the logic values of the clock selection signals SPEED1 and SPEED1 and the basic clocks .phi.M and .phi.M0 to .phi.M3 and the waveforms of the respective basic clocks .phi.M and .phi.M0 to .phi.M3 are shown in FIG.
And shown in FIG. As can be seen from these figures, the basic clock .phi.M and the first basic clock .phi.M0 are the fastest, and the second basic clock .phi.M1, the third basic clock .phi.M2 and the fourth basic clock .phi.M3 are the slowest in order.

The flip-flop circuit 37 includes three stages of D flip-flops 371, 372, 373, and the basic clock φM selectively output by the selection circuit 36.
0 to φM3 are the D flip-flops 371 to 37 of the respective stages
It is input to the C input of 3. The Q output of the D flip-flop 373 at the final stage becomes the transfer / read clock φ1 via the inverter, and the Q bar output becomes the transfer / read clock φ2 half phase shifted from the transfer / read clock φ1 via the inverter. By these transfer / read clocks φ1 and φ2, charges are transferred to the CCD transfer unit 303 and output from the read unit 303a.

The Q-bar output of the final stage D flip-flop 373 is the D flip-flop 36 of the selection circuit 36.
It is input to the C input of 1,362. That is, the timing of the switching operation control of the selection circuit 36 is the fall of the transfer / read clock φ2 (the rise of the Q-bar output).
Is in sync with.

The clock switching process executed by the CPU 11 will be further described with reference to FIGS. In the circuit configuration shown in FIG. 3, the selection circuit 36 is
It is possible to select four types of first to fourth clocks .phi.M0 to .phi.M3. In the present embodiment, these clocks .phi.M0 ...
Two of the first and second basic clocks φM0 from φM3,
φM1 is selected as the high-speed clock and the low-speed (standard) clock, and both the first and second basic clocks φM
A description will be given below assuming that 0 and φM1 are switched to operate.

FIG. 8 shows a main flowchart of this AF sensor unit processing. In this process, when the integrated values of the dummy pixel groups 404Ad, 404Bd, 404Cd are read, the first basic clock φM0 is selected and read with the high-speed transfer / read clocks φ1, φ2 (first-speed transfer / read clock). When the integrated pixel values of the sensor pixel groups 404A, 404B, 404C are read out, the second basic clock φM1 is selected and the read processing is performed with the standard speed transfer / read clocks φ1, φ2 (the second speed transfer / read clock). It is characterized by doing. In this process, first, the basic clock φM is output, and the numbers of pixels A, B and Cstart are set in the RAM (S
201, S203). The AF sensor unit 30 is reset and initialized to prepare for integration (S20).
5).

Then, the clock selection signal SPPED1 is set to "1".
(Logical value 1, high level) and the clock selection signal SPPED2 is reset to "0" (logical value 0, low level) (S207). As a result, the basic clock φM is switched to the second basic clock φM1, and the read clock is also switched to the standard speed transfer / read clocks φ1 and φ2 corresponding to the second basic clock φM1, and the AF sensor unit is based on these clocks. It becomes possible to drive 30.

Next, the integration signal φINT is raised to a high level in order to start integration (S209). This causes the sensors 304A, 304B, 304C to start integration. The CPU 11 waits for the integration end signal φAD to fall to the low level, that is, for the integration to end (S2).
11). When the integration is completed, after this time, the integration end signal φAD becomes a count pulse synchronized with the transfer / read clocks φ1 and φ2, and the number of transfer pixels can be counted by counting this count pulse φAD.

When the integration is completed, the integration end flag FENDi
"1" is set to nt, and the φAD counter that counts up the falling edge of the count pulse φAD is started (S213, S215). Clock selection signal SPPED1, 2
"0" is set for each (S217). By this setting, the second basic clock φM1 is switched to the first basic clock φM0, and the transfer / read clocks φ1, φ
Since 2 also switches at high speed, high-speed transfer starts. Then, it waits until the count value of the φAD counter becomes equal to or larger than the A start point number Astart (S219). Since the first sensor dummy pixel is read out here, it is discarded as it is.

When the count value of the φAD counter becomes equal to or more than the A start point number Astart, the fetch count is set to Ase.
Set nser_bit and call the CCD IN subroutine to start the first basic clock φM0 to the second basic clock φ
Switch to M1 for standard speed transfer / read clock φ1
, Φ2, the respective pixel signals integrated by the first sensor light receiving portions A1 and A2 are fetched (S221, S223).

When the CCD IN subroutine is entered, "1" is set to the clock selection signal SPPED1 and the clock selection signal SPPE
D2 is set to "0" to select the second basic clock .phi.M1. Depending on this selection, the transfer / read clock φ1, φ
2 also becomes the standard speed clock, and transfer and reading are executed at the standard speed (S301).

Then, waiting for the count pulse φAD to fall to the “L” level, that is, in synchronization with the count pulse φAD, the pixel signal fetching process is performed (S303). In the pixel signal acquisition processing, the pixel signal amplified by the amplifier 325 and clamped by the clamp circuit 327 is input, and the A /
D-convert and store at a specified address in RAM (S3
05). Then, the number of acquisitions is decremented by 1, and it is checked whether the number of acquisitions after decrement has become 0. If it is not 0, the process returns to step S303 and S
The pixel signal acquisition processing in 303 and S305, the acquisition number decrement processing in S307, and the acquisition number check processing in S309 are executed. Then, when the number of acquisitions becomes 0, that is, the first sensor light receiving units A1 and A2.
When the pixel signal of is acquired, the process returns to step S225 of the START flow (S309).

In step S225, step S217
Similarly, "0" is set to each of the clock selection signals SPPED1 and SPPED2. By this setting, the second basic clock .phi.M1 is switched to the first basic clock .phi.M0, and the transfer / read clocks .phi.1 and .phi.2 are also switched at high speed, so that high speed transfer is started. Then, it waits until the count value of the φAD counter becomes equal to or more than the B start point number Bstart (S227). Since the second sensor dummy pixel is read out here, it is discarded as it is.

When the count value of the φAD counter becomes equal to or more than the B start point number Bstart, Bse is set as the number of fetches.
nser_bit is set, CCD IN subroutine is called, first basic clock φM0 to second basic clock φ
Switch to M1 for standard speed transfer / read clock φ1
, Φ2, the respective pixel signals integrated by the second sensor light receiving portions B1 and B2 are fetched (S229, S231).

After the pixel signals of the second sensor light receiving portions B1 and B2 are fetched, the process returns to step S233 of the START flow, and like the steps S217 and S225, the clock selection signals SPPED1 and SPPED2 are respectively set to "0". Set. With this setting, the second basic clock .phi.M1 is switched to the first basic clock .phi.M0 and the transfer / read clocks .phi.1 and .phi.2 are also switched at high speed, so that high speed transfer is started. Then, it waits until the count value of the φAD counter becomes equal to or more than the C start point number Cstart (S235).
Since the third sensor dummy pixel is read out here, it is discarded as it is.

When the count value of the φAD counter becomes equal to or more than the C start point number Cstart, the fetch count is set to Cse.
nser_bit is set, CCD IN subroutine is called, first basic clock φM0 to second basic clock φ
Switch to M1 for standard speed transfer / read clock φ1
, Φ2, the respective pixel signals integrated by the third sensor light receiving portions C1 and C2 are fetched (S237, S239).

After the pixel signals of the third sensor light receiving portions C1 and C2 are captured, the process returns to S241 of the START flow, the φAD counter is stopped and the process returns to S205, and the processes of S205 to S241 are repeated.

The CPU 11 executes the steps S223 and S2.
31, the sensors 304A and 304 acquired in S239
A predetermined defocus amount calculation process is performed based on the pixel signals of B and 304C, and a predetermined AF process is performed.

As described above, in the present embodiment, when the signal charge is serially read from the transfer section 303 of the AF sensor unit 30, the second basic clock φM1 is supplied during the period in which the signal charge is read from the transfer section 303. Switch to and transfer /
The read clocks φ 1 and φ 2 are switched to the standard speed, but the charges of the dummy sensor pixel group, which are unnecessary charges, are transferred to the transfer unit 303.
Since the transfer / read clocks .phi.1, .phi.2 are switched at high speed by switching to the first basic clock .phi.M0 during the period of being output from, the read time is shortened.

The above is the embodiment in which the signal charges are taken in from all the sensor sections. However, in the multi-AF processing, the pixel signals of some of the sensor sections among the plurality of sensor sections ( Sometimes only the signal charge) is used. For example, in the present embodiment, there are cases where only the pixel signals of the third sensor light receiving units C1 and C2 are used. In such a case, it is useless to take in the pixel signals of the first sensor light receiving portions A1, A2 and the second sensor light receiving portions B1, B2 that are output before the pixel signals of the third sensor light receiving portions C1, C2.

Therefore, in the second embodiment, the pixel signals of the first sensor light receiving portions A1 and A2 and the second sensor light receiving portions B1 and B2 which are not taken in are swept out by the high speed pulse similarly to the dummy pixel. An example of the processing is shown in FIG.
The same step number is attached to the step shown in FIG. 8 and performing the same processing as the step shown in FIG. The third
Although not shown, the photographer or the like selects the sensor 304C. When the third sensor 304C is selected, the flow chart shown in FIG. 10 is entered.

Since the second embodiment is the same as the step shown in FIG. 8 in which the processing of S219 to S233 is omitted, the description of the individual steps will be omitted and only the features will be described.

When the integration is completed, the integration end flag FENDi
"1" is set to nt, and the φAD counter that counts up the falling edge of the count pulse φAD is started (S213, S215). Clock selection signal SPPED1, 2
"0" is set for each (S217). By this setting, the second basic clock φM1 is switched to the first basic clock φM0, and the transfer / read clocks φ1, φ
Since 2 also switches at high speed, high-speed transfer starts. Then, it waits until the count value of the φAD counter becomes equal to or more than the C start point number Cstart (S235). Since the first sensor dummy pixel signal, the first sensor pixel signal, the second sensor dummy pixel signal, the second sensor pixel signal, and the third sensor dummy pixel signal are read out here, they are discarded as they are.

When the count value of the φAD counter becomes equal to or more than the C start point number Cstart, the fetch count is set to Cse.
Set nser_bit, call CCD IN subroutine, switch from the first basic clock φM0 to the second basic clock φM1, and transfer / read clock φ at standard speed.
The pixel signals integrated by the third sensor light receiving portions C1 and C2 are fetched by 1 and φ2 (S237 and S239).

When the process of taking in the pixel signals of the third sensor light receiving parts C1 and C2 is completed, the φAD counter is stopped and the process returns to S205, and the steps S205 to S217 and S235 are performed.
~ The process of S241 is repeated.

As described above, according to the second embodiment,
When only the third sensor 304C is used, the pixel signals of the first sensor A and the second sensor B are read with a high-speed clock, so the time until the reading of the pixel signal of the third sensor 304C is shortened.

When the second sensor 304B and the third sensor 304C are selected, the pixel signals of the first sensor 304A are read out by skipping steps S219 to S225 in the steps shown in FIG. Is performed at high speed, the second sensor 304B and the third sensor 304B
The reading end time of the sensor 304C is shortened.

As described above, according to the first and second embodiments, the transfer / read clock is switched to the high-speed clock while the unused charges are being read during the series of charge read processing, and the charges to be used are read. Since the clock is switched to the standard speed clock when outputting, the reading time is shortened and the AF sensor unit processing time is shortened. Moreover, in the present embodiment, the basic clock φM is divided to convert the clock speed, but in this case, since switching is performed in synchronization with the transfer read pulses φ1 and φ2, synchronization is maintained throughout the AF sensor unit processing. To be done.

[0050]

As is apparent from the above description, the present invention is
When receiving light from the subject with the light receiving unit and transferring multiple pixel signals photoelectrically converted and accumulated to the transfer unit in stages,
When the read pixel signal is taken in, it is driven by the standard speed transfer / read clock generated from the reference clock, and when reading other charges, it is faster than the standard speed transfer / read clock generated from the reference clock. transfer/
Since it is driven by the read clock, the time required for capturing the pixel signal is shortened.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a main part of a circuit configuration of a single-lens reflex camera to which the present invention has been applied.

FIG. 2 is a diagram showing a configuration of a CCD image sensor unit of the same eye reflex camera.

FIG. 3 is a block circuit diagram showing an embodiment of a timing signal generating means of a CCD processing circuit of the same eye reflex camera.

FIG. 4 is a diagram showing a relationship between a clock switching signal and a basic clock in the timing signal generating means.

FIG. 5 is a diagram showing a waveform of a basic clock in the timing signal generating means.

FIG. 6 is a diagram showing a timing chart of the CCD processing circuit.

FIG. 7: CCD for clock switching operation of the present invention
It is a figure which shows the timing chart of a processing circuit.

FIG. 8 is a first diagram relating to a clock switching operation of the present invention.
It is a figure which shows the flowchart of embodiment of this.

FIG. 9 is a diagram showing a flowchart relating to a process of capturing a pixel signal output from a CCD image sensor unit.

FIG. 10 is a diagram showing a flowchart of a second embodiment of the clock switching operation of the invention.

[Explanation of symbols]

11 CPU (control means) 30 CCD line sensor unit 301 Line sensor 303 CCD transfer section 304A First sensor 304B Second sensor 304C Third sensor 33 Timing generation / drive circuit (clock means,
Timing signal generating means) 35 frequency divider circuit 36 selection circuit 37 flip-flop circuit

Front page continuation (72) Inventor Masahiro Kawasaki 2-36 Maenocho, Itabashi-ku, Tokyo Asahi Kogaku Kogyo Co., Ltd.

Claims (5)

[Claims] 1. A light receiving section having a plurality of light receiving means for receiving a subject light, photoelectrically converting and accumulating the electric charge, and the electric charge accumulated by each of the light receiving means is transferred stepwise by a transfer / reading clock. A line sensor having a transfer unit for outputting, a clock unit for outputting a constant basic clock, and the transfer / transfer at different speeds in synchronization with the basic clock.
A focus detection sensor control device comprising: a timing signal generation unit that generates a plurality of read clocks; and a clock switching unit that switches the transfer / read clock speed that drives the line sensor. 2. The clock switching means according to claim 1, wherein a period in which the unnecessary charges are output from the transfer unit is switched to a high-speed first speed transfer / read clock, and a period in which useful charges are output is the first clock. A sensor control device for focus detection, characterized by switching to a transfer / read clock at a second speed which is slower than the transfer / read clock at one speed. 3. The focus detection according to claim 1, wherein the transfer section is composed of one continuous CCD transfer section, and the light receiving section is composed of a plurality of light receiving sections separated from each other. Sensor control device. 4. The switching device according to claim 2, wherein the switching unit switches to the transfer / reading clock at the second speed during a period in which the light receiving unit of each of the light receiving units reads the charges photoelectrically converted from the transfer unit, A focus detection sensor control device, characterized in that the transfer / read clock of the first speed is switched during the other periods. 5. The switching device according to claim 2, wherein the switching unit switches to the transfer / read clock at the second speed during a period in which the useful charge used for focus detection is read from the transfer unit, and in other periods. A focus detection sensor control device, characterized by switching to the transfer / read clock of the first speed.