JPH0828857B2 - Character blur prevention circuit in video circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character blurring prevention circuit in a video circuit such as a still image reproducing device.

2. Description of the Related Art In recent years, for example, a still image reproducing device is commercially available in which a photographic image photographed by a camera is magnetically recorded on a still image floppy disc and is reproduced by an ordinary television. Here, the video signal is recorded on a plurality of tracks on the disk in a relationship of 1 track-1 screen, that is, 1 rotation-1 field. Then, such a video signal is read by a head from the disk, demodulated and output.

By the way, the normal television standard system employs a 1/2 interlaced scanning (so-called interlaced scanning) system. For example, in the NTSC system as in Japan, the number of horizontal scanning lines for one field is 262.5H, and the total number of scanning lines for one screen is 525H for two fields, that is, one frame. When reproducing a still image disk or the like in which a video signal of one field (that is, a horizontal scanning line of 262.5H) is recorded in one track by such a television, the joint portion of the recording becomes a problem. That is, the video signal on the same track (which is always the same video signal for each field) is read while continuously rotating the still image disk, but at the recording seam (that is, the end point = start point), H, that is, a half of the horizontal synchronization period, shifts for each field. Therefore, if the image is reproduced as it is on an ordinary television receiver, the screen will be distorted, and a normal still image cannot be displayed.

Therefore, the 1-field repeated reproduction signal is alternately passed through the 0.5H delay circuit, which is 1/2 horizontal synchronization period for each field, from the recording seam on the track, and these are combined to synthesize the horizontal synchronization. It is necessary to create a continuous playback signal.

Therefore, in general, a block structure as shown in FIG. 3 is adopted. First, after the video reproduction signal on a certain track read by the reproduction head 1 is amplified by the head amplifier 2, one is made a non-delayed through signal, and the other is made.
It is input to the demodulation circuit (FM) 4 as a 0.5H delay signal passed through the 0.5H delay circuit 3 for 1/2 horizontal synchronization period. Here, in the demodulation circuit, these through signals and 0.5H delay signals are alternately switched for each field by a switching pulse signal SWP (Y) (Y means a luminance signal). On the other hand, the composite periodic signal (C · Sync) obtained by separating the demodulated signal by the periodic signal separation circuit 5
A synchronizing signal is generated through the synchronizing signal generation circuit 6, and the signal demodulated by the demodulation circuit 4 is combined by the waveform combining circuit 7 and output as a frame signal (video signal) to the receiver. . Here, the switching pulse signal SWP (Y) selects the through signal and the 0.5H delay signal by switching between the H level and the L level for each field as shown in FIG. The H delay period is generated, and the switching pulse signal SWP (Y) has a vertical through period (H level) in the 0.5H delay period.
The through signal is selected only in the vertical synchronization period.

In the timing chart shown in FIG. 4, the video signal is placed between the 1H horizontal synchronizing signals. In the vicinity of the vertical synchronization, there are a plurality of equivalent pulses arranged in 0.5H, and 6 equivalent pulses, and thus 3H, are used as the vertical synchronization signal V. Before and after such a vertical synchronizing signal V, there are 6 equivalent pulses, that is, V detection portions arranged in 0.5H rows of 3H each. 0.5 for switching pulse signal SWP (Y)
Within the H delay period, there are vertical through periods corresponding to these 18 equivalent pulses, in which the actual vertical synchronizing signal V is detected and directly output as a through signal.

This is the basic method for preventing image blurring for each field.

By the way, when reproducing such a still image, the character of the track number in which the still image is recorded may be displayed on the screen together with the still image. The character information such as the track number is not recorded on the disk and is processed by, for example, a circuit shown in FIG. First, the microcomputer 8 writes the data for determining the character display position to the character generation IC 9, and the character generation IC 9
Then, when the display position is reached, character data is output and displayed. At this time, the track number is displayed, for example, at the upper right position of the screen, but in any case, it is better to specify the character display position and always display the same position. Therefore, in the character generation IC9, the composite sync signal C.Syn
The vertical synchronizing signal V.Sync is received through the integrating circuit 10 based on c, and the composite synchronizing signal C.Sync is supplied to the transistor 11
Horizontal sync signal H ・ Sy through the signal inverted by
receive nc. Then, as shown in FIG. 6, the number of horizontal synchronizing signals H.Syns is counted from the time when the vertical synchronizing signal V.Sync is detected through the integrating circuit 10 (rising edge), and the predetermined position determined by the program, that is, n. The character of the track number is displayed at the H position for each piece.

The problem to be solved by the invention is that a whisker-like switching noise, as shown by a broken line pulse A in FIG. 6, appears on the composite sync signal C.Sync at the fall of the switching pulse signal SWP (Y). Sometimes. Here, in order to determine the character display position of the track number, the horizontal synchronizing signal H.Sync is sequentially counted from the rising of the vertical synchronizing signal V.Sync. The noise pulse A is also counted as 1H. Since the count value is n × H, which is about 1H earlier than the through period, the display position is 1H. Since the character display deviated by 1H is repeated alternately, the track number display is in a character flickering display state of flickering up and down.

Means for solving the problem The output of the composite sync signal from the rising edge of the vertical sync signal to at least after the falling edge of the vertical through period after the output to the character generation IC is invalidated, and the operation end time is set in the composite sync signal. A monostable circuit is provided as a reference time for counting the horizontal synchronizing signal.

By the fall at the end of the vertical slew period,
Whisker-shaped noise pulses equivalent to the horizontal sync signal may be mixed in the composite sync signal, but during this period, the monostable circuit disables and masks the output of the composite sync signal. Since the horizontal synchronizing signal is counted with reference to the end point of the operation of, the noise pulse is never counted. Therefore, the characters and the like of the track number are always output to the same horizontal synchronizing signal portion, and vertical blurring does not occur.

Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 and 2. The same parts as those shown in FIGS. 3 to 6 are designated by the same reference numerals. In this embodiment, the horizontal synchronizing signal H for the character generating IC 9 is operated by operating on the basis of the output of the integrating circuit 10.
A monostable circuit 12 that masks the Sync input for a certain period is provided. That is, the monostable circuit 12 is the integration circuit.
A monostable multivibrator 13 that is triggered by the rising edge of the vertical sync signal V.Sync detected by 10 is provided, and a transistor 14 that is turned on by the output of the monostable multivibrator 13 is connected in parallel to the transistor 11. Become. Here, the number of the monostable multivibrator 13 is m from the rising timing t ₁ of the vertical synchronizing signal V · Sync,
For example, it is set so that output can be generated over a length of about 8H. That is, the switching pulse signal SWP
It is set so that the output can be performed at least until the timing t ₂ which is later than the fall of the vertical through period of (Y).

With this configuration, when the integrating circuit 10 detects the vertical synchronizing signal V.Sync based on the composite synchronizing signal C.Sync in the 0.5H delay period, the signal is generated.
Captured by IC9. On the other hand, monostable multivibrator 1
3 is triggered at the rising edge of this timing t ₁ to turn on the transistor 14. Therefore, even if the composite sync signal C • Sync is inverted by the transistor 11 and the horizontal sync signal H • Sync is taken in by the character generation IC 9, it is canceled by the transistor 14 which is turned on to the ground side, and one pulse for about 8H is reached. Only given. Then, when the monostable multivibrator 13 is turned off and the transistor 14 is turned off, the horizontal synchronizing signal H · Sy is generated as in the case shown in FIG.
nc is sequentially output to the character generation IC9. Therefore, the horizontal sync signal H · Sync is counted with the operation end timing t ₂ of the monostable multivibrator 13 as a reference to determine the character display position (the count value is, for example, n−m H). Then, the noise pulse A will not be counted as 1H. That is, the timing t ₂ after the mask time when the influence of the noise pulse A is eliminated is not counted directly from the rising edge of the vertical synchronizing signal V · Sync and is used as the counting reference point of the horizontal synchronizing signal H · Sync. As a result, it is possible to always display the track number on the same horizontal synchronization line without repeating vertical blurring for 1H.

As described above, the present invention provides a monostable circuit that operates for a fixed time from the vertical sync detection time in the 0.5H delay period, and counts the horizontal sync signal in the composite sync signal based on the end time of the operation. Therefore, even if a whisker-like noise pulse occurs in the composite sync signal due to the fall of the vertical through period, it is masked by the monostable circuit and invalidated, so the noise pulse is not counted either. It is possible to always display the track number characters at the same position without vertical blurring.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing its operation, FIG. 3 is a circuit diagram showing general video signal processing, and FIG. 4 is a timing showing its operation. FIG. 5 is a circuit diagram showing a conventional example, and FIG. 6 is a timing chart showing its operation. 9 …… Character generation IC, 12 …… Monostable circuit, SWP (Y) ……
Switching pulse signal (switching control signal), C / Sync
... Composite sync signal

Claims (1)

[Claims] 1. A composite sync signal in which a horizontal sync signal and a vertical sync signal are mixed is used, and a through period for outputting a video signal as a through signal and a 0.5H delay signal obtained by delaying the through signal by 0.5H are output. The 0.5H delay period is switched to every 1 field, and at the time of vertical synchronization in the 0.5H delay period, the vertical synchronizing signal is output in the through signal state without being delayed. In a character blur prevention circuit in a video circuit equipped with a character generation IC that counts the number of pulses of the horizontal sync signal in the composite sync signal based on the detection of the sync signal to determine the output position of the displayed character, the vertical sync signal Of the composite sync signal from the rising edge of at least the falling edge of the vertical through period Character shake preventing circuit in the video circuit, characterized in that the operating end and disables output for serial character generator IC provided monostable circuit for a reference time count of the horizontal synchronizing signal in the Konpojitsuto synchronization signal.