JPH08287242A - Data transfer controller - Google Patents

Abstract

PURPOSE: To improve the availability of a storage means with simple configuration. CONSTITUTION: An image bus control part 20 controls a page memory 26, an expansion processing part 18a2, and an input buffer 16a1 and data stored in the page memory 26 are transferred to an input buffer 16as3, an expansion processing part 18a2, an output buffer 14a3, and the input buffer 16a1, and inputted to an output device 24. The image bus control part 20 controls an input/output buffer 12, a compression processing part 18a1, and the page memory 26, and data outputted from a CPU are transferred to an input/output buffer 12, an input buffer 16a2, the compression processing part 18a1, an output buffer 14a2, and the page memory 26 in order and stored in the page memory 26.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device, and more particularly to a data transfer control device for transferring data input from an external input device to an external output device or an external input device.

[0002]

2. Description of the Related Art Conventionally, in a data transfer control device, the dot data generated by the CPU is temporarily held in a memory, the data in the memory is read out, and the speed peculiar to the output device is read. It is widely used to transfer in.

In this device, the cycle for writing the dot data generated by the CPU in the memory and the cycle for reading the memory for data transfer to the output device are executed for the memory which is a common resource, so the latter If more cycles are required to read the memory, the data to the output device will not be in time, and as a result, the output content may be erroneous.

In view of this fact, a buffer for buffering is provided between the system bus and the video memory, and while the MPU is accessing a device other than the video memory, the image data transfer control of the page printer is cut off from the video memory. A system and its apparatus have been proposed (Japanese Patent Laid-Open No. 3-62).
219).

In this device, the writing of data from the MPU to the video memory only slightly improved the limitation of reading data from the video memory to the output device. In other words, apparently the bus is disconnected at a certain time, but when writing data from the MPU to the video memory,
Contention with reading data from the video memory to the output device still remains. Moreover, M is very fast.
With PUs and very fast printers, conflicts will always occur. Avoiding competition with this technology is not possible.

Further, in order to improve the speed of the DRAM itself, a dynamic random access memory control device for improving the access speed of the DRAM to some extent by using an access called a first mode which the DRAM has (Japanese Patent Laid-Open No. 80322/1993). Issue).

This is a method of reducing the precharge time and accessing the DRAM itself at high speed by using a continuous read mode called a fast mode for reading from the DRAM instead of a normal cycle.
However, this can be easily realized because it simply uses the function of the DRAM itself, and the access on the bus is limited to the speed of the DRAM.

Common to both of the above-mentioned prior arts is to speed up the access to the DRAM only or to separate the access from the bus to the DRAM, but the page memory usage has become more complicated these days. The conventional method of directly connecting to an output device with a page memory has reached the speed limit.

By the way, recent page memories have come to be widely used for high-resolution, color output, and multi-function peripherals in which data is input from an input device and processed and output. The characteristics that can be commonly applied to this type of device are that the transfer speed is extremely high and the transfer data amount is large. Also, the data is
It is often found that not only output but also processing is added in real time. The video memory used in such a device is required to execute various processes in parallel at high speed.

As an example of the above processing, there are compression processing and decompression processing. The reason why compression and decompression are used is that by compressing the image data to be transmitted to the printer, the effect of reducing the load on the bus and the capacity of the buffer memory can be expected.

However, in order to incorporate this compression / expansion into an actual printer device, complicated control is required to guarantee the data transfer rate to the printer device. A printer that handles such compression / expansion has been proposed (Japanese Patent Laid-Open No. 3-252719).

For this printer, one proposal has been proposed for incorporating a function such as compression / expansion into the printer. A plurality of compression methods are provided in a compression control circuit on an image bus, which is separated from the system bus on the printer side, and the printer performs compression by a compression method not possessed by the host processor and sends it to the host processor. However, in this printer, the printer has multiple types of compressors and the actual circuit is not described, but the concept of parallelism of processing is not reflected and all the processing is done by simply placing the MPU on the image bus. Is configured to be executed.

In other words, the compression / expansion and density conversion functions are only incorporated in the printer device, and it is not necessary for these functions to be on the printer side. It is a prerequisite for this device to use functions in a time-sharing manner, such as a printer acting as a compressor for a certain time and an original printer for a certain time. In essence, this device merely replaces the functions that can be processed by software with the hardware in the special device. Further, in actual operation, the MPU on the system bus instructed by the host processor controls the transfer on the image bus and the processing circuits for each function, and all cycles are performed via the memory, and each processing is performed. It is executed sequentially. Since this device can process only one page as a unit, considering the worst case of data transfer in this device, after writing from the host processor to the memory, reading from the memory and expanding, the data is read again and the density is read. After conversion, it will be output to the printer. Since the memory speed is constant, the more processing, the slower the time until printing, and the continuous printing that can be realized by preparing one page while preparing the next page becomes impossible.

If it is attempted to execute the respective processes in parallel with this configuration, all the processes will cause access competition to the memory which is a common resource, and under this environment, it becomes difficult to guarantee the data transfer rate to the printer. In order to guarantee this, the MPU needs a mechanism for avoiding this on the image bus by its processing software.

Management by software of the MPU is performed by using an interrupt or the like, but this interrupt processing is limited to a speed range that can be processed by software, and in order to realize a plurality of parallel processings. , It is desirable to implement a mechanism for avoiding access conflict by the latter hardware.

Generally, avoiding access contention is performed by an arbiter circuit connected to the bus. This arbiter circuit receives an access request signal for each processing function and outputs an access permission signal for each processing function. Upon receiving an access request for each processing function of the image bus, this arbiter circuit uses this bus in various arbitration methods. Control to use in a time-sharing manner. As it is composed of hardware, the control speed itself is satisfactory. There are various methods as such an arbitration method, and generally, there are a method of assigning a priority (priority method) and a method of permitting in order (round robin method).

However, since such an arbiter circuit cannot know what kind of cycle is currently executed, considering a special case such as memory arbitration,
It is extremely difficult to improve the utilization effect.

Further, there are some other drawbacks. The first is the capacity of the memory. The memory capacity is always required for the number of processes for compressing, decompressing, or density converting data of a certain data format. The memory reduction effect of compression may be offset here. The larger the number of processes, the larger the memory required.

The second is the amount of data transferred during processing.
The printer must read the uncompressed data once and compress it, then return the compressed data to the host once and receive the compressed data again in order to print it. In this case, the uncompressed data is transferred by the equivalent amount of two times. Will be done. Assuming a color image of A3, 256 gradations,
If the data is represented by 4 colors of resolution 400 DPI and YMCK, it will be 128 MByte per sheet, so 2
Since a data transfer amount of 56 MBytes is required for the system bus, the bandwidth of the system bus must be very large.

Thirdly, the control of the memory itself needs to be incorporated in each processing function. Since each processing function individually accesses the memory, it is necessary to output all control signals for the memory such as addresses and control signals. This makes the hardware redundant and raises prices more than necessary.

To solve all of these drawbacks,
Structural improvement is indispensable, and a device that realizes parallel operation with a simple configuration is required.

The present invention has been made in view of the above facts, and an object of the present invention is to propose a data transfer control device in which the utilization efficiency of the storage means is improved with a simple structure.

[0023]

In order to achieve the above-mentioned object, the invention according to claim 1 holds an input holding means for holding data inputted from an external input device and outputting the held data, and holding the inputted data. A first holding means for outputting the held data and a second holding means for holding the input data and outputting the held data;
Storage means for inputting and storing data, and data output from the input holding means are transferred to the first holding means, and data output from the second holding means are transferred to the storage means. An image bus to which the output side of the input holding means, the input side of the first holding means, the output side of the second holding means and the input side of the storage means are connected, and from the first holding means It is connected to the output side of the first holding means for inputting data and to the input side of the second holding means for outputting data to the second holding means, and the image from the input holding means A first instruction is given to the first holding means to input the data output via the bus, a predetermined process is performed on the data input from the first holding means, and the predetermined processing is performed. Done day To the second holding means, and processing means for giving a second instruction to the second holding means so as to output the data held by the second holding means to the image bus; and the external input device. The data input to the input holding unit from the first holding unit is transmitted through the image bus to the first
Of the storage means, the processing means, the second holding means, and the storage means in this order,
The input holding means, as stored in the storage means,
And a control means for controlling the processing means and the storage means.

According to a second aspect of the present invention, in the first aspect of the present invention, an output holding means for holding the input data and outputting the held data to an external output device is further provided, and the output data is output from the storage means. The output side of the storage means and the input side of the input holding means or the input side of the output holding means are connected to an image bus so that the data is transferred to the input holding means or the output holding means, and the control means is The storage means so that the data stored in the storage means is input from the input holding means to the external input device via the image bus or from the output holding means to the external output device via the image bus. The input holding means or the output holding device is controlled.

According to a third aspect of the present invention, in the second aspect of the present invention, the control means transfers the data stored in the storage means from the output holding means to the external output device or the image bus via an image bus. Control to the storage means and the output holding means or the input holding means for outputting from the input holding means to the external input device via
The data output from the external input device is sequentially transferred to the input holding unit, the first holding unit, the processing unit, the second holding unit, and the storage unit via an image bus via an image bus. Then, the input holding means, the processing means, and the control of the storage means to be stored in the storage means are prioritized.

According to a fourth aspect of the invention, in the invention according to any one of the first to third aspects, the predetermined process is any one of compression, decompression and resolution conversion.

According to a fifth aspect of the invention, input holding means for outputting the input data to the external input device, first holding means for holding the input data and outputting the held data, and the input data Second holding means for holding and outputting the held data; storage means for outputting the stored data; output holding means for holding the input data and outputting the held data to an external output device; The output side of the storage means is such that the data output from the means is transferred to the first holding means and the data output from the second holding means is transferred to the output holding means or the input holding means, respectively. An image bar to which the input side of the first holding means, the output side of the second holding means and the input side of the output holding means or the input side of the input holding means are connected. And connected to the output side of the first holding means so as to input data from the first holding means and to the input side of the second holding means so as to output data to the second holding means. In addition, a first instruction is given to the first holding means to input the data output from the input holding means via the image bus, and a predetermined process is performed on the data input from the first holding means. The second holding means outputs the data subjected to the predetermined processing to the second holding means and outputs the data held by the second holding means to the image bus. The processing means for giving an instruction and the data stored in the storage means are connected to the output holding means via the first holding means, the processing means, the second holding means and the image bus via an image bus, or The above And a control means for controlling the storage means, the processing means, and the output holding means or the input holding means so that they are transferred in the order of the force holding means and input to the external output device or the external input device. .

According to a sixth aspect of the invention, in the fifth aspect of the invention, the input holding means holds the data input from the external input device, outputs the held data, and outputs the data to the image bus. When connected, the control means controls the input holding means and the storage means so that the data input from the external input device is transferred to and stored in the storage means.

The invention according to claim 7 is the invention according to claim 6, wherein the control means stores the data stored in the storage means into the first holding means, the processing means, and the second holding means. And controlling the storage means, the processing means, and the output holding means or the input holding means to be transferred to the output holding means or the input holding means in order and input to the external output device or the external input device. The data input from the device is transferred to the storage means and stored therein in priority to the control of the input holding means and the storage means.

According to an eighth aspect of the present invention, in the invention according to any one of the fifth to seventh aspects, the predetermined process is any one of compression, decompression and color tone conversion.

The invention according to claim 9 is the invention according to any one of claims 1 to 8, wherein the processing means outputs the input permission signal to the first holding means. The first instruction to the holding means and the output permission signal to the second holding means to give the second instruction to the second holding means, and the first holding means. If there is no data in the first holding means, a signal indicating that there is no data in the first holding means, and if there is data in the second holding means, a signal indicating that there is data in the second holding means. When output to the control means, the control means inputs a signal indicating that there is no data from the processing means to the first holding means,
The input holding means is controlled so that the data output from the external input device is input and held, and the held data is output to the bus, and a first data transfer permission signal is output to the processing means. As a result, the processing unit causes the first holding unit to output the input permission signal and the data output on the bus is input to the first holding unit, and the processing unit transfers the data to the second holding unit. When a signal indicating that there is data is input, by outputting a second data transfer permission signal to the processing means, the processing means outputs the output permission signal to the second holding means to hold the data. The processing means is controlled so that the generated data is output on the bus.

According to a tenth aspect of the present invention, input holding means for inputting and holding data from an external input device and outputting the held data, and storage means for inputting and storing the data and outputting the stored data. And at least one first processing means for performing the first processing on the input data and outputting the data subjected to the first processing, and performing the second processing on the input data and performing the second processing. At least one second processing means for outputting processed data; and at least one for inputting and holding the data according to an instruction of the first processing means and outputting the held data to the first processing means One first holding means and the second
Inputting and holding data according to the instruction of the processing means, and outputting at least one second holding means for outputting the held data to the second processing means, and the data output from the first processing means. And hold it together with the first
The at least one third holding means for outputting the held data according to the instruction of the processing means, and the data output from the second processing means for receiving and holding the second data.
From the input holding means, at least one fourth holding means for outputting the held data according to the instruction of the processing means, an output holding means for inputting and holding the data and outputting the held data to an external output device, The output data is stored in the first holding means, the data output from the third holding means is stored in the storage means, the data stored in the storage means is stored in the second storage means, and the fourth storage means is stored in the storage means. Of the input holding means, the first holding means and the second holding means of the input holding means so that the data output from the holding means is transferred to the output holding means or the input holding means. An input side, an output side of the third holding means and the fourth holding means, an input side and an output side of the storage means, and
An image bus to which the input side of the output holding means is connected, and data output from the external input device are stored in the input holding means, the first holding means, the first processing means, the third holding means, And transferred in the order of the storage means,
The input holding means, as stored in the storage means,
The first control for controlling the first processing unit and the storage unit is performed, and the data stored in the storage unit is stored in the second holding unit, the second processing unit, and the fourth holding unit. Means and the output holding means or the input holding means so as to be transferred to the external output device or the external input device in this order, and the storage means, the second processing means and the output holding means or the input holding means. And a control means for performing a second control.

According to an eleventh aspect of the present invention, in the tenth aspect of the invention, the control means gives priority to the second control over the first control.

According to a twelfth aspect of the present invention, in the tenth aspect of the present invention, a plurality of the storage means are provided, and the control means performs the first control and the second control at the same time.

According to a thirteenth aspect of the present invention, in the invention according to any one of the tenth to twelfth aspects, the first process is compression and the second process is decompression. There is.

According to a fourteenth aspect of the present invention, in the invention according to any one of the tenth to thirteenth aspects, the first processing means includes the first holding means and the second holding means.
And outputs the input permission signal to the second holding unit to give the instruction to the first holding unit and the second holding unit, and the first processing unit holds the third holding unit. And the second processing means outputs the output permission signal to the fourth holding means to give the instruction to the third holding means and the fourth holding means, and the first holding means. The processing means is the first
When there is no data in the first holding means, a signal indicating that there is no data in the first holding means and the second processing means when the second holding means has no data A signal indicating that there is no data in the holding means is output to the control means, respectively, and the first processing means has data in the third holding means when the third holding means has data. And the second processing means outputs to the control means a signal indicating that the fourth holding means has data when the fourth holding means has data, respectively. The means, when a signal indicating that there is no data is input from the first processing means to the first holding means, inputs and holds the data output from the external input device, and holds the held data. The image The input holding means so as to output the input data to the first holding means and output the first data transfer permission signal to the first processing means. It is confirmed that the data output from the input holding means on the image bus by outputting the permission signal is input to the first holding means, and the first processing means stores the data in the third holding means. When the signal shown is input, a second data transfer permission signal is output to the first processing means to cause the first processing means to output the output permission signal to the third holding means. The first processing means is controlled so that the data held by the third holding means is output to the image bus, and the second processing means indicates that there is no data in the second holding means. Signal The second processing means by controlling the storage means so as to output the stored data on the image bus and outputting a third data transfer permission signal to the second processing means. The second holding means outputs the input permission signal and the data output from the storage means onto the image bus is input to the second holding means, and the second processing means outputs the fourth data. When a signal indicating that there is data is input to the holding means, a fourth data transfer permission signal is output to the second processing means so that the second processing means outputs the fourth data to the fourth holding means. An output permission signal is output to control the second processing means so that the data held by the fourth holding means is output onto the image bus.

[0037]

According to the present invention, the output side of the input holding means, the input side of the first holding means, the output side of the second holding means, and the input side of the storage means are connected to the image bus.

A processing means is connected to the output side of the first holding means and the input side of the second holding means.

The control means controls the input holding means and the processing means so that the data input from the external input device to the input holding means is stored in the first holding means via the image bus. At that time, the processing means gives the first instruction to the first holding means to input the data output from the input holding means via the image bus. The first instruction may be given by, for example, outputting an input permission signal to the first holding means.

Further, the processing means performs predetermined processing on the data input from the first holding means and outputs the data subjected to the predetermined processing to the second holding means. Note that the predetermined processing includes, for example, compression, decompression, and resolution conversion.

Further, the processing means gives a second instruction to the second holding means so as to output the data held by the second holding means to the image bus. The second instruction may be given by, for example, outputting an output permission signal to the second holding means.

Then, the control means causes the data output from the second holding means to the image bus to be transferred to the storage means via the image bus and stored in the storage means, and the processing means and the storage means. To control.

Here, the processing means outputs a signal indicating that there is no data in the first holding means to the control means when there is no data in the first holding means and the data is stored in the second holding means. If there is, a signal indicating that the second holding means has data may be output to the control means.

In this way, the control means which inputs the signal indicating that there is no data from the processing means to the first holding means is
The input holding means is controlled to input and hold the data output from the external input device and to output the held data on the bus. Then, the control means causes the processing means to output the first data transfer permission signal to cause the processing means to output the input permission signal to the first holding means (the first data transfer permission signal).
Is given) so that the data output on the image bus is input to the first holding means.

As described above, the control means inputs the signal indicating that there is data from the processing means to the second holding means, and the control means outputs the second data transfer permission signal to the processing means. Causes the second holding means to output an output permission signal (gives a second instruction) so that the data held in the second holding means is output from the second holding means to the image bus. .

Here, the output side of the storage means and the input side of the input holding means or the input side of the output holding means may be further connected to the image bus.

Then, the control means causes the data stored in the storage means to be inputted from the input holding means to the external input device via the image bus or from the output holding means to the external output device via the image bus. It controls the storage means and the input holding means or the output holding device.

At this time, the storage means and the output holding means for outputting the data stored in the storage means from the output holding means to the external output device via the image bus or from the input holding means to the external input device via the image bus. Alternatively, the control of the input holding means is performed by inputting the data output from the external input device via the image bus, the first holding means,
The control is performed with priority over the input holding means, the processing means, and the control of the storage means, which are sequentially transferred to the storage means via the processing means, the second holding means, and the image bus and stored in the storage means.

As described above, the processing means is connected to the output side of the first holding means and the input side of the second holding means, and the data subjected to the predetermined processing is output from the second holding means to the image bus. Following the processing, the data input by the input holding means is input to the first holding means, a predetermined processing is performed, and the data is stored in the storage means via the second holding means.
Further, since the data stored in the storage means is read and input to the external input device via the input holding means or to the external output device via the output holding means, the data is continuously transferred and (EN) It is possible to perform a predetermined process and store it in a storage unit, continuously read data from the storage unit, and input the data to an external input device or an external output device, and improve the utilization efficiency of the storage unit with a simple configuration. You can

According to a fifth aspect of the present invention, the image bus has an output side of the storage means, an input side of the first holding means, and a second side.
The output side of the holding means and the input side of the output holding means or the input side of the input holding means are connected.

The processing means is connected to the output side of the first holding means and the input side of the second holding means.

Then, in the control means, the data stored in the storage means is output holding means or input holding means via the first holding means, the processing means, the second holding means and the image bus via the image bus. The storage means, the processing means and the output holding means or the input holding means are controlled so that they are transferred in this order and input to the external output device or the external input device.

At this time, the processing means first inputs the data output from the storage means via the image bus.
The first instruction is given to the holding means of. Note that, as described above, this first instruction may be performed by, for example, outputting an input permission signal to the first holding means.

Further, the processing means performs the predetermined processing on the data thus inputted from the first holding means, and outputs the data subjected to the predetermined processing to the second holding means. Note that the predetermined processing includes, for example, compression, decompression, and color tone conversion.

Then, the processing means gives a second instruction to the second holding means so as to output the data held by the second holding means to the image bus. It should be noted that, as described above, the second instruction may be performed by, for example, outputting an output permission signal to the second holding unit.

Here, as described above, the processing means outputs to the control means a signal indicating that the first holding means has no data when the first holding means does not have data, and the second means. When the holding means has data, a signal indicating that the second holding means has data may be output to the control means.

In this way, the control means which inputs the signal indicating that there is no data from the processing means to the first holding means is
The storage means is controlled so that the data stored in the storage means is output to the image bus. Then, the control means outputs the first data transfer permission signal to the processing means to cause the processing means to output the input permission signal to the first holding means (gives a first instruction), and outputs the signal onto the image bus. The output data is input to the first holding means.

Further, as described above, the control means to which the signal indicating that there is data in the second holding means is inputted from the processing means, the control means outputs the second data transfer permission signal to the processing means so that the processing means An output permission signal is output to the second holding unit (a second instruction is given) so that the data held in the second holding unit is output from the second holding unit to the image bus.

Further, the output side of the input holding means may be connected to the image bus. And in this case,
The control unit controls the input holding unit and the storage unit so that the data input from the external input device is transferred via the image bus and stored in the storage unit.

At this time, the data stored in the storage means is transferred in the order of the first holding means, the processing means, the second holding means and the output holding means or the input holding means, and then the external output device or the external input device. Control of the storage means, the processing means, the output holding means, or the input holding means to be input to the input terminal in preference to the control of the input holding means and the storing means for transferring the data input from the external input device and storing the data in the storage means I am trying to do it.

As described above, the processing means is connected to the output side of the first holding means and the input side of the second holding means, and the data subjected to the predetermined processing is output from the second holding means to the image bus. Subsequent to the processing, the data in the storage means input and stored from the external input device is read out, input to the first holding means, subjected to predetermined processing and output to the second holding means, and second The holding means stores the data in the storage means and the storage means while inputting data from the holding means to the external input device via the input holding means or the second holding means to the external output device via the output holding means. It is possible to continuously read and transfer data, perform predetermined processing, and input the data to an external input device or an external output device, so that it is possible to improve the utilization efficiency of the storage means with a simple configuration.

According to a tenth aspect of the present invention, the image bus includes an input side and an output side of the input holding means, an input side and an output side of the storage means, an input side of the first holding means and the second holding means, The output side of the third holding means and the fourth holding means, and the input side of the output holding means are connected.

The first processing means is provided on the output side of the first holding means and the input side of the third holding means, and the first processing means is provided on the output side of the second holding means and the input side of the fourth holding means. The second processing means is connected. The first processing means performs compression processing, and the second processing means performs decompression processing.

The control means performs the first control and the second control. The second control may be prioritized over the first control, or a plurality of storage means may be provided so that the first control and the second control may be performed simultaneously.

Here, the first control is that the data output from the external input device is input holding means, first holding means,
The input holding means, the first processing means and the storage means are controlled so that the first processing means, the third holding means and the storage means are transferred in this order and stored in the storage means.

In the second control, the data stored in the storage means is transferred in the order of the second holding means, the second processing means, the fourth holding means and the output holding means or the input holding means. The storage means, the second processing means, and the output holding means or the input holding means are controlled so as to be input to the external output device or the external input device.

Here, the first processing means outputs the input permission signal to the first holding means and the second processing means outputs the input permission signal to the second holding means, respectively.
The holding means may be instructed.

Further, the first processing means outputs the output permission signal to the third holding means and the second processing means outputs to the fourth holding means, respectively, so that the third holding means and the fourth holding means. May be instructed to.

Further, the first processing means sends a signal indicating that the first holding means has no data and the second processing means sends the second holding means to the second holding means when there is no data in the first holding means. When there is no data, a signal indicating that there is no data in the second holding means is output to the control means, respectively, and when the first processing means has data in the third holding means, the third holding means. The second processing means outputs a signal indicating that there is data to the control means, and the second processing means outputs a signal indicating that there is data in the fourth holding means to the control means. May be.

In this case, the control means inputs and holds the data output from the external input device when the signal indicating that there is no data is input from the first processing means to the first holding means. By controlling the input holding means so as to output the held data on the image bus and outputting the first data transfer permission signal to the first processing means, the first processing means transfers to the first holding means. The first processing unit is controlled so that the input permission signal is output and the data output from the input holding unit onto the image bus is input to the first holding unit.

Further, the control means outputs a second data transfer permission signal to the first processing means when a signal indicating that there is data is input from the first processing means to the third holding means. As a result, the first processing means is caused to output the output permission signal to the third holding means, and the first processing means is controlled so that the data held by the third holding means is output to the image bus.

Further, the control means controls the storage means so as to output the stored data on the image bus when the signal indicating that there is no data is input from the second processing means to the second holding means. And outputting the third data transfer permission signal to the second processing means to cause the second processing means to output the input permission signal to the second holding means to output the data output from the storage means onto the image bus. The second processing means is controlled so that is input to the second holding means.

Further, the control means outputs a fourth data transfer permission signal to the second processing means when a signal indicating that there is data is input from the second processing means to the fourth holding means. As a result, the second processing means controls the second processing means so that the fourth holding means outputs the output permission signal and the data held by the fourth holding means is output to the image bus.

In this way, the control means controls the input holding means, the first processing means and the storage means when performing the first control, and the storage means and the second processing when performing the second control. By controlling the means and the output holding means or the input holding means, the first processing and the second processing can be performed in parallel with a simple configuration, and the control means is the input holding means, the first processing.
Since the processing means, the storage means, the second processing means, and the output holding means are controlled, the data transfer path can be set arbitrarily according to the control timing.

[0075]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below in detail with reference to the drawings.

As shown in FIG. 1, the data transfer control device of this embodiment is provided with a page memory 26 as a storage means for temporarily holding the data output to the output device 24 and the data input from the input device 22. ing. The page memory 26 includes a DRAM. The image bus 2 is connected to the input end and the output end of the page memory 26.
8 are connected. An input / output buffer 12 as an input holding means is connected to the image bus 28 via an input end and an output end. This input / output buffer 12
Is a buffer for temporarily holding data from the system bus and data to the system bus.

Further, the data transfer control device of this embodiment is
A compression processing unit 18a1 as a first processing unit for performing compression processing on data and a decompression processing unit 18a2 as a second processing unit for performing decompression processing on data are provided. The compression processing unit 18a1 is connected to the image bus 28 via an input terminal as an input buffer 16a as a first holding unit.
2 is connected through the output end, and the second processing bus 18a2 is connected to the image bus 28 through the input end.
An input buffer 16a3 as a holding means for the is connected via an output end. Input buffers 16a2 and 16a3
Captures the data output onto the image bus 28 via the input end and temporarily holds the data, and the held data is compressed via the output end to the compression processing unit 18a1 and the expansion processing unit 18, respectively.
It is designed to output to a2.

Therefore, the compression processing section 18a1 inputs the data output onto the image bus 28 via the input buffer 16a2, and compresses the input data. In addition, the decompression processing unit 18a2
The data output on the image bus 28 is input via the input buffer 16a3, and the input data is expanded.

An output buffer 14a2 as a third holding means is connected to the compression processing section 18a1 via an input end. The output buffer 14a2 takes in the data compressed by the compression processing section 18a1 via the input end and temporarily holds the data, and outputs the held data to the image bus 28 via the output end. ing. An output buffer 14a3 as a fourth holding unit is connected to the decompression processing unit 18a2 via an input end. The output buffer 14a3 has a decompression processing unit 18a2.
The decompressed data is fetched via the input end and temporarily held, and the held data is output onto the image bus 28 via the output end.

Further, the data transfer control device of this embodiment is
Output buffer 14a1 as an input holding means for temporarily holding the data input from the input device 22 and outputting the held data to the image bus 28 via the output terminal, and the output device to the data input via the image bus 28. 24
Buffer 16a1 as an output holding means for outputting to
(Connected to the image bus 28 via the input end)
Also, the image bus control unit 2 as a control means for performing the transfer on the image bus 28 and the control of the page memory 26.
It has 0.

Here, the output buffer 14a1 and the input device 22 are connected by the local data input bus 14L, and the output buffer 14a1 receives data from the input device 22 via the local data input bus 14L. Has become.

Further, the input buffer 16a1 and the output device 2
4 is connected by a local data output bus 16L, and the input buffer 16a1 outputs data to the output device 24 via the local data output bus 16L.

The image bus controller 20 controls the control signal line 2
The control signal line 20 is connected to the input / output buffer 12 via 0L1.
The control signal line 20 is connected to the output buffer 14a1 via L2.
Control signal line 20L4 to page memory 26 via L3
To the input buffer 16a1 via the control signal line 20L5
1 to the data processing unit 18a1 via the control signal line 20L
These are controlled by outputting predetermined signals to the data processing unit 18a2 via 52.

Next, the image bus controller 20 will be described in detail. As shown in FIG. 2, the image bus control unit 20 includes an input / output control unit 32, an output device control unit 34, a processing unit control unit 36, a memory control unit 38 including a microcomputer, and an arbiter 40. Has been done.

When the CPU (or DMA master) receives a data transfer request signal (XREQ) from the outside of the image bus 28, the input / output controller 32 receives the arbiter 40.
To the transfer request signal (LXLEQ) and waits. Then, the transfer enable signal (DMAC
YC) is input, this transfer enable signal (DMACY
A control signal for controlling the input / output buffer 12 is generated in response to the input of (C). This control is called BB control, and BB is a bus buffer (Bus-Buffer).
It means the input / output buffer 12 in the meaning of r). Further, the input / output control unit 32 generates a response signal (XRDY) for notifying the CPU (or the DMA master) outside the image bus 28, which is the main operator, of the transfer end. The unit of access to the page memory 26 from the outside of the image bus 28 controlled by the input / output control unit 32 is executed by the data width of the input / output buffer 12.

The output device control section 34 controls the horizontal synchronizing signal (LineSyn) which is a timing signal from the output device 24.
c) and the vertical synchronization signal (PageSync), the transfer request signal (RBREQ) to the arbiter 40.
And then wait. Then, when the transfer permission signal (SODCYC) is received from the arbiter 40, the transfer permission signal (SODCYC) is input,
A control signal for controlling the input buffer 16a1 is generated.
This control is called RB control, and RB means the input buffer 16a1 in the sense of a read buffer. The unit of access to the output device 24 controlled by the output device control unit 34 is executed by the data width of the input buffer 16a1.

The processing unit control unit 36 controls the input buffer 16a.
2 and the compression processing unit 1 connected to the output buffer 14a2
8a1, the input buffer 16a3, and the output buffer 14
The expansion processing unit 18a2 connected to a3 is controlled.

Here, the processing unit control unit 36 controls the compression processing unit 1
The signals output to the 8a1 and the expansion processing unit 18a2 include a signal for each of the compression processing unit 18a1 and the expansion processing unit 18a2 and a signal common to both the compression processing unit 18a1 and the expansion processing unit 18a2.

Input buffer 16a2 or input buffer 1
A signal meaning that there is no data in 6a3 (SBE
MPTY) or the signal (DBFULL) indicating that the output buffer 14a2 or the output buffer 14a3 is full of data is received from either the data processing unit 18a1 or the data processing unit 18a2, the processing unit control unit 36 16a2, 16a3 transfer request (SBREQ) or output haffer 14a2, 1
Arbiter 40 sends a transfer request (DBREQ) to 4a3.
Output to and wait. When the transfer permission signal (CMPCYC) is received from the arbiter 40, the end is notified by outputting the ENDMPMP signal to the arbiter.

Of these signals, SBEMPTY, D
There are two systems of BFULL, SBREQ, and DBREQ for each of the compression processing unit 18a1 and the expansion processing unit 18a2. However, COMPCYC and ENDCOM
There is only one strain of P. DBREQ and SBREQ are the logical OR of request signals for two processes, compression and decompression. Then, in order to distinguish between compression and decompression, the SODREQ signal is added only to the decompression request, and SODCY is added as a response signal from the arbiter
C signal is added.

The memory control unit 38 receives the cycle enable signal from the arbiter 40 and the decode signal (M
EMCYC, SOLCYC, DMACYC, COMPC
YC, REFCYC) and outputs various timing signals to be described later, and then outputs a cycle end signal (ENDREF, ENDMEM.ENDCOM) to the arbiter 40.
P) is output. That is, for example, the memory control unit 38
Owns a refresh counter, and when this counter becomes a full counter, a refresh request (REFRE
Output Q) and wait. When the permission signal (REFCYC) is received from the arbitration unit, a refresh cycle is triggered by the received signal and an end signal (ENDREF) is output. These cycle enable and cycle type decode signals are output signals output by the arbiter managing the image bus. Further, the memory control unit 38 controls the page memory 26 with control signals (RAS, CAS, WE,
MEMADR), control signals (BMOE, BMLT) for the input / output buffer 12, and data processing units 18a1 and 18a
a2 control signals (SBRDY, DBRDY) or input buffer 16a1 control signals (RBL
T) is output.

As described above, the arbiter 40 includes the input / output device controller 32, the output device controller 34, and the processor controller 3.
6. Receive the transfer request signal from each of the memory control units 38, and perform arbitration so that the transfer to the output device 24 has the highest priority. The output of the arbiter 40 is a signal (SODCY) indicating the type of cycle to each control unit.
C, DMACYC, MEMCYC, COMPCYC ...
...) is output as a discharge for a certain period of time.

Now, the above-mentioned signals for executing each cycle will be described with reference to FIG. First, each signal input to the memory control unit 38 will be described.

REFCYC is input from the arbiter 40, which indicates that the refresh cycle is enabled on the image bus when "REFCYC is 1". ENDREF from the memory control unit 38 is the arbiter 4
The arbiter 40 keeps this signal RE until asserted to 0.
Hold FCYC = 1.

MEMCYC is input from the arbiter 40, which indicates that a memory cycle is permitted on the image bus when "MEMCYC is 1".

SODCYC is input from the arbiter 40, and when "SODCYC is 1" indicates that the data transfer cycle to the output device 24 for printing is permitted on the image bus.

COMPCYC is input from the arbiter 40, and when "CMPCYC is 1", it indicates that a cycle for compression / expansion processing is permitted on the image bus.

DMACYC is input from the arbiter 40, and when "DMACYC is 1" indicates that the data transfer cycle for writing to the page buffer is permitted on the image bus.

Next, each signal output from the memory controller 38 will be described. ENDREF is output to the arbiter 40, which notifies the arbiter 40 that the refresh cycle has ended when "ENDREF is 1".

The ENDMEM is output to the arbiter 40, which notifies the arbiter 40 that the memory cycle has ended when "ENDMEM is 1".

ENDCMP is output to the arbiter 40, which notifies the arbiter 40 that the cycle for the compression / expansion processing has ended when "ENDCMP is 1".

BMOE is output to the input / output buffer 12, which is an output enable signal for the input / output buffer 12, and the input / output buffer 12 receiving "0" of this signal outputs the data on the image bus. To do.

SBRDY is output to the compression processing section 18a1 and the expansion processing section 18a2, which is a timing control signal for data transfer to the compression processing section 18a1 and the expansion processing section 18a2 for compression or expansion processing. The compression processing unit 18a1 and the decompression processing unit 18a2, to which "0" of this signal is input, input buffers 16a2 and 1a so as to latch the data on the image bus 28 at a predetermined timing.
6a3 is controlled.

DBRDY is output to the compression processing unit 18a1 and the expansion processing unit 18a2, which is a data output timing control signal for the compression processing unit 18a1 and the expansion processing unit 18a2 for compression or expansion processing.
0 "received compression processing unit 18a1 and decompression processing unit 18a2
Controls the output buffers 14a2 and 14a3 so as to output the data onto the image bus 28 at a predetermined timing.

RAS, CAS and ME are page memories 3
6, which are a row address strobe signal, a column address strobe signal, and a write enable signal, respectively.

Next, the operation of this embodiment will be described. First,
The control routine of the arbiter 40 will be described with reference to the flowchart shown in FIG.

In the present embodiment, the data to be output to the output device 24 is received from the outside of the image bus 28, temporarily stored in the page memory 26, then read out and serially transmitted to the output device 24. At that time, in addition to compression / expansion as a process, writing the data to the page memory 26 does not mean that the data from the outside of the image bus is directly written to the memory, but is temporarily compressed.
It is written in the page memory 26 after being compressed by a1.

Similarly, at the time of decompression, the data read from the page memory 26 is not directly output to the output device 24, but is temporarily decompressed by the decompression processing unit 18a2 and then output to the output device 24.

In this embodiment, since the compression and the expansion are performed at the same time, the following five data transfer cycles compete with each other. First, the outline of each cycle is shown below.

Data Transfer from Output Buffer 14a3 to Input Buffer 16a1 This data transfer is performed when the data expanded by the expansion processor 18a2 is stored in the output buffer 14a3 and the output buffer 14a3 is full of data. The data is output to the input buffer 16a1 for output to the output device 24.

From page memory 26 to input buffer 16
Data Transfer to a3 This data transfer is to input the compressed data to be expanded by the expansion processor 18a2 from the page memory 26.

The above-mentioned data transfer is paired and the expansion processing is performed. Refresh A refresh cycle unique to the page memory 26 (DRAM).

Data Transfer from Output Buffer 14a2 to Page Memory 26 In this data transfer, the data after compression by the compression processing section 18a1 is stored in the output buffer 14a2, and when the output buffer 14a2 is full, the page memory 26 is full. The data is output to.

Input / output buffer 12 to input buffer 1
Data Transfer to 6a2 This data transfer is to transfer the held data from the input / output buffer 12 which holds the data transferred from the CPU via the system bus to the input buffer 16a2.

The above-mentioned data transfer is paired and compression processing is performed. Next, it will be shown what priority order the above five types of data transfer cycles should be arbitrated. As mentioned above, the competition of these five types of cycles must be arbitrated under the characteristic limitation of the output device 24. The limitation is that the data transfer rate to the output device 24 is constant and that the page memory 2
That is, the page memory 26 has to be refreshed at regular intervals in order to guarantee the memory retention of No. 6.

In the present embodiment, the data transfer to the output device 24 directly corresponds to the data transfer. Therefore, the cycle of data transfer should have higher priority than all cycles. Then, in order for the data transfer to achieve a constant speed, the data transfer paired with this must obtain the next priority. In this sense, the data transfer cycle is indirectly performed by the output device 24.
Corresponds to the data transfer to. Then, these data transfer cycles always have priority over the other three types of cycles.

The leftmost end of the flowchart shown in FIG. 4 shows the data transfer cycle, and the adjacent one shows the data transfer cycle. In addition, → in the execution statement indicates assignment
On the actual circuit, the flip-flop output transits to the level indicated.

First, in step 102, it is determined whether or not RBREQ has been recognized. That is, for example, as shown in FIG. 6, from the output device control unit 34 which receives the vertical synchronization signal PS and the horizontal synchronization signal LS from the output device 24,
If REQ is output, the determination at step 102 is affirmative and the routine proceeds to step 104.

Further, as shown in FIG. 6, for example, the decompression processing unit 18a2 which detects that the output buffer 14a3 connected to the decompression processing unit 18a2 is full of data.
The processing unit control unit 36 that inputs DBFULL from
The REQ is output to the arbiter 40. At the same time, the processing unit control unit 36 outputs SODREQ to the arbiter 40 in order to identify the decompression process. As a result, the determinations at step 104 and step 108 are affirmed, and at step 112, SODYC and CMPCYC
Is changed to 1 and SOCYCYC and CMP are changed to 1.
CYC is output to the memory control unit 38 and the SOD
CYC is output to the processing unit control unit 36.

As a result, the data output from the output buffer 14a3 is transferred to the image bus 28, as will be described later.
Data is transferred to the input buffer 16a1 via (see the data transfer path in FIG. 8). When this data transfer is completed, the memory control unit 38 outputs ENDCOMP to the arbiter.

Therefore, in step 114, ENDCOM
By determining whether or not P is recognized, it is determined whether or not the compression processing has been completed and the decompressed data has been transferred to the input buffer 16a1. SO to return to the state
DCYC and CMPCYC are transited to 0, and the process returns to step 102.

On the other hand, as described above, the output device controller 3
4 (see FIG. 6), RBREQ is input from the processing unit control unit 36 that inputs SBEMPTY from the decompression processing unit 18a2 that detects that there is no more data in the input buffer 16a3, and when SBREQ and SODREQ are input, step 102, The determination at step 104 is affirmed, the determination at step 108 is denied, and the determination at step 110 is affirmed.

In this case, in step 118, the SOD
CYC and MEMCYC are transited to 1, the MODCYC and MEMCYC which have transited to 1 are output to the memory control unit 38, and the SODCYC is output to the processing unit control unit 36.

As a result, the data stored in the page memory 26 is read and transferred to the input buffer 16a3 (see the data path in FIG. 8). Upon completion of the data transfer process, the memory control unit 38 outputs ENDMEM to the arbiter 40.

Then, in step 120, ENDMEM.
The data stored in the page memory 26 is read by determining whether or not the input buffer 1 has been recognized.
6a3, if ENDMEM is recognized, in step 122, to return to the initial state, SODCYC and MEMCYC are transited to 0,
Return to step 102.

As described above, the arbiter 40 is in a state where there is no data in the input / output buffer 16a1 (read buffer) (RBREQ is active), or one of the input buffers 16a3 (decompression buffer) requests transfer. When in the state (SODREQ is active),
Prioritizes data transfer cycles (step 10
2, step 104 (step 106 described later)).

Further, in this state, the data transfer cycle or which cycle is actually requested is
It is determined whether the output buffer 14a3 is full and wants to output data (DBREQ is active) or the input buffer 16a3 is empty and wants to input data (SBREQ is active) (step 108). , Step 110).

Since the determination of DBREQ comes first, the priority of the data transfer cycle is guaranteed. Further, while the data transfer cycle is permitted, the cycle request is masked for all cycles including the data transfer cycle, but as soon as the data transfer cycle is completed, the process returns to step 102 and all There is a possibility that the right will be passed to the cycle.

By arbitrating in this way, the output device 2
The transfer speed to 4 can always be guaranteed. Since all cycles are buffer transfer, even if a data transfer cycle occurs on the image bus, data transfer to the output device 24 outside the image bus 28 or transfer to the input / output buffer 12 on the system bus is performed. Etc. can be executed in parallel. The execution of these cycles outside the image bus is controlled by the respective control units.

Further, the arbiter 40 does not output a control signal for the actual page memory 26 or a timing signal such as a latch for each buffer, but merely a signal for notifying another control unit which cycle is permitted. Output only. SODCYC indicates a cycle for decompression, and CMPCYC indicates a cycle without the page memory 26. Receiving these signals, the control units receive the target page memories 2 already described.
6 and the timing signal of the control signal for each buffer are output.

Next, the refresh cycle which is another limitation will be described. This refresh cycle has a third priority. It is located at the center in the flowchart shown in FIG.

That is, RB from the output device controller 34
If the REQ is not recognized, the determination at step 102 is denied, and it is determined at step 106 whether or not the SODREQ is recognized. If the determination is affirmative, it is necessary to perform decompression processing, so the processing returns to step 102 and the above processing (steps 102 to 122) is repeated.

If the determination in step 106 is negative, it means that the decompression process or the refresh cycle needs to be performed. In step 124, it is determined whether or not REFREQ is recognized from the memory control unit 38. , Determine whether a refresh cycle needs to be performed. If the determination is affirmative, the REFCY is determined in step 126 to allow the refresh cycle.
Transition C to 1. That is, it is a signal indicating that REFCYC has permitted refresh.

As a result, the page memory 26 performs a refresh cycle under the control of the memory controller 38. When the refresh cycle is completed, ENDREF is input from the memory control unit 38, so that step 1
In step 28, it is determined whether or not ENDREF is recognized. If the determination is affirmative, in step 130, REFCYC is returned to 0 to return to the initial state, and step 102
Return to

As described above, the refresh cycle has the third highest priority, but the arbitration for the page memory 26 is generally the highest priority for refresh. However, in order to support the special application of the output device 24 here, it is dropped third for the arbiter 40.

The time required for refreshing is the maximum of the execution times of the cycles of data transfer in which data transfer to output device 24 is not performed. However, since the cycle in this embodiment is completed in a very short time of transfer to the buffer, there is no problem of being out of spec.

Next, the data transfer cycle will be described. This data transfer cycle is handled as a cycle group that does not require speed guarantee. In the flowchart shown in FIG. 4, the data transfer cycle is located at the rightmost end, and the data transfer cycle is adjacent to it. Here, DMACYC is a permission signal for compression.

The compression process itself has nothing to do with the speed of the output device 24, and therefore should not be guaranteed in terms of speed. The relationship of the data transfer cycle is
The data transfer cycle is prioritized over the data transfer cycle.

That is, when the determination in step 124 is negative, it is determined in step 132 whether LXREQ has been recognized. That is, as shown in FIG.
The input / output control unit 32 that receives the XREQ from the U is LXR
The EQ is output to the arbiter 40. Therefore, in this case, the determination at step 132 is affirmative, and at step 134 D
It is determined whether or not BREQ is input.

For example, the compression processing unit 18a1 which detects that the output buffer 14a3 is full of data is D
BFULL is output to the processing unit control unit 36. DBFUL
The processing unit control unit 36, which has input L, stores the DB in the arbiter 40.
Output REQ. Therefore, in this case, step 1
34 is affirmative, and in step 136, DMACY
Transition C and MEMCYC to 1.

As a result, the compressed data is transferred from the output buffer 14a2 to the page memory 26 via the image bus 28 and written therein (see the data path in FIG. 8). In this way, when the data from the output buffer 14a2 is written to the page memory 26, the image control unit 38 outputs ENDMEM.

Then, in step 138, ENDMEM
It is determined whether or not the data from the output buffer 14a2 has been written in the page memory 26 by determining whether or not is recognized. If the determination is affirmative, in order to return to the initial state, DMACYC and MEMCYC are returned to 0 in step 140, and this processing ends.

On the other hand, when the determination in step 134 is negative, it is determined in step 142 whether SBREQ has been recognized. That is, it is determined whether or not SBEMPTY is input from the compression processing unit 18a1 that detects that there is no more data in the input buffer 16a2.

If the determination is affirmative, step 1
At 44, DMACYC and CMPCYC are transited to 1. As a result, the data is transferred from the input / output buffer 12 holding the data input from the CPU to the input buffer 16a2 via the image bus 28 (see the data transfer path in FIG. 8). Then, when the data transfer is completed, the memory controller 38 outputs ENDCMP.

Then, in step 146, ENDCMP
It is determined whether or not the data input from the CPU is transferred from the input / output buffer 12 to the input buffer 16a2 by determining whether or not is recognized.

If the determination is affirmative, step 1
At 48, to return to the initial state, DMACYC and CMP
CYC is reset to 0, and the process returns to step 102.

In the control routine of the arbiter 40 described above, there is a cycle if the conditions of the data transfer cycle, the refresh cycle, and the data transfer cycle are satisfied at any time. In other words, the higher the bandwidth of the image bus 28 of this embodiment, the higher the possibility that the cycle will be executed.

In other words, if the price is to be kept low, it is possible to construct a system that does not require much bandwidth, and an appropriate bandwidth is required in order to realize simultaneous execution. In the simultaneous execution of compression / expansion, it is sufficient to realize a transfer speed which is about 2 to 3 times that of the printer, although it depends on the configuration of the peripheral circuit. In this way, the system performance can be changed depending on the bandwidth, and the number of processes that can be added can be changed accordingly.

Next, the control routine of the memory control unit will be described with reference to the flow chart shown in FIG.

In this flowchart, the execution unit surrounded by a square is executed every clock. Also, I
The DLE display shows that there is no signal transition in the execution unit and some signal change is seen after the next clock.

First, for the memory controller 38, the cycle having the highest priority is the refresh cycle.
In order to guarantee this operation, the memory control unit 38 first determines whether or not REFCYC, which is an input from the arbiter 40, is active as the first selection for determining its own cycle to be executed at that time.

That is, in step 152, REFCY
It is determined whether C is recognized. When the refresh counter reaches the full count and outputs REFREQ to the arbiter 40 and recognizes the REFCYC output from the arbiter 40, the determination in step 152 is affirmed. In this case, in step 154, the refresh (REFRES
H) Execute cycle. As the type of refresh cycle, it is assumed that the CAS before RAS is temporarily used from a plurality of refresh modes possessed by the DRAM device itself. The changes over time are as follows.

At the first clock cycle, CAS is changed from level "1" to "0". In the next clock cycle, RAS is transited from level "1" to "0". In the next clock cycle, CAS is transited from the level "1" to "0". At the next clock cycle, RA
Transition S from level "1" to "0" and END
REF is changed from level "0" to "1". Then, at the next clock cycle, ENDREF goes to level
Transition from "1" to "0".

In this way, the output is for the page memory and the cycle end signal for the arbiter is output. Upon receiving this ENDREF, the arbiter recognizes that the current image bus field cycle has ended,
Permit use of image bus for next cycle.

Further, in this flowchart, the image bus 28 cannot be used while the refresh cycle is being executed, but since the page memory 26 cannot be used at the time of refreshing, the image bus 28 exists as an access on the image bus 28. However, in this configuration, even if the refresh is executed, the buffer has a function as a speed warming device, so that it waits at most about 5 clock cycles and no speed problem occurs.

When the refresh cycle ends, the next cycle becomes possible after one clock idle cycle (clock cycle in which nothing is done).

Similarly, when REFCYC is in the inactive state and the refresh cycle is not executed first, the other cycles are executed without idle.

The execution start condition of the other cycle is MEMC.
It is defined by YC, COMCYC, SODCYC, and DMACYC. The condition determination of the cycle start is achieved within one clock cycle. When all these conditions are not met, it becomes an idle cycle and the output signal becomes
It will not change at all.

Next, the cycles other than refresh will be described. The four cycles located in the lower stage of the flowchart are composed of a cycle using the page memory 26 connected to the image bus 28 and a cycle not using the page memory 26.

The two on the left side are the cycles in which the page memory 26 is actually used. Of these two types of cycles,
The leftmost position is data transfer from the page memory 26 to the input buffer 16a3 during decompression processing (see the data transfer path in FIG. 8). On the right side is data transfer from the output buffer 14a2 to the page memory 26 during compression processing (see the data transfer path in FIG. 8).

The two on the right side are the cycles on the image bus 28 that do not use the page memory 26. The rightmost of these two types of cycles is from the input / output buffer 12 to the input buffer 16a2. Data transfer is performed (data transfer path in FIG. 8), and the left side is data transfer from the output buffer 14a3 to the input buffer 16a1 during decompression processing (data transfer path in FIG. 8).

As described above, when RBREQ is input from the output device control unit 34 (see FIG. 6) and SBREQ and SODREQ are input from the processing unit control unit 36, the arbiter 40 causes the SODYC and MEMCYC to be input to the memory control unit 38. Output to. In this case step 156
And the determination in step 160 is affirmative, and step 162
Then, the process of reading the data from the page memory 26 and transferring it to the input buffer 16a3 is performed (see the data transfer path in FIG. 8).

That is, first, RAS is transited to 0. CAS and SBRDY are set to 0 at the next clock cycle.
Transition to. In this way, when RAS is transited to 0 and then to CAS0, data is read from the page memory and transferred onto the image bus 28.

On the other hand, when the SBRDY that has transited to 0 is input, the decompression processor 18a2 stores in the input buffer 16a3.
An instruction is given to fetch the data on the image bus 28. As a result, the data on the image bus 28 is held in the input buffer 16a3.

Since RAS, CAS and SBRDY are returned to 1 and data is transferred from the page memory 26 to the input buffer 16a2 in order to return to the initial state after 1 clock idle cycle from the time when SBRDY is transited to 0. ENDMEM is changed to 1 in order to notify that, and then ENDMEM is changed to 0 in order to return to the initial state.
, And returns to step 152.

On the other hand, if the determination at step 156 is positive and the determination at step 160 is negative, then at step 164 it is determined whether DMACYC is recognized. That is, as shown in FIG. 7, the LXREQ is input from the input / output control unit 32 and the processing unit control unit 36 inputs, for example, the DBCY from the arbiter 40 that inputs DBREQ.
It is determined whether or not C is input. If the determination is affirmative, in step 166, the data is transferred from the output buffer 14a2 to the page memory 26 and written in the page memory 26 (see the data transfer path in FIG. 8).

That is, first, RAS and DBRDY are transited to 0. When DBRDY transited to 0 is input, the compression processing unit 18a1 gives the output buffer 14a2 an instruction to output data onto the image bus 28.

At the next clock cycle, WE transits to 0 and DBRDY returns to 1. As a result, the data output from the output buffer 14a2 onto the image bus is written in the page memory 26.

In the next clock cycle, CAS is transited to 0, and in the next clock cycle, it returns to the initial state.
ENDMEM is transited to 1 to return AS, WE, and CAS to 1 and to indicate that the data transfer is completed. Then, in order to return to the initial state in the next cycle, EN
Return DMEM to 0.

On the other hand, if the determination at step 156 is negative, then at step 158, COMPCYC
Is recognized, and it is determined in step 168 whether SODCYC is recognized. That is, as shown in FIG. 6, RBREQ is input from the output device control unit 34 and, for example, DBREQ and SODREQ are input from the processing unit control unit 36.
The arbiter 40 that has input is COMPYC and SOD
Output CYC. Thus, from the arbiter 40 to CO
Enter MPCYC and SOLCYC, then step 1
58 and step 168 are affirmative, step 1
At 70, the output buffer 14a3 to the input buffer 16a
Data transfer processing to 1 is performed (see the data transfer path in FIG. 8).

That is, first, DBRDY is transited to 0. In this way, the decompression processing unit 18a2, which has received the DBRDY transitioned to 0, gives an instruction to output data from the output buffer 14a3 onto the image bus 26. As a result, the data is output from the output buffer 14a3 onto the image bus 26.

DBRDY is returned to 1 in the next cycle. In the next cycle, RBLT is transited to 0 and ENDDCMP is transited to 1 to notify that the data transfer is completed. When the RBLT that has transited to 0 in this way is input, the input buffer 16a1 takes in the data on the image bus 26. As a result, the data output from the output buffer 14a3 onto the image bus 26 is taken into the input buffer 16a1 (see the data transfer path in FIG. 8).

Then, in the next cycle, in order to return to the initial state, RBLT is returned to 1, ENDCMP is returned to 0, and the process returns to step 152.

On the other hand, if the determination in step 168 is negative, it is determined in step 172 whether DMACYC is recognized.

That is, as shown in FIG. 7, LXREQ is input from the input / output control unit 32 and the processing unit control unit 3
From 6, for example, the arbiter 40 inputting SBREQ
Displays the DMACYC and COMPCYC in the memory control unit 38.
Output to. Accordingly, the determination in step 158 is affirmative, the determination in step 168 is negative, and the determination in step 1
The judgment at 72 is affirmed. In this case, the process of transferring the data from the input / output buffer holding the data input from the CPU to the input buffer 16a2 via the image bus 28 is performed (see the data transfer path in FIG. 8).

That is, first, SBRDY is transited to 0 and BMOE is transited to 0. In this way, when the SBRDY transitioned to 0 is input, the compression processing unit 18a1
Gives an instruction to the input buffer 16a2 to take in the data on the image bus 28.

Here, the input / output control unit 32 inputs the DMACYC from the arbiter 40 as described above,
The BB control for controlling the input / output buffer 12 to fetch the data from the CPU is performed. Therefore, the input / output buffer 12 fetches and holds the data from the CPU. When the BMOE output from the memory control unit 38 and transiting to 0 is input, the input / output buffer 12
Outputs the held data (data fetched from the CPU) onto the image bus.

As a result, the data output from the input / output buffer 12 is transferred to the input buffer 16a2 via the image bus 26 (see the data transfer path in FIG. 8).

In the next cycle, SBRDY is returned to 1 and E is sent to notify that the data transfer is completed.
Transition NDCP to 1.

Then, in the next cycle, in order to return to the initial state, BMOE is returned to 1, ENDDCMP is returned to 0, and the process returns to step 152.

FIGS. 9 and 10 show timing charts when the above-described data transfer cycle, ... Is executed. In FIG. 9, the compression processing unit 18
a1, the input buffers 16a2, 1 of the expansion processing unit 18a2
The timing of data transfer to 6a3 is shown.

The memory controller 38 outputs the page memory 26, so that the data is fixed on the image bus 28 at the rising edge CLK ₀ of the next clock when SBRDY is output by itself.
It controls the compression processing unit 18a1, the expansion processing unit 18a2, and the input buffer 16a1. Two timings are taken up here, one is a data transfer path and the other is a data transfer path.

In other words, the compression processing unit 18a1 and the decompression processing unit 18a2 do not need to be aware of the timing of the transfer source device when inputting data on the image bus 28, and always recognize the SBRDY and rise of the next clock. This means that it is sufficient to take in the data at CLK ₀ .

FIG. 10 shows the timing of data transfer to the output buffers 14a2 and 14a3 of the compression processing unit 18a1 and decompression processing unit 18a2. The memory control unit 38 outputs data from the output buffers 14a2 and 14a3 during the next rising edge CLK ₁ of the next clock and the next rising edge CLK ₂ of the clock when DBRDY is output. Data transfer is covered here.

In other words, the compression processing unit 18a1 and the decompression processing unit 18a2 do not need to be aware of the transfer destination device when outputting data on the image bus 28.
It means that the data should be output between the rising edge CLK ₁ of the clock next to the clock that recognizes RDY and the rising edge CLK ₂ of the next clock.

Next, a second embodiment of the present invention will be described.
The configuration of this embodiment is the same as the configuration of the first embodiment described above, and therefore its description is omitted. As described above, the present embodiment has the same configuration as that of the first embodiment and takes another data path.

The present embodiment is used for diagnostic purposes. That is, the decompression processing unit 18a2 operates in the same manner as usual, but by changing the transfer destination on the image bus 28 under the control of the memory control unit 38, the decompression processing unit 18a2 is operated for another diagnostic purpose. It is possible to use. As a result, the data transfer, which should normally be one-way toward the output device 24, is realized in the opposite direction (see the data transfer path 'in FIG. 11).

In this case, as shown in FIG. 12, the decompression processing unit 18a2 does not need to be aware of the transfer destination device when outputting the data on the image bus 28, and the DB is always
The rising edge CLK of the next clock after recognizing RDY
It means that you can output the data in ₂ .

Next, a third embodiment of the present invention will be described.
In this embodiment, as shown in FIG. 13, the compression processing unit and the decompression processing unit in the configuration of the first embodiment described above are not interposed. The data transfer cycle in this case is data transfer from the input / output buffer 12 to the page memory 26, refresh and data transfer from the page memory 26 to the input buffer 16a1.

In this case, this is the data transfer itself to the printer. The priority decreases in the order of data transfer cycle, refresh cycle, and data transfer cycle. In this embodiment, SODREQ, SBREQ, DBRE which are cycle identification signals for compression / expansion processing.
Q is not needed here. The band width of the image bus 28 at this time may be smaller than that in the case where the compression and expansion are performed. This is because the number of cycles is reduced by two, and the bandwidth can be reduced.

By the way, in order to realize the case with and without the compression / expansion by the same arbiter, a register mechanism that can be set from the system bus is provided in the image bus control unit and one bit in the register is compressed. It is possible to express it as a bit indicating the presence or absence of the input, and input this to the arbiter to give the arbiter a plurality of operations. Note that this function is not necessary if either the function with or without compression / decompression is used fixedly.

First, the arbiter 40 when there is no compression processing.
The control routine of is described with reference to FIG.

In step 202, it is determined whether or not RBREQ has been recognized. If the determination is affirmative, in step 204, SOLCYC and MEMCYC are transited to 1. As a result, the memory control unit 38 executes the data transfer cycle. When this process ends, the memory control unit 38 outputs ENDMEM to the arbiter 40.

Then, in step 206, ENDMEM
Is recognized, and if it is recognized, in step 208, to return to the initial state, SODCYC and ME are returned.
MCYC is reset to 0 and the process returns to step 202.

On the other hand, when RBREQ is not recognized in step 202, REFRE is determined in step 210.
It is determined whether or not Q is recognized, and if it is recognized, step 212 is performed to allow the refresh cycle.
Then, REFCYC is changed to 1. As a result, Ref
When the resh cycle is executed and when the cycle ends, ENDREF is input from the memory control unit 38. Therefore, in step 214, it is determined whether or not ENDREF is recognized. If the determination is affirmative, step 21
In step 6, REFCYC is returned to 0 to return to the initial state, and the process returns to step 202.

Further, in step 210, REFREQ
If not recognized in step 218, LXR
It is determined whether or not the EQ is recognized. When the determination is affirmative, DMACYC and MEMCYC are transited to 1. As a result, the memory control unit 38 executes the data transfer cycle. When this process ends, the memory control unit 38 outputs ENDMEM to the arbiter 40.

Therefore, in step 222, ENDMEM
Is recognized, and if it is recognized, in step 224, DMACYC and ME are returned to return to the initial state.
MCYC is reset to 0 and the process returns to step 202.

Next, the control routine of the memory controller 38 will be described with reference to FIG. First, in step 152,
It is determined whether REFCYC is recognized. If the determination is affirmative, the Refresh cycle is executed in step 154, and the process returns to step 152.

On the other hand, if the determination in step 152 is negative, it is determined in step 232 whether or not MEMCYC is recognized. If the determination is negative, the process returns to step 152 and the determination is made. If affirmative, write data to the page memory 26 or
Step 2 to determine whether to read data from
In S34, it is determined whether or not SODCYC is recognized. If the determination is affirmative, it means that the data is written in the page memory 26. Therefore, in Step 236, the data transfer cycle is executed, and then in Step 152. Return.

On the other hand, if the determination in step 234 is negative, it is determined in step 238 whether or not DMACYC is recognized. If the determination is positive, the data can be read from the page memory 26. Therefore, in step 240, the data transfer cycle is executed, and the process returns to step 152.

Incidentally, FIG. 16 shows a timing chart of this embodiment. As shown in FIG. 16, in the data transfer cycle, the BMOE is stored in the input / output buffer 12.
Data is written in the page memory 26 between the rising edge CLK ₁ of the next clock and the rising edge CLK ₂ of the next clock when the (instruction signal for transferring the data held from the input / output buffer 12) is changed to 0. It is controlled so that

In the case of a data transfer cycle,
By transitioning RBLT to 0 between the rising edge CLK ₁ of the next clock and the rising edge CLK ₂ of the next clock when the data is read from the page memory 26, the data is taken into the input buffer 16a1. Have control.

Data transfer for reading data from the page memory 26 and transferring it to the input / output buffer 12.
Also, B is stored in the I / O buffer 12 between the rising edge CLK ₁ of the next clock and the rising edge CLK ₂ of the next clock when data is read from the page memory 26.
MOE (instruction signal for latching data on the image bus 28) is set to 0.

As described above, the memory control unit 38 sends the data transfer, ', to the control signals (BMOE, RAS, C).
It is executed by outputting (AS, WE, RBLT) to the input / output buffer 12, the page memory 26 and the input buffer 16a1. That is, the input / output buffer 12, the page memory 26, and the input buffer 16a1 do not need to be aware of the transfer destination device when outputting data to the image bus 28.

Next, a fourth embodiment of the present invention will be described.
In the above-described embodiments, the processes of compression and decompression have been described as embodiments. However, in the present embodiment, resolution conversion is performed.

As shown in FIG. 17, the structure of this embodiment is as follows.
The input buffer 16a3, the decompression processing unit 18a2, and the output buffer 14a3 of the first embodiment described above are omitted, and the resolution conversion processing unit 18 is used instead of the compression processing unit 18a1.
a3 is provided.

Next, the operation of this embodiment will be described. In this embodiment, the data fetched from the CPU is used as the input / output buffer 12, the input buffer 16a2, and the resolution conversion processing unit 18.
a3 and output buffer 14a2, and then page memory 2
6, a resolution conversion process for writing data to the memory 6, a read process for reading the resolution-converted data stored in the page memory 26, and a refresh cycle.

In this embodiment, simple thinning is executed as the resolution conversion. Simple thinning out is, for example, 6
When you want to drop 00 dpi data to 300 dpi,
The original data is simply used every other dot (one dot is thinned out every two dots). In addition, 600d
It is not limited to dropping the data of pi to 300 dpi, and the data of 600 dpi is, for example, 200 dpi.
Alternatively, it may be dropped to 100 dpi.

As will be described later, the data from the system bus is once resolution-converted (for example, after being converted into a half data amount) and stored in the page memory 26, and then read from the page memory 26 and output. Device 24. As for the priority at that time, reading is the highest priority,
Subsequently, refresh, data transfer from the output buffer 14a2 to the page memory 26, and the input / output buffer 1
The order of data transfer from 2 to the input buffer 16a2 is as follows.

First, the control routine of the arbiter 40 is shown in FIG.
This will be described with reference to FIG. At step 302, RBREQ
Is determined, and if the determination is affirmative, in step 304, SODCYC and MEMCYC
To 1. As a result, the memory control unit 38 performs a read process of reading data from the page memory 26. When the processing is completed, the memory control unit 38 outputs ENDMEM to the arbiter 40 to notify that the processing is completed.

Then, in step 306, ENDMEM
Is determined, and if the determination is affirmative, in step 308, the SODC is returned to the initial state.
YC and MEMCYC are reset to 0, and the process returns to step 302.

On the other hand, when the determination in step 302 is negative, it is determined in step 310 whether SODREQ has been recognized. If the determination is affirmative, it is necessary to perform the above-mentioned reading process, and therefore, step 30
Return to 2.

On the other hand, if the determination in step 310 is negative, it is determined in step 312 whether REFREQ has been recognized. If the determination is affirmative, REFCYC is transited to 1 in step 314. As a result, the refresh cycle is permitted. Therefore, the memory control unit 38 changes the REFCYC transitioned to 1 to
When the refresh cycle is executed and the processing is completed, ENDREF is output to the arbiter 40.

Therefore, in step 316, ENDREF
Is determined, and if the determination is affirmative, in step 318, the REFC is returned to the initial state.
YC is reset to 0, and the process returns to step 302.

On the other hand, if the determination in step 312 is negative, it is determined in step 320 whether LXREQ has been recognized. When the determination is affirmative, it is determined in step 322 whether DBREQ has been recognized, and in step 330 it is determined whether SBREQ has been recognized.

When the output buffer 14a2 is full of data, DBREQ is input from the processing section control section 36. In this case, the determination at step 322 is affirmative, and at step 324, DMACYC and MEMCYC.
To 1. As a result, the process of transferring data from the input buffer 14a2 to the page memory 26 by the memory control unit 38 is executed. When the processing is completed, the memory control unit 38 outputs ENDMEM to the arbiter 40.

Then, in step 326, ENDMEM
It is determined whether or not is recognized, and if the determination is affirmative, DMACYC and MEMCY are returned to the initial state.
C is returned to 0 and the process returns to step 302.

On the other hand, when there is no more data in the input buffer 16a2, SBREQ is input from the processing section control section 36. In this case, the determination in step 322 is denied and the determination in step 330 is affirmed, and DMACYC and CMPCYC are transited to 1 in the next step 332. As a result, the process of transferring data from the input / output buffer 12 to the input buffer 16a2 by the memory control unit 38 is executed. When the processing is completed, the memory control unit 38 outputs ENDCMP to the arbiter 40.

Then, in step 334, ENDCMP
Is determined, and if the determination is affirmative, DMACYC and CMPCY are used to return to the initial state.
C is returned to 0 and the process returns to step 302.

Next, the control routine of the memory control unit 38 will be described with reference to the flowchart shown in FIG.

First, in step 152, it is determined whether or not REFCYC is recognized. If the determination is affirmative, the refresh cycle is executed in step 154 and the process returns to step 152.

On the other hand, if the determination in step 152 is negative, it is determined in step 342 whether DMACYC is recognized. If the determination is affirmative, it is necessary to perform resolution conversion processing, so in step 344,
It is determined whether MEMCYC is recognized. If the determination is affirmative, the instruction to transfer the data from the output buffer 14a2 to the page memory 26 has been received. Therefore, in step 346, the process of transferring the data from the output buffer 14a2 to the page memory 26 is executed. , Step 1
Return to 52.

On the other hand, when the judgment at step 342 is affirmative, if CMPCYC is recognized, the judgment at step 344 is denied and the judgment at step 348 is affirmed. In this case, since the instruction to transfer the data from the input / output buffer 12 to the input buffer 16a2 is received, the process of transferring the data from the input / output buffer 12 to the input buffer 16a2 is executed in step 350, and step 152 is executed. Return to.

Next, when DMACYC is not recognized in step 342, it is not necessary to perform the refresh cycle and resolution conversion processing, and it is necessary to perform the read processing for transferring the data from the page memory 26 to the read input buffer 16a1. There is. Therefore, in this case, in step 352, it is determined whether or not the SODCYC is recognized. If the determination is affirmative, in step 354,
It is determined whether MEMCYC is recognized. If the determination is affirmative, that is, the instruction to perform the read process of transferring the data to the read input buffer 16a1 is received from the page memory 26, the read process is performed in step 356, and the process returns to step 152.

Next, a fifth embodiment of the present invention will be described.
In the above-described fourth embodiment, resolution conversion is performed instead of compression and decompression processing, but in the present embodiment, color tone conversion processing is performed instead of compression and decompression processing. It is the one.

As shown in FIG. 20, the configuration of this embodiment is similar to that of the input buffer 16a of the first embodiment described above.
2, the compression processing unit 18a1 and the output buffer 14a2 are omitted, and a color tone conversion processing unit 18a4 is provided instead of the decompression processing unit 18a2.

Next, the operation of this embodiment will be described. The conversion by the lookup table is used as the color conversion for the convenience. That is, assuming that the gradation of one dye component of a color image is 8 bits, color conversion is to convert this value into another 8-bit value unique to the output device 24.

In this embodiment, the data fetched from the CPU via the system bus is temporarily stored in the page memory 26, then read from the page memory 26, subjected to color conversion, and then transferred to the output device 24. To be done. At this time, the priority order is from the output buffer 14a3 to the input buffer 1
Data transfer to 6a1 is the highest, followed by data transfer from page memory 26 to input buffer 16a3, refreshing, and data transfer (writing) from input / output buffer 12 to page memory 26.

First, the control routine of the arbiter 40 is shown in FIG.
This will be described with reference to FIG. First, in step 102, RB
It is determined whether or not REQ is recognized, and if the determination is affirmative, it is determined at step 104 whether or not SODREQ is recognized. If the determination is affirmative, it is necessary to perform color tone conversion processing. That is, output buffer 1
When the data is full in 4a3, DBREQ is input. In this case, the determination in step 108 is affirmative, and in step 112, SODCYC and CMPCYC are transited to 1. As a result, the memory control unit 38 changes the output buffer 14a3 to the input buffer 1
A process of transferring data to 6a1 is executed. When the processing is completed, the memory control unit 38 sends an E to the arbiter 40.
Output NDMCP.

Therefore, in step 114, ENDCMP
Is determined, and if the determination is affirmative, in step 116, the SODC is returned to the initial state.
YC and CMPCYC are reset to 0, and the process returns to step 102.

On the other hand, when there is no more data in the input buffer 16a3, SBREQ is input.
In this case, the determination in step 116 is affirmative, and in step 118, SOLCYC and MEMCYC are transited to 1. As a result, the process of reading data from the page memory 26 and transferring it to the input buffer 16a3 by the memory control unit 38 is executed. When the processing ends, the memory control unit 38 outputs ENDMEM to the arbiter 40.

Then, in step 120, ENDMEM
Is determined, and if the determination is affirmative, in step 122, the SODC is returned to return to the initial state.
YC and MEMCYC are reset to 0, and the process returns to step 102.

If the determination at step 102 is negative and the determination at step 106 is affirmative, it is necessary to perform the color tone conversion processing, so the process returns to step 102.

On the other hand, if the determination in step 106 is negative, the refresh cycle or write processing is performed.

Therefore, in step 124, REFREQ
If it is affirmed, the REFCYC is changed to 1 in step 126,
Allow refresh cycles. As a result, the memory control unit 38 executes the refresh cycle and outputs ENDREF to the arbiter 40 when the processing is completed.

Then, in step 128, ENDREF
Is determined, and if the determination is affirmative, REFCYC is returned to 0 to return to the initial state,
Return to step 102.

On the other hand, if the determination in step 124 is negative, it is determined in step 132 whether LXREQ has been recognized. If the determination is affirmative, neither the tone conversion processing nor the refresh cycle, the CPU
Since the data transfer enable signal has been input from the I / O buffer 12, data is transferred from the input / output buffer 12 to the page memory 26. Therefore, in step 136, DMACYC and MEM
Transition CYC to 1. As a result, the memory control unit 38
When the process of transferring data from the input / output buffer 12 to the page memory 26 by the is executed and the process is completed,
The memory control unit 38 outputs ENDMEM.

Therefore, in step 138, ENDMEM
Is determined, and if the determination is affirmative, the DMAC is returned to the initial state in step 140.
YC and MEMCYC are reset to 0, and the process returns to step 102.

Next, the control routine of the memory control unit 38 will be described with reference to the flow chart shown in FIG.

First, in step 152, it is determined whether or not REFCYC is recognized. If the determination is affirmative, the refresh cycle is executed in step 154 and the process returns to step 152.

On the other hand, if the determination in step 152 is negative, it is determined in step 402 whether DMACYC is recognized. If the determination is affirmative, it is necessary to perform the color tone conversion process, so in step 404, M
It is determined whether EMCYC is recognized. If the determination is affirmative, in step 406, the input / output buffer 1
The process of transferring the data from 2 to the page memory 26 is executed, and the process returns to step 152.

On the other hand, if the determination in step 402 is negative, then in step 408, it is determined whether SODCYC is recognized. If the determination is positive, the ME
Did you recognize MCYC (step 410), CMPCY?
It is determined whether C is recognized (step 414). As a result, whether there is an instruction to transfer data from the page memory 26 to the input buffer 16a3, or the output buffer 14a3
From the input buffer 16a1 is judged.

If the determination in step 410 is affirmative, it means that there is an instruction to transfer data from the page memory 26 to the input buffer 16a3, and step 412 is executed.
Then, the process of transferring the data from the page memory 26 to the input buffer 16a3 is executed, and the process returns to step 152.
On the other hand, if the judgment in step 410 is denied, step 41
If the judgment of No. 4 is affirmed, the output buffer 14a3
Since there is an instruction from the input buffer 16a1 to transfer data, in step 416, the output buffer 14a1
The process of transferring data from a3 to the input buffer 16a1 is executed, and the process returns to step 152.

In the various embodiments described above, the data transfer is controlled by outputting a timing signal from the memory control unit to each buffer and processing unit. Therefore, the external input device (CPU or DMA controller) is controlled. ), Various processes can be executed in parallel while maintaining the required data transfer rate of the external output device (printer). That is, compression and decompression on the same image bus can be executed simultaneously.

Further, the Refresh cycle can be executed in the idle time, so that the processing time can be shortened.

Further, the memory control unit controls all the buffers on the image bus and the timings for the buffers and the memories, which allows the data transfer path on the image bus to be arbitrarily set. Further, since the transfer timing of the processing means is constant regardless of the transfer destination device, the interface of the processing means can be simplified. Therefore, it is possible to easily add processing. For example, various processing functions other than compression and decompression processing, such as resolution conversion and color tone conversion, can be added.

Furthermore, by changing the bandwidth of the image bus, it is possible to construct from a system that realizes multi-functionality and configuration to an inexpensive system that is limited to a specific purpose.

[0248]

As described above, according to the present invention, the processing means is connected to the output side of the first holding means and the input side of the second holding means, and the data which has been subjected to the predetermined processing is secondly held. Subsequent to the processing of outputting from the means to the image bus, the data input by the input holding means is input to the first holding means, a predetermined processing is performed, and the data is stored in the storage means via the second holding means. The data is stored continuously, and the data stored in the storage means is read out and input to the external input device via the input holding means or to the external output device via the output holding means. The data can be transferred, subjected to a predetermined process and stored in the storage unit, and data can be continuously read from the storage unit and input to an external input device or an external output device, and the utilization efficiency of the storage unit can be improved with a simple configuration. Improvement Thereby, an effect that.

According to the present invention, the processing means is connected to the output side of the first holding means and the input side of the second holding means, and the data subjected to the predetermined processing is transferred from the second holding means to the image bus. In succession to the output processing, the data in the storage means input and stored from the external input device is read out, input to the first holding means, subjected to predetermined processing, and output to the second holding means, Since the second holding means inputs to the external input device via the input holding means, or the second holding means inputs to the external output device via the output holding means,
Utilizing the storage means with a simple configuration, the data can be stored in the storage means, the data can be continuously read and transferred from the storage means, the predetermined processing can be performed, and the data can be input to an external input device or an external output device. It has an effect that efficiency can be improved.

Further, according to the present invention, the control means controls the input holding means, the first processing means and the storage means when performing the first control, and the storage means and the second control when performing the second control. By controlling the processing means and the output holding means or the input holding means, it is possible to perform the first processing and the second processing in parallel with a simple configuration, and the control means is the input holding means,
Since the first processing means, the storage means, the second processing means and the output holding means are controlled, there is an effect that the data transfer path can be arbitrarily set according to the control timing.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is a block diagram showing details of an image bus control unit.

FIG. 3 is an explanatory diagram for explaining a signal to a memory control unit and a signal from the memory control unit.

FIG. 4 is a flowchart showing a control routine of the arbiter of the first embodiment.

FIG. 5 is a flowchart showing a control routine of a memory control unit of the first embodiment.

FIG. 6 is an explanatory diagram for explaining a signal used when executing decompression processing.

FIG. 7 is an explanatory diagram for describing a signal used when performing compression processing.

FIG. 8 is an explanatory diagram for explaining a data transfer path.

FIG. 9 is a timing chart of data transfer to an input buffer.

FIG. 10 is a timing chart of data transfer from the output buffer.

FIG. 11 is a block diagram of a second embodiment and a diagram showing a data transfer path.

FIG. 12 is a timing chart of the second embodiment.

FIG. 13 is a block diagram of a third embodiment and a diagram showing a data transfer path.

FIG. 14 is a flowchart showing a control routine of the arbiter of the third embodiment.

FIG. 15 is a flowchart showing a control routine of a memory control unit of the third embodiment.

FIG. 16 is a timing chart of the third embodiment.

FIG. 17 is a diagram showing a block unit and a data transfer path of a fourth embodiment.

FIG. 18 is a flowchart showing a control routine of a memory control unit of the fourth embodiment.

FIG. 19 is a flowchart showing a control routine of a memory control unit of the fourth embodiment.

FIG. 20 is a block diagram of a fifth embodiment and a diagram showing a data transfer path.

FIG. 21 is a flowchart showing a control routine of a memory control unit of the fifth embodiment.

FIG. 22 is a flow chart showing a control routine of a memory control unit of the fifth embodiment.

[Explanation of symbols]

(First Embodiment to Third Embodiment) 12 Input / Output Buffer (Input Holding Means) 14a1 Output Buffer (Input Holding Means) 14a2 Output Buffer (Second Holding Means (Claim 1), Third Embodiment Holding means (for example, claim 10) 14a3 Output buffer (Second holding means (for example, claim 5), Fourth holding means (for example, claim 10) 16a1 Input buffer (output holding means) 16a2 Input buffer (First holding means (eg, claim 1, claim 10)) 16a3 Input buffer (first holding means (eg, claim 5), second holding means (eg, claim 10)) 18a1 Compression Processing unit (processing means (for example, claim 1), first processing means (for example, claim 10)) 18a2 Expansion processing unit (processing means (for example, claim 5)), second processing means (for example, (Requirement 10)) 20 Image bus control section (control means) 26 Page memory (storage means) 28 Image bus (fourth embodiment) 18a3 Resolution conversion processing section (processing means (for example, claim 1)) (fifth embodiment) Embodiment) 18a4 tone conversion processing unit (processing means (for example, claim 5))

Claims (14)

[Claims] 1. Input holding means for holding data input from an external input device and outputting the held data; first holding means for holding the input data and outputting the held data; Second holding means for holding data and outputting the held data; storage means for inputting and storing the data; data output from the input holding means to the first holding means; Of the input holding means, the input side of the first holding means, the output side of the second holding means, and the storage so that the data output from the holding means are transferred to the storage means, respectively. An image bus to which an input side of the means is connected, and data is output to the output side of the first holding means and the second holding means so that the data is input from the first holding means. Is connected to the input side of the second holding means and gives a first instruction to the first holding means so as to input the data output from the input holding means via the image bus, and The data input from the first holding unit is subjected to a predetermined process, the data subjected to the predetermined process is output to the second holding unit, and the second data is output to the second holding unit.
Processing means for giving a second instruction to the second holding means so as to output the data held by the holding means to the image bus, and the data input to the input holding means from the external input device is stored in the image bus. The input holding means, so that the data is transferred in the order of the storage means via the first holding means, the processing means, the second holding means, and the image bus, and is stored in the storage means. A data transfer control device comprising: a control unit that controls the processing unit and the storage unit. 2. An output holding means for holding the input data and outputting the held data to an external output device, wherein the data output from the storage means is transferred to the input holding means or the output holding means. As described above, the output side of the storage means and the input side of the input holding means or the input side of the output holding means are connected to an image bus, and the control means stores the data stored in the storage means.
The storage means and the input holding means or the output holding device are controlled so that the input holding means can input from the input holding means via the image bus or the output holding means to the external output device via the image bus. The data transfer control device according to claim 1, wherein 3. The control means outputs the data stored in the storage means from the output holding means to the external output device via the image bus or from the input holding means to the external input device via the image bus. Controlling the storage means and the output holding means or the input holding means, the data output from the external input device via the image bus, the input holding means, the first holding means,
Priority is given to control over the input holding means, the processing means, and the storage means, which are transferred to the storage means through the processing means, the second holding means, and the image bus in this order and stored in the storage means. The data transfer control device according to claim 2, which is performed. 4. The data transfer control device according to claim 1, wherein the predetermined process is any one of compression, decompression, and resolution conversion. 5. Input holding means for outputting input data to an external input device, first holding means for holding the input data and outputting the held data, and holding data for holding the input data Second holding means for outputting the stored data, storage means for outputting the stored data, output holding means for holding the input data and outputting the held data to an external output device, and data output from the storage means Is transferred to the first holding means, and the data output from the second holding means is transferred to the output holding means or the input holding means, respectively, on the output side of the storage means, the first holding means. An image bus to which the input side of the means, the output side of the second holding means and the input side of the output holding means or the input side of the input holding means are connected, and the first storage The input holding unit is connected to the output side of the first holding unit to input data from the holding unit and to the input side of the second holding unit to output data to the second holding unit. Means for giving a first instruction to the first holding means to input the data output from the means via the image bus, and performing a predetermined process on the data input from the first holding means, Outputting the processed data to the second holding means and the second holding means.
Processing means for giving a second instruction to the second holding means so as to output the data held by the holding means to the image bus; and the data stored in the storage means via the image bus. Storage means for transferring the output holding means or the input holding means through the holding means, the processing means, the second holding means, and the image bus in this order and inputting them to an external output device or an external input device. And a control means for controlling the processing means and the output holding means or the input holding means. 6. The input holding means holds data input from an external input device, outputs the held data, and has an output side connected to the image bus, and the control means inputs from the external input device. 6. The data transfer control device according to claim 5, wherein the input holding unit and the storage unit are controlled so that the stored data is transferred to and stored in the storage unit. 7. The control means transfers the data stored in the storage means in the order of the first holding means, the processing means, the second holding means, the output holding means or the input holding means. The storage means, the processing means, and the control for the output holding means or the input holding means to be input to the external output device or the external input device by transferring the data input from the external input device to the storage means and storing the data. 7. The data transfer control device according to 6, wherein the control is performed prior to the control of the input holding unit and the storage unit. 8. The data transfer control device according to claim 5, wherein the predetermined process is any one of compression, decompression, and color tone conversion. 9. The processing means gives the first instruction to the first holding means by outputting an input permission signal to the first holding means and outputs an output permission signal to the second holding means. Is output to give the second instruction to the second holding means, and when there is no data in the first holding means, a signal indicating that there is no data in the first holding means, and When there is data in the second holding unit, a signal indicating that the second holding unit has data is output to the control unit, and the control unit causes the processing unit to hold the first holding unit. When a signal indicating that there is no data is input to the input input device, the data output from the external input device is input and held, and the input holding means is controlled to output the held data on the bus. The processing means By outputting the first data transfer permission signal, the processing unit causes the first holding unit to output the input permission signal, and the data output on the bus is input to the first holding unit. When a signal indicating that there is data is input from the processing means to the second holding means, a second data transfer permission signal is output to the processing means so that the processing means transfers to the second holding means. 9. The data transfer control according to claim 1, wherein the processing means is controlled so that the output permission signal is output and the held data is output on a bus. apparatus. 10. An input holding means for inputting and holding data from an external input device and outputting the held data; a storage means for inputting and storing the data and outputting the stored data; At least one first processing means for performing the first processing and outputting the data subjected to the first processing; At least one second processing means for outputting, and at least one first holding means for inputting and holding data according to an instruction from the first processing means and outputting the held data to the first processing means And at least one second holding means for inputting and holding data according to an instruction of the second processing means and outputting the held data to the second processing means, At least one third holding means for inputting and holding the data output from the first processing means and outputting the held data according to an instruction from the first processing means, and for outputting from the second processing means At least one fourth holding means for inputting and holding the stored data and outputting the held data according to the instruction of the second processing means, and an external output device for inputting and holding the data and holding the held data. Output holding means for outputting to, the data output from the input holding means is stored in the first holding means, the data output from the third holding means is stored in the storage means, and the storage means Of the input holding means so that the data is transferred to the second holding means and the data output from the fourth holding means is transferred to the output holding means or the input holding means. Force side and output side, input side of the first holding means and the second holding means, output side of the third holding means and the fourth holding means, input side and output side of the storage means, and An image bus to which an input side of the output holding means is connected, and data output from the external input device, the input holding means, the first holding means, the first processing means, the third holding means , And the storage means, so that the input holding means, the first processing means, and the storage means are controlled so as to be stored in the storage means. The data stored in the second holding means, the second processing means, the fourth holding means and the output holding means or the input holding means are transferred in this order to an external output device or an external input device. As entered Serial storage means, the data transfer control device and a control means for performing a second control for controlling the second processing means and the output holding means or the input holding means. 11. The data transfer control device according to claim 10, wherein the control means performs the second control with priority over the first control. 12. The data transfer control device according to claim 10, further comprising a plurality of the storage units, wherein the control unit simultaneously performs the first control and the second control. 13. The data transfer control device according to claim 10, wherein the first processing is compression and the second processing is decompression. 14. The first processing means outputs the input permission signal to the first holding means and the second processing means outputs the input permission signal to the second holding means, respectively. By giving the instruction to the second holding means, the first processing means outputs the output permission signal to the third holding means and the second processing means outputs the output permission signal to the fourth holding means, respectively. In addition to giving the instruction to the third holding means and the fourth holding means, when the first processing means does not have data, the first holding means has no data. And a signal indicating that there is no data in the second holding means when the second processing means outputs data to the control means. 1 processing means is before Note that when the third holding means has data, a signal indicating that the third holding means has data and the second processing means when the fourth holding means has data are described above. A signal indicating that there is data in the fourth holding means is output to the control means, respectively, and the control means inputs a signal indicating that there is no data in the first holding means from the first processing means. In this case, the input holding means is controlled so that the data output from the external input device is input and held, and the held data is output to the image bus. The data transfer permission signal is output from the first processing means to the first holding means to output the input permission signal, and the data output from the input holding means onto the image bus is the first data. A second data transfer permission signal is output to the first processing means when a signal indicating that there is data is input from the first processing means to the third holding means. By doing so, the first processing means causes the third holding means to output the output permission signal, and the data held by the third holding means is output to the image bus. The storage means is controlled so as to output the stored data to the image bus when a signal indicating that there is no data is input from the second processing means to the second holding means while controlling the storage means. Shikatsu and the second
By outputting a third data transfer permission signal to the processing means, the second processing means causes the second holding means to output the input permission signal, and the storage means outputs the input onto the image bus. When data is input to the second holding means and a signal indicating that there is data in the fourth holding means is input from the second processing means, the fourth data is input to the second processing means. By outputting a transfer permission signal, the second processing means causes the fourth holding means to output the output permission signal so that the data held by the fourth holding means is output onto the image bus. The control means for controlling the second processing means.
The data transfer control device according to any one of claims 0 to 13.