JP2000315172A - Memory control using memory state information to shorten access latency time - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide memory control and access traffic control for shortening memory access latency time. SOLUTION: A memory controller circuit 18a connected to a memory 24 consisting of plural lines includes a circuit 28 for receiving a signal expressing a memory access request. The 1st signal received by the receiving circuit 28 includes the 1st address and the 2nd signal received by the circuit 28 after the reception of the 1st signal includes the 2nd address of the memory. The circuit 18a includes also a determination circuit 30 (RAn, AC#Bn#ROW, C#B#Rn) for determining whether the 2nd address is related with the 1st address or not and a circuit 30 for issuing a control signal to the memory 24. Each memory access is generated by the control signal in response to each request. The control signal issuing circuit 30 issues the control signal to the memory 24 so that the same line out of plural lines is actively stored between the 1st and 2nd accesses in response to the determination circuit 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to environments implementing memory control and direct memory access ("DMA"), and particularly to circuits, systems, and systems in these environments to reduce access latency. Aimed at the way.

[0002]

2. Description of the Related Art Memory control includes a memory controller,
That is, because dynamic random access memory ("DRAM") is a type of memory that is often controlled, it is standard practice in computer technology by a mechanism called a DRAM controller. A DRAM controller may be another circuit or module contained within a larger circuit and typically receives a request to access one or more memory locations of a corresponding memory. To respond to each request, the memory controller implements sufficient circuitry (e.g., address and logic decoders) to provide appropriate control signals to the memory, appropriately controlling the memory and deactivating its storage circuitry. Energize.

[0003]

While certain DRAM controllers are designed to increase the efficiency of memory access, certain limitations are imposed under current technology in connection with embodiments of the present invention. I understood. Some of these limitations are generated by the DRAM controller, which generates a number of overhead cycles, where overhead cycles represent cycles where the DRAM is busy but is not currently transmitting or receiving data. One common solution to reduce the overall penalty caused by overhead is to use burst operations. Typically, only a single address is required with the burst size, and subsequent data units (ie, bursts) can be read or written without additional overhead for each data unit, so the burst operation is a whole operation. Reduce overhead. However, even with burst techniques, it is still important to determine the amount of overhead cycles required for a particular burst size. In this regard, with current technology, the ratio of burst length to total access length provides one measure of efficiency. Given this measure, efficiency can be improved by increasing the burst length, ie, by providing long uninterrupted burst accesses. In other words, it is considered that the efficiency is improved because the number of data access cycles with respect to the overhead cycle is increased for the same number of overhead cycles. However, it has been confirmed by the present inventor that such a method also causes an obstacle. One disadvantage is that bursts of multiple cycles prohibit access to memory by different request circuits during the burst,
Or if a different request circuit is allowed to interrupt the burst, this may be an overhead that stops the current burst.
Add the cycle and the extra overhead of restarting the burst after the access of the different request circuits is completed,
Typically achieved by interrupts. These disadvantages are:
This is especially true for systems that include one or more processors with access to the same DRAM (eg, general purpose, special purpose processors, MPUs, SCPs, video controllers, etc.).

[0004] To further illustrate the above limitations and provide additional explanation, FIG. 1 illustrates a timing diagram of four accesses to main memory via a DRAM controller, which access is generally referred to as A1. Name it A4. For the sake of explanation,
Assume that accesses A1 and A3 are first resources R1 (eg, CPU) and accesses A2 and A4 are second resources R2 (eg, external peripherals). Accesses A1 through A4 will be discussed in detail below, but note that at this point in FIG. 1 each represents an example of the typical number of clock cycles spent in these accesses. These numbers and timing of accesses will be used hereinafter to illustrate various advantages of embodiments of the present invention.

Access A1 is a read burst access to main memory, where the burst is eight data words. The first part of access A1 is the overhead period,
Example requires 6 cycles. This overhead is referred to in this document as the reading overhead, and as is known in the art, operations such as providing control signals to the main memory containing the address to be read and waiting for main memory operation to respond to these signals. Including. The second part of access A1 is the provision of a burst of data from main memory. In this example, the burst size is 8, and each burst amount (eg, 16 bits) consumes a single clock.
Accordingly, eight 16-bit bursts require eight cycles in total. To summarize the description of access A1, those skilled in the art will recognize that this requires a total of 14 cycles.

Accesses A2, A3, and A4 represent a single data read, a write burst, and a single data write, respectively. Like access A1, each of accesses A2, A3, A4 starts with some number of reading overhead cycles. In particular, the read operation of access A2 uses a reading overhead of 6 cycles,
Each of the A3 and A4 write operations uses three cycles of reading overhead. In addition, access A2, A
3, each of A4 is shown to consume a single cycle per data amount. Thus, a single data operation for accesses A2 and A4 each consumes a corresponding single cycle, while a burst operation for access A3 consumes eight cycles,
Each of the cycles corresponds to one of eight bursts of write data. Finally, each of accesses A2, A3, and A4 is
Note that this also includes post-access overhead, which is referred to in this document as termination overhead. Such overhead also results from various control operations, such as receiving a signal indicating the end of the access along with precharging the memory rows and / or banks. In the example of FIG. 1, the read operation of access A2 uses a 2-cycle termination overhead, the write operation of access A3 uses a 4-cycle termination overhead,
The write operation for access A4 uses a 5-cycle termination overhead.

It is helpful here to summarize the results relating to the description of FIG. 1 and to examine its various disadvantages. The first disadvantage is that accessing only 18 data volumes requires a total of 47
Note that the cycle is being consumed. Therefore, 29 cycles result from overhead operations, and therefore 62% of the cycles (ie 29/47 = 0.6
2) is associated with overhead, and actual data access requires 38 percent of the cycle (ie, 18/47 = 0.3
8) has left. As another consideration of the scheme of FIG. 1, note that a gap occurs between accesses A3 and A4, which occurs, for example, when there is a sufficient gap between the requests that resulted in accesses A3 and A4. When such a gap occurs, an additional extra latency clock cycle is consumed as mere latency, as shown by way of example in FIG. 1 as eight cycles. During this time,
No bandwidth is used to access data. In addition, after the waiting time, when the DRAM controller reissues the reading overhead for accessing A4, there is extra latency at the start of access A4. From the foregoing, it will be appreciated by those skilled in the art that these factors along with other factors contribute to, increase, and degrade overall system performance the average time to access data (ie, latency).

As a further background, the use of DMA provides the system with some system latency. DMA allows a peripheral device or a coprocessor to access memory without using a large amount of processor resources to perform data transfers. A traffic controller groups and orders DMA accesses along with direct processor accesses. In particular, if another peripheral issues an access request to the traffic controller and access is granted by the controller, the DM
Access to main memory is provided via the A channel. In addition, the CPU also has access to main memory via a channel provided via a traffic controller separately from the DMA. In each case, multiple devices
The DMA scheme typically provides an access channel to memory for memory access via A.

While DMA thus provides improved performance in various respects, the inventor has noted that the memory memory described above in connection with FIG.
He acknowledged that it did not solve the shortcomings of the controller. In addition, the scope of the present invention includes a consideration of the priorities used in connection with DMA and traffic control and improving system performance, both alone and in combination with an improved memory controller.

In view of the above, a need has arisen to overcome the disadvantages of the prior art and provide improved memory control and access traffic control to reduce memory access latency.

[0011]

In one embodiment, there is a memory controller circuit coupled to a memory, where the memory has a plurality of rows. The memory controller circuit includes a circuit that receives a signal representing a request to access the memory. For these signals, the first signal representing the first request to access the memory is received by the receiving circuit and includes a first address of the memory, and the second signal representing the second request to access the memory is the second signal. One signal is received by the receiving circuit after receiving the signal and includes the second address of the memory. The memory controller circuit also includes a determination circuit for determining whether the second address is directed to the same row of the same plurality of rows as the first address. Further, the memory controller circuit includes a circuit that issues a control signal to the memory in response to receiving a signal indicating a request to access the memory. By these control signals, the first
A first memory access occurs in response to the request, and a second memory access occurs in response to the second request. Finally,
In response to a decision circuit that determines that the two addresses are directed to the same row of the plurality of rows as the first address, the same row of the plurality of rows is actively held between the first and second accesses. The control signal issuing circuit issues a control signal to the memory in such a manner. Other circuits, systems, and methods are also disclosed and claimed.

[0012]

FIG. 2 illustrates various DRAM control and traffic control embodiments described in this document,
For example, a preferred embodiment of a general purpose wireless data platform 10 that can be used to implement a smart phone or portable computing device. Wireless data platform 10 includes a general purpose (host) processor 12 having an instruction cache 12a and a data cache 12b, each having a corresponding instruction memory management unit ("MMU") 12c and 12d, and a buffer circuit 12e. The operating core 12f is illustrated, and all of them communicate with each other via a system bus SBUS. SBUS is data SBU
Includes S _d , address SBUS _a and control SBUS _c conductors. A digital signal processor ("DSP") 14a having its own internal cache (not shown) and a peripheral interface 14b are coupled to the SBUS. Although not shown, various peripherals, including digital-to-analog converters ("DACs") or network interfaces, are therefore coupled to peripheral interface 14b.
DSP 14a and peripheral interface 14b are coupled to a DMA interface 16 which is further coupled to a traffic controller 18, which is described in more detail below. The traffic controller 18 is also coupled to the SBUS, as is the video or LCD controller 20 in communication with the LCD or video display 22. Traffic controller 18, an address 24 _a in the preferred embodiment the main memory synchronous dynamic random access memory ( "SDRAM") is 24, the data 24 _d, are coupled via a bus control 24 _c. In fact, it should be noted that for the following description, the traffic controller 18 includes a DRAM controller 18a as an interface for the connection between the traffic controller 18 and the SDRAM 24. Regarding this point, in this embodiment,
Although the DRAM controller 18a is a module within the circuits forming the traffic controller 18, the various circuits and functions described in this document in connection with the DRAM controller 18a can be implemented in separate devices and, in fact, Note that it is used in other examples. Returning to traffic controller 18 in general, this is address 2
6 _a, data 26 _d, It is noted finally that it is coupled to the flash memory 26 (or memories) via control 26 _c bus.

The general operational aspects of wireless data platform 10 are appreciated by noting that it utilizes both general purpose processor 12 and DSP 14a.
Unlike current devices where DSPs are assigned to special fixed functions, the DSP 14a of the preferred embodiment can be used for multiple functions. This allows the user to take full advantage of the DSP 14a. For example, DSP14
Certain areas where a can be used relate to functions such as speech recognition, image and video compression and decompression, data encryption, document-to-speech conversion, and the like. The architecture can easily add new features and enhancements to the wireless data platform 10.

Turning now to the traffic controller 18, its general operation, as well as the various circuits coupled to it, include DMA access requests and host processor 1
2 can receive direct access requests from
In response to both of these requests, a transfer from / to the following is enabled: from the host processor 12 to the SDRAM 24 or vice versa; from the host processor 12 to the flash memory 26 or vice versa; SDRAM 24 or vice versa from peripheral devices connected to peripheral interface 14b. Video or LCD controller 20 from SDRAM 24. In addition, in a preferred embodiment, conflict-free accesses can be performed simultaneously. For example, SDRAM24
The host processor 12 may execute the reading from the flash memory 26 simultaneously with the DMA transfer from the flash memory 26 to the video or LCD controller 20. Otherwise, the traffic controller 18 can read video or LCD from SDRAM 24.
The preferred embodiment is operating on a first-in first-out basis ("FIF
O ") including a circuit consisting of 18b to take a burst of data from SDRAM 24 and provide it in a continuous stream such as requiring pixel data to be provided to video or LCD controller 20.

For convenience of illustration, the traffic controller 18 is shown to include a request stack 18c, which logically represents that different circuits have requested a DMA transfer during the overlapped time, and thus these different Request DM
A transfers remain pending for a common time. In the preferred embodiment, another physical storage device, such as request stack 18c, does not actually exist; instead, different requests reach one or more conductors. For example, a request from a peripheral device arrives on a conductor reserved for such a request. In a more complex scheme, however, the request stack 18c may represent actual physical storage. Also, in terms of receiving access requests, in the preferred embodiment only one request per request source is pending at one time by the traffic controller 18 (other than the auto-refresh request detailed below). Before issuing access requests, all request sources must be DMA
This restriction can be ascertained by requiring that authorization be received from the controller 18. For example,
The authorization may indicate that a previous request issued by the same request source has been serviced. However, in more complex embodiments, multiple requests from the same request source could be pending by the DMA controller 18. Returning to stack 18c, the intention is to explain the case where multiple requests are pending at the same time, whether from the same or different request sources, and these requests are analyzed and processed as described in detail below. You. Further in this regard, each of these pending requests is selected according to an order defined by various priority considerations, since traffic controller 18 includes a priority handler, which will be described in more detail below. In other words, in one embodiment, pending requests are serviced in the order in which they were received, while in other embodiments, pending requests are granted access in a different order than received as will be subsequently acknowledged. Finally, the traffic controller 18
Includes circuitry for supporting connections to the various circuits described above that provide direct or DMA access. For example, traffic controller 18 preferably includes a flash memory interface that generates the appropriate signals required by the flash device. As another example, traffic controller 18 includes DRAM controller 18a as described above, which implements the control of the state machine and generates the appropriate signals required by SDRAM 24. This latter interface provides various advantages within the scope of the present invention, and is described in detail below, along with the various functions associated therewith.

Although the traffic controller 18 has been introduced, it should be noted that various inventive methodologies are included in the preferred embodiment detailed below. To provide a description in order, the DRAM controller 18 described first will be described.
a and the DRAM controller 18 within the traffic controller 18 described second.
Divide the methodology into those that pertain to some sort of priority consideration being processed outside of a. Finally, however, we describe how these methodologies can be combined to further reduce the latency that would otherwise occur in the prior art.

In the preferred embodiment, the DRAM controller 1
8a is designated to support three different memories.
As an example, two of these memories are available from Texas Instruments, 16
M-bit TMS626162 (512k x 16-bit I / O x 2 banks) and 64-Mbit TMS664164 (1M x 16-bit I / O x 4 banks). The third of these memories is a 64 Mbit memory made up of two banks. The burst length from the SDRAM 24 in response to a request from the DRAM controller 18a is fully programmable with a 16-bit data amount of 1 to 8 and follows the first request indicated by REQ as described in more detail below. By sending one or more consecutive requests, indicated by the SREQ, thereby allowing all burst lengths between 1 and 256 without extra overhead, 256
(Page length). In the preferred embodiment, this programmability is implemented via control from the DRAM controller 18a to the SDRAM 24, rather than the burst size of the SDRAM memory control register.

One attractive advantage implemented in the preferred embodiment of DRAM controller 18a is that latency reduction can be achieved by responding to input memory access requests based on an analysis of SDRAM 24 state information. It is.
This function is illustrated and described below with reference to the flow chart of FIG. 4, which will first be introduced with reference to the block diagram of FIG. FIG. 3 illustrates both the SDRAM 24 and the DRAM controller 18a in more detail than FIG. 2, but again, only the selected elements are illustrated to simplify the illustration again and focus on the description of the DRAM control surface.

Turning to the SDRAM 24 of FIG. 3, it includes a plurality of memory banks designated banks B0 through B3. The number of banks, here four, comes from the example in which the SDRAM 24 is a Texas Instruments 64-megabit memory as described above. When different memories are used, the number of banks is also different (for example, the aforementioned 16
(2 banks when using megabit memory)
As is known in SDRAM technology, each bank of a multi-bank memory has a corresponding row register that indicates the currently active row address in the corresponding bank. In FIG. 3, these row registers are named B0_ROW to B3_ROW corresponding to banks B0 to B3, respectively.

Turning now to the DRAM controller 18a of FIG. 3, the preferred embodiment includes sufficient circuitry to indicate various state information identifying the current operation of the SDRAM 24, and how this information is used. Whether to reduce the waiting time will be described later. Preferably, this status information is stored in row register B0_R
It is desirable to include a copy of the same information stored in B3_ROW from OW. Therefore, the DRAM controller 18a sets AC_B0_RO
It contains four registers, named W_AC_B3_ROW, where each indicates the active row address (if any) of the corresponding bank B0-B3. In other words,
The registers AC_B0_ROW to AC_B3 of the DRAM controller 18a
_ROW information is obtained from the row registers B0_ROW to B3_ROW of the SDRAM 24.
Has the same information as a mirror image. In addition, register AC_B0_RO
For each of W to AC_B3_ROW, DRAM controller 18
a includes corresponding bit registers C_B_R0 through C_B_R3 that indicate whether the corresponding row is currently being accessed. For example, if bit register C_B_R0 is set (e.g., a value equal to 1), this indicates that the row identified by the address of AC_B0_ROW is currently being accessed, and conversely if this bit is clear , AC_B0_ROW indicates that the row, if any, is not currently accessed.
Also, for each of the registers AC_B0_ROW to AC_B3_ROW,
The DRAM controller 18a determines that the content of AC_Bn_ROW is
DRAM 24 includes a corresponding bit register RAn indicating that this row of corresponding bank n is active. Note also that each register RAn (ie, RA0 through RA3) can be set to 1 at the same time. This means that each bank activates the row whose value is contained in each AC_Bn_ROW register. However, conversely, only one C_B_Rn is set to one at a time because it indicates which bank is currently being accessed and only one bank is accessible at a time.

The DRAM controller 18a also includes an additional circuit for generating various commands to the SDRAM 24 described below. In this regard, the DRAM controller 18a uses the SDRA
Preferably, it includes a CURR_ACCESS register that stores information about the most recent (or current) request that gave access to M24. This information includes the remainder of the address of the current access (ie, the column address), its direction, and size. In addition, DRAM controller 18a includes an input 28 for receiving the next (ie, pending) access request. The access request information received at input 18 is provided to comparison logic and state machine 30, which includes the state information stored in bit registers RA0-RA3 and C_B_R0-C_B_R3, the row addresses of registers AC_B0_ROW to AC_B3_ROW, and the CURR_ACCESS register. Have access to information stored in The circuitry used to implement the comparison logic and state machine 30 may be selected by one of ordinary skill in the art from various examples, but in any event performs the functions detailed below in connection with FIG. As an introduction before proceeding, the comparison logic and slate machine 30 is a DRAM controller 1
It gives an address to the address bus 24 _a between 8a and SDRAM 24, should also be noted that it is connected to provide a control signal to the control bus 24 _c between the DRAM controller 18a and SDRAM 24. For the latter, for purposes of illustration, the control signals are combined in various ways and identified as various commands, each of which is issued per single cycle, and for each type of required access (i.e., single read, burst). Read, single write, burst write, auto refresh, power down). The actual control signals communicated to execute these commands include the following signals: RAS, CAS, DQML, DQMU, W, CKE,
CS, CLK, and address signals. However, the combination of these control signals to perform the functions described in Table 1 immediately below is more easily referred to by the function corresponding to each function than by elaborating on the value of each of the various control signals. Can be.

[Table 1]

FIG. 4 illustrates a flow chart of a method, generally designated at 40, which illustrates the desired operation of the DRAM controller 18a with respect to memory access of the SDRAM 24, which method includes a comparison logic and operation of the entire state machine 30. It is implemented by. Method 40 begins by selecting 42 the next memory access request (abbreviated as "RQ") for analysis. In the embodiment of FIG. 3, RQ is received from input 28. However, it should be noted that the request may be directly from a bus or the like. In addition, for simplicity, method 40
This explanation shows that the operation of the previous RQ has already been
4 shows that each of the banks B0 to B3 is accessed. Therefore, register AC_B0_ROW
Each of C_B3_ROW is loaded with the corresponding row address,
It is assumed that the remaining bit registers are set to the appropriate state based on which row and / or bank is active. Another assumption is that the previous authorization was at the current memory access, ie
It is assumed that information communicating on (writing to or reading from SDRAM 24 ₎ on data bus 24d is present. Given these assumptions, method 40 proceeds from step 42 to step 44. However, before proceeding to step 44, the aforementioned hypothetical event (ie, there is already an active row)
It should be noted that the following description will further provide those skilled in the art with an understanding of the preferred embodiment, even though no occurrences have occurred.

Step 44 determines whether the bank accessed by RQ from step 42 (hereinafter referred to as the target bank) is the same bank that is currently being accessed. CURR_ACCES the bank part of the address of RQ
The comparison logic and state machine 30 makes this determination by comparing to the bank portion of the address stored in the S register. If the target bank of the RQ is the same bank that is currently being accessed, the method 40 proceeds to steps 44 to 46 as described below. Conversely, RQ
If the target bank of is in a different bank than the one currently being accessed, the method 40 proceeds from step 44 to step 58, which follows step 46 to provide a more direct description of the benefits as detailed below. Is done.

In step 46, since the target bank of the RQ is known to be in the same bank as the one currently being accessed, the page accessed by the RQ (hereinafter referred to as the target page) is the target bank. Determines if it is already on the same active row. In this regard, it should be noted that the terms "page" and "row" can be considered to refer to the same thing, because DR
This is because in the case of AM or SDRAM, these memory rows correspond to page information. Thus, step 46 determines whether the target page (or row) is on the same page (or row) that is already active in the target bank. By comparing the page address portion of the address of the RQ with the corresponding bit of the active row address stored in the appropriate register of the target bank,
The comparison logic and state machine 30 makes this determination.
For example, if bank B0 is the target bank, step 46 compares the page address of RQ with the corresponding bit of the active row value stored in register AC_B0_ROW. If the target page of the same row is already active in the target bank, method 40 proceeds from step 46 to step 48. Conversely, if the target page is
If the bank is on a different row than the already active row,
Method 40 proceeds from step 46 to step 52.

From the above, note that step 48 is reached when the target bank of the RQ is the same as the bank currently being accessed, and the target page is on the currently active row of the target bank. As a result, and providing a substantial improvement in latency described below, step 48 matches the access command of the RQ (eg, READ or WRITE) and occurs during the current access or near the last data transfer cycle. Let it. To further illustrate this point, FIG. 5 illustrates the current access CA and RQ (eg,
FIG. 8 illustrates both timing diagrams of the operation of step 48 for an access resulting from a read). In particular, as an example, it is assumed that the current access CA generates a burst of 8 data units in the corresponding 8 cycles. According to this example, step 48 matches and generates access commands during or near the end of the current access CA. In the preferred embodiment, the particular match in step 48 is based on whether the RQ is a write or a read. Accordingly, each of these situations is described separately below.

For step 48 where the RQ matches the access command when writing, the write access command is matched and issued in the clock cycle following the last data access of the current access CA. In other words, for the RQ that is a write, the last data of the current access CA is
If the access occurs in cycle N, the write access command for RQ is issued aligned in cycle N + 1. Further, note that during the same cycle that a write command is issued on the control bus, the data to be written is placed on the data bus. Thus, the data to be written is also on the data bus in cycle N + 1, and thus immediately follows the last data from the current access CA on the data bus in cycle N.

For the step 48 of matching the access command when RQ is read, the first cycle following the last data cycle of the current access CA, the CAS latency for a draw read, the read access command Will be issued consistently. In particular, consider that in most systems, the CAS latency is 1, 2, 3, or 4 cycles, depending on the memory being accessed and the clock frequency. Thus, in order to match read RQ access commands in the preferred embodiment, the CAS latency cycle number is subtracted from the first cycle following the last data cycle of the current access CA. In fact, in the preferred embodiment,
The comparison logic and state machine 30 includes an indicator of the current bus frequency from which to select the corresponding CAS latency. In general, the lower the bus frequency, the lower the CAS latency. For example, in idle mode where the required MIPS is low, the bus frequency is relatively low and the CAS latency is determined to be equal to one. Read RQ example, CAS
Proceeding to step 48 for an example where the latency is equal to one cycle, step 48 proceeds to the last data of the current access CA.
Align and generate read access commands one cycle before the first cycle following the cycle. In other words,
If the last data access of the current access CA occurs in cycle N for a RQ that is a read, the read access command of the RQ is aligned and generated in cycle N when the CAS latency is equal to one. You. Therefore, due to this alignment, a read access command is issued during the last data cycle of the current access CA, and the data read in response to this command appears on the data bus during cycle N + 1. For an example having one or more extra cycle CAS latencies, one or more extra cycles before the last data cycle of the current access CA will result in a corresponding alignment of the read access.

Once the RQ access command has been matched by step 48, step 49 represents the issuance of this command to SDRAM 24 by DRAM controller 18a to service the RQ. Other advantages of this operation will now be recognized as method 48 proceeds to step 50, as described immediately below.

Upon reaching step 50 following steps 48 and 49, step 50 performs an access in response to the access command matched by step 48. Thus, proceeding with the example of FIG. 5, step 50 performs a read that generates the first data unit of the data unit burst to be read, and a read that continues until the burst access is completed. To summarize the current example, the remaining seven data units are read during seven consecutive clock cycles. Thus, note the numerous advantages of the described operation. First, due to the matching of step 48, the first data unit of the access RQ is read in the clock cycle immediately after the last data cycle of the access CA. Second, steps 48 and 5
Note that the zero operation keeps the active row active so that the first and all consecutive accesses are directed to the same row in the same memory bank. In other words, there is no extra step of precharging the row during the occurrence of these accesses. Further, to implement this point, by chaining the contents of the row register (ie, AC_Bn_ROW) with the column address of the CURR_ACCESS register, the previous address is already in the DRAM controller 18a.
, The preferred embodiment does not need to retransmit the address of the RQ to SDRAM 24 for continuous access. Thus, again, the preferred embodiment simply performs the access while leaving the previously active row active. This advantage of keeping the row active also occurs in DMA burst control, as described below, but at this point, the DRAM controller 18a, by virtue of the description of receiving the request indicated by SREQ, indicates that , Indicating that the request is for data that follows the sequence of data just requested, and thus is directed to the same row address as the immediately preceding request. In any case, the prior art technique of accessing, precharging, re-addressing and re-activating a row will reduce the latency otherwise created. Third, FIG. 4 shows that the flow of the method 40 is from step 50 to step 42.
It should be understood that this occurs while the access of step 50 occurs. Therefore,
While the access of the current RQ is occurring, step 42 proceeds to the next
RQ processing may be started. Thus, in this regard, if the multiple burst requests are directed to the same bank and the same page of the bank, method 40 will repeatedly align the access commands and provide data access in the same manner as shown in FIG. It will be appreciated by those skilled in the art to execute and repeat the latency reduction described above for each successive event occurrence.
Thus, this set of reductions for each successive access therefore generates much less latency for successive accesses compared to the prior art.

Returning to step 46 of FIG. 4, an example is described where the method 40 proceeds from step 46 to step 52, which is consistent with the bank that the target bank is currently accessing, Recall what happens when a page is on a different row than the row already active in the target bank. At step 52, method 40 waits for completion of the current access. In the preferred embodiment, this completion is "access on" or "no access on"
Is detected by the DRAM controller 18a which checks the state of the access signal indicating either of the above. In particular, if there is a change from access on to no access on, the DRAM controller 18a knows that the current access has been completed, and thus step 52 can be completed. Then step 54
Precharges the row accessed by the just completed access, which sends a DEAC_x command to SDRAM 24
This is executed by the AM controller 18a. Thereafter, step 56 activates the row containing the target page by sending an ACTV_x command, and again the method proceeds to step 49 to issue an access command (eg, by either READ or WRITE), and step 50. To access the row with Finally, while the deactivation and subsequent activation of steps 54 and 56 is the worst scenario for cycle use under the preferred embodiment, the probability of this scenario is due to the locality and spatial Considering the nature of sex, it is relatively small.

Returning to step 44, an example where the method 40 proceeds from step 44 to step 58 will be described.
Recall that this occurs when the bank is different from the bank currently being accessed. Before proceeding further, when step 58 is reached, the currently active row on the currently accessed bank (ie, as evaluated from step 44) is not disturbed from this flow of method 40. Please be careful. In other words, this alternative flow does not deactivate the row of the currently accessed bank,
Thus, subsequent accesses where the row was not deactivated between successive accesses are accessible again. Returning now to step 58, this determines if there is an active row in the target bank. If so, the method 40 proceeds to steps 58-60. If there is no active row in the target bank, the method 40 proceeds from step 58 to 70. The operation of step 58 is preferably performed by comparison logic and state machine 30 which first consults a bit register corresponding to the target bank and indicating its current state. For example, if bank B1 is the target bank, comparison logic and state machine 30 evaluates whether bit register RA1 is set to indicate an active state. In this regard, reduced latency compared to systems that wait for the current access to complete before initiating any overhead operations towards activating the bank for the next access Note again. Next, the method 40 proceeds from step 58 to step 60.

Step 60 operates in much the same way as step 46 described above, except that in step 60 the target bank is different from the bank currently being accessed. Thus, step 60 determines whether the target page is on the same row in the target bank. If the target page is on the same line in the target bank,
The method 40 proceeds from step 60 to step 62. target·
If the page is on a different row than the active row in the target bank, the method 40 proceeds from step 60 to step 68. Alternative paths starting from steps 62 and 68 are described below.

Step 62 matches the access command of the RQ and waits for the end of the current access. This alignment is also found in the reference to step 64 following step 62. In particular, step 62
Then, the comparison logic and the state machine 30 issue an access command (for example, READ or WRITE) for issuing to the SDRAM 24.
Directive), so that the target
Make the bank the currently accessed bank. in addition,
This operation of step 62 is generally similar to that described above in connection with step 48. Therefore, the reader is referred to the above description of step 48 for further details indicating that step 62 preferably matches the access command before or during the last data cycle of the current access. I want to. Thus, the method proceeds to step 64, where it issues a READ or WRITE command to SDRAM 24, followed by step 66, where an access corresponding to RQ is performed. Thereafter, method 40 returns from step 66 to step 42 to process the next memory access request.

Returning to step 60, recall that this flow is directed to step 68 when the RQ is on a different page than the one already active in the target bank. In this example, step 68 precharges the currently active row of the target bank. Again, in the preferred embodiment, this is accomplished by issuing a DEAC_x command to SDRAM 24. Thereafter, step 70 activates the row containing the target page, and the method proceeds to step 62. From the foregoing description of step 62, step 62 therefore matches the access command to the RQ, issues an access command, and performs the access corresponding to the RQ step 6
One skilled in the art will recognize that 4 and 66 follow. Thereafter, method 40 again returns from step 66 to step 42 to process the next memory access request.

To further clarify the above description and its advantages, FIG. 6 again illustrates accesses A1 through A4 from FIG. 1, but now implements the method 40 of FIG. The timing of these modified accesses is indicated, assuming that they represent a memory access request that operates to access a row that is already active in any of the banks. Following this assumption, those skilled in the art can easily track the steps of method 40 and arrange that the leading cycle of the overhead of access A2 occurs at the same time (ie, overlaps) as the last data access cycle of access A1. Can conclude. Thus, a single data unit from access A2 is read in the clock cycle immediately after reading the last data unit of the burst of access A1. Similarly, for access A3, its reading overhead is advanced at a time that is partially the same as a single read of data from access A2, and overlaps during a portion of the time of access A2's termination overhead. Therefore, the actual data access (burst write) can be started earlier than when the reading overhead of access A3 cannot be started until the termination overhead of access A2 is completed. Finally, recall that for access A4, this is received after an eight cycle gap. However, since the assumption is that access A4 is already directed to a row that is already active, there is no need to precharge and then reactivate this row during the access, so the number of cycles in its reading overhead is Note that it is reduced (or eliminated). Thus, the total number of cycles, both gap and reading overall, is reduced, which also reduces access latency. Therefore, in conclusion, continuous SD
Those skilled in the art will recognize that the ability to keep a row active for RAM access increases bandwidth without increasing the clock frequency and reduces power consumption, which is often important in portable systems. Therefore,
Overall latency is reduced and system performance is dramatically improved. It should be noted that, as a final matter, the localization and spatiality that occurs in many systems has resulted in the aforementioned improvements or has resulted from certain programs implemented in these systems. In this regard, in a preferred embodiment, the DRAM controller 18a further includes a programmable bit whose state is to activate or deactivate the functions of FIG. Thus, if for some reason such a scheme is determined to be undesirable (eg, if there is a problem with locality or spatial assumptions,
Or if the program is known to produce random or very unpredictable memory accesses), setting this bit to the appropriate state deactivates the function of FIG. The technology can be operated in the manner of a controller. Conversely, setting this bit to activate the above function achieves the advantages detailed above for programs that will result in consecutive accesses to the same row of memory.

While the DRAM controller 18a has been described through the structure of FIG. 3, the method of FIG. 4, and the results of FIGS. 5 and 6, FIG. 7 illustrates in more detail how to implement the various details described above. I do. Before proceeding further, FIG. 7 is an example of practicing the present invention, and various details described above will not be described again here, but those skilled in the art will be able to ascertain additional information and teach the teachings of this document. Can be provided. Therefore, the inputs of FIG. 7 should be understood from the above description, a signal indicating a current access request, a control signal for selecting either a 16 Mbit or a 64 Mbit memory, controlled by the DRAM controller 18a. Control signal to select whether a given memory has two or four banks, and a frequency signal used to determine CAS latency.
Certain additional connections and details regarding these signals are described below.

FIG. 7 shows that the access request line and the bank
The address portion is connected to a first input of multiplexer 72. A second input of the multiplexer 72 is connected to receive an internal address from the DRAM controller 18a,
Here, the internal address represents the most recently accessed row and bank address (readable from any of the AC_Bn_ROW and RAn registers). The control input of multiplexer 72 is a signal SR which is activated upon receipt of the continuous request signal SREQ.
It is connected to either the logical OR when the page intersection is detected by the EQ or the DRAM controller 18a. Thus, when neither of these events occurs, multiplexer 72 connects to pass the address from the access request to DRAM controller 18a, while if one of these events occurs, multiplexer 72 switches from the internal request. Is connected so as to pass the address to the DRAM controller 18a. The row address output by the multiplexer 72 is connected to the four AC_Bn_ROW registers, so that the address is thereafter stored in the appropriate one of these four registers for subsequent comparison. In addition, the output of multiplexer 72 is connected to an input of each of four comparators 74 ₀ 74 _3,
Here the second input of each of these comparators is connected to receive the previously stored row address from the corresponding register AC_B0_ROW to AC_B3_ROW. Thus, each comparator can compare the row address of the current address with the last row address of the corresponding bank (stored in register AC_Bn_ROW). The output of the comparator 74 ₀ is connected to the first input of AND gate 76 _a0, an input of the inverter INV ₀ that connects the output to the first input of the AND gate 76 _b0, to. Similarly, the output of the comparator 74 ₁ to 74 ₃ is connected to the AND gate of the pair in an equivalent way. AND gate 76 _a0
To 76 _b3 are connected to the output of a two-to-four decoder 78, which receives a two-bit bank address from the address output by multiplexer 72, and which of the four banks is being addressed. Is decoded into an output signal S_BANK that goes high (or two banks if a two-bank memory is used). Finally, A
The third input of each of the ND gate 76 _a0 from 76 _b3 is connected to the output of the corresponding RAn register.

The output of each of AND gates 76 _a0 through 76 _b3 provides a comparison logic and input to state machine 30. In particular, each AND gate with the identifier "a"
A high signal is output if the same row (and hence SB_SR) is addressed in the same bank as the most recent (or current) row addressed in that bank. Similarly, each AND gate with the identifier "b" is addressed to the same bank as the most recent (or current) row addressed to that bank, but to a different row (hence SB_DR). Output a high signal.

Finally, the comparison logic and state machine 3
As another input to 0, each pair of AND gates has C_B_
Latency signal introduced here for the first time together with the Rn register
Note that we add LAT_Rn. With respect to the latter, the comparison logic and the state machine of state machine 30 may be configured to issue commands (eg, ACTV_
It is desirable to include enough states to accommodate the latency requirements caused by various different combinations of (x, READ, WRITE, etc.). For example, for two consecutive reads, there is a minimum of nine cycles of latency between accessing data for these reads. Thus, other latency requirements, along with such latency between commands, correspond to the states of the comparison logic and state machine 30, which are coded in each row of the latency signal LAT_Rn. Thus, comparison logic and state machine 30 considers the latency of each of these rows before issuing the next command.

Returning to the description of the function of the traffic controller 18 beyond the mere DRAM controller 18a, this function is first introduced by first returning to the hardware block diagram of FIG. FIG. 8 illustrates a block of the traffic controller 18 as shown in FIG. 2 and illustrates yet another additional function. Looking at its function, the traffic controller 18 includes a FIFO 18b and a request stack 18c, both described above, where the FIFO 18b stores burst pixel data for communication with a video or LCD controller 20, and the request stack 18c Recall temporarily that these different pending requests are analyzed and the multiple access requests are stored so that they can act as described below.

Continuing with the description of FIG. 8, in the preferred embodiment, each access request in request stack 18c also has a priority associated with it, which may also reach the conductor associated with the corresponding request. desirable. However,
In a more complex scheme, the priority is also coded and stored with the request in the request stack 18c. As described in detail below, the priority may be changed to a value different from the initial value thereafter.
Thus, in a preferred embodiment where the priority is present as a signal on a conductor, this signal may be changed on that conductor (e.g., changing from one binary state to another may change from low priority to high priority). Represents a change to degrees). Generally, and as will become more apparent below, the lower priority is the DR
Issuing the corresponding request to the AM controller 18a causes a delay before the corresponding access request is serviced, while conversely, higher priority means that other efficiency considerations may cause the current service to wait , The corresponding access request is immediately communicated to the DRAM controller 18a. These alternatives are described further below.

The traffic controller 18 also includes a priority handler and state machine 18d. The priority handler and state machine 18d is constructed by those skilled in the art from various alternatives and, in any event, achieves the functions detailed herein. As an introduction example of the priority analysis, the priority handler and the state machine 18d are shown in FIG.
Want to do contain 8d _T is noted that depicted. Priority table 18 d _T are lists the order in which the service access request by issuing a corresponding request to the DRAM controller 18a. Priority is based on the type of circuit issuing the request and on whether a particular circuit is assigned a higher priority than its normal priority for a particular circuit. The dynamic change of the priority will be described later. For convenience of explanation and as shown in FIG. 8, the order of priorities by the priority handler and state machine 18d is now shown in Table 2.

[Table 2] As an example to illustrate the information in Table 2, the first pending request is from host processor 12 (ie, priority 4) and the second request is from peripheral interface 14b.
If the priority is high from (i.e., priority 3),
DRAM by priority handler and state machine 18d
The next request issued to controller 18a corresponds to a high priority request from peripheral interface 14b due to its high priority value. Other examples are evident from Table 2 and from the following description of FIG.

To further illustrate the above discussion of priority considerations, FIG. 9 illustrates a flow diagram of a method generally designated at 80 and illustrating the desired operation of the associated components shown in FIG. The method 80 begins at step 82, where the access request of the request stack 18c is analyzed by the priority handler and the state machine 18d. As will be appreciated from the conclusions of the description of FIG. 9, at any time, the occurrence of step 82 is such that one or more requests are pending in request stack 18c. In any case, for an access request of request stack 18c, method 80 proceeds to step 8
Go from step 2 to step 84.

At step 84, the priority handler and state machine 18d determines whether there is one or more pending requests in the priority stack 18c. If so, method 80 proceeds from step 84 to step 86; otherwise, method 80 proceeds from step 84 to step 88. Step 86
The priority handler and state machine 18d issues a memory access request to the DRAM controller 18a corresponding to the access request in the request stack 18c having the highest priority. Therefore, Table 2 above shows the requests thus selected for the service. It should also be noted that FIG. 9 illustrates step 86 'in dashed lines, which step is included to indicate that the priority changes at any time in any of the various ways described below. In any case,
Step 86 issues a memory access request to DRAM controller 18a, which in the preferred embodiment should provide access to SDRAM 24 in the manner described above. Finally, recall that in the preferred embodiment, a single request source generally has only one pending request at a time, and thus there are no two pending requests of the same priority in such a case. However, if an embodiment is implemented in which multiple requests of the same priority from the same request source are pending, step 8
For 6, it may be desirable for step 86 to issue a memory request for an access request that is pending for the longest period. When a request is issued to DRAM controller 18a, method 80 returns from step 86 to step 84,
The above process is repeated until there is only a single pending access request, at which point method 80 proceeds to step 88.

At step 88, the priority handler and state machine 18d issues a memory access request to the DRAM controller 18a corresponding to a single access request in the request stack 18c. Thereafter, method 80 returns from step 88 to step 82, in which the system proceeds to request stack 1
If there is one request in 8c, either the next pending access request is processed or the process waits for the next request and proceeds as described above.

As introduced above, the request stack 18c
The priority associated with certain types of pending requests may dynamically change from an initial value. In particular, in the preferred embodiment, there are three sources: (1) Video and LC
D controller 20, (2) peripheral interface 14
b, (3) the priority associated with the access request from each of the SDRAM 24 automatic refresh may be changed. To further illustrate the priority changes for these three different request sources, each will be described separately below and the reader's attention will again be directed to FIG. 8 for the following description of another advantage of the traffic controller 18. I want to be.

The priority corresponding to the video and the request from the LCD controller 20 is the FIFO 18b (this can be video or
(Which provides video data to the LCD controller 20) based on how much data remains. In particular, if the FIFO 18b is almost empty at a particular time, requests issued by the video or LCD controller 20 during that time will be assigned a relatively high priority,
Conversely, if the FIFO 18b is barely empty at a particular time, during which time requests from the video or LCD controller 20 will be assigned a normal (ie, relatively low) priority.
To accomplish this indication, FIFO 18b is coupled to provide control signals to priority handler and state machine 18d. In addition, the video and LCD controller 2 are already associated with the priority resulting from the availability of the FIFO 18b.
If the request from 0 is undecided and a normal priority is initially assigned, and if the FIFO 18b reaches a certain degree of freeness, the priority is switched to a high priority. The definition of the empty state of the FIFO 18b can be selected by those skilled in the art. For example, from Table 2, it should be appreciated that access requests from the video and LCD controller 20 can be assigned either a priority of 1 (high priority) or a priority of 7 (normal priority). In the preferred embodiment, a single threshold storage is selected for the FIFO 18b to determine which priority to assign, and if the FIFO 18b has less video data than this threshold, the video and LCD controller 20 issues a Alternatively, pending requests are assigned a high priority, whereas if the amount of data in the FIFO 18b is equal to or greater than this threshold, the video and LCD controller 20
Issued or pending requests from are usually assigned a priority.
However, those skilled in the art can select different methods of priority selection, and do not need to limit the priority to the two categories. For example, another approach may be to use linear steps from one to a large number, such as one to five steps. In this case, when the FIFO 18b is 1/5 or less, an access request from the video and LCD controller 20 is assigned a priority value of 1. As another example, when the FIFO 18b is 4/5 or more, a priority value of 5 is assigned to an access request from the video or LCD controller 20.

The priority corresponding to the access request from the peripheral interface 14b is initially assigned a normal value, but is dynamically changed to a higher value based on how pending the request is. In this regard, the traffic controller 18 includes a timer circuit 1 including a programmable register 18e _R for storing an 8-bit count threshold.
8e. Thus, when an access request from the peripheral interface 14b is first stored in the request stack 18c, it is assigned a normal priority, and from Table 2, this normal priority for other priority is a value of 5. It is recognized that. However, when this request is stored, the timer circuit 18e starts counting. If the count of timer circuit 18e reaches the value stored in programmable register 18e _R before the pending request is serviced,
Timer circuit 18e issues a control signal to priority handler and state machine 18d to change the access request from normal to high. Referring again to Table 2, this high priority over other priorities is a value of three. If the request is serviced before the timer circuit 18e reaches its programmed limit, the count is reset and the next pending peripheral request is analyzed. In addition, while the above description refers only to a single peripheral request, alternative embodiments maintain separate counts if one or more peripheral requests are pending in request stack 18c, where Each separate count starts when the corresponding request is stored.

The priority corresponding to the automatic refresh is initially assigned a normal priority, but is dynamically changed to a higher value based on how many requests remain pending. Before going into the details of this process, note that all banks must first be refreshed within the refresh interval, as a background to SDRAM memory. For most SDRAMs currently on the market, this time is typically standardized to 64 milliseconds. During this 64 ms, all banks must be refreshed, which means that a certain number of required automatic refresh requests (eg, 4
k) must be sent to SDRAM.
As is known in the art, an auto-refresh request does not include an address, but instead causes the SDRAM to increment a pointer to an area of memory in response to receipt of the request. Typically, this area is multiple rows, and for multiple bank memories, the same row in each of the multiple banks is refreshed in response to a single automatic refresh request. Finally, as a background of the automatic refresh, in the related art, there are generally two methods for issuing an automatic refresh request to the SDRAM. Here, the first method is that the automatic refresh request is issued at regular time intervals during the refresh period. The second method is to issue a refresh request, and in response to a single command, in response to the command, refresh all lines in all banks in order. However, it is noted that embodiments of the present invention have disadvantages with each of these prior art schemes. For example, if the auto-refresh requests are equally spaced, each time one of the requests is received and applied to SDRAM 24, this will cause all banks of memory to be precharged. However, such a result reduces the advantage of keeping the row active for a significant period of time as implemented by the present invention. As another example, if a single command is issued to refresh all rows in all banks, memory is not available to all request sources during this refresh period, which is a complex system. Harmful. Accordingly, the preferred embodiment overcomes these shortcomings, as described immediately below.

In the preferred embodiment, the automatic refresh is implemented by a priority handler and state machine 18d that sends bursts of automatic refresh requests to the DRAM controller 18a. Generally and as shown below, the bursts are relatively small, such as bursts of 4, 8, or 16 autorefresh requests. Therefore, in response to these requests, the SDRA
There is a period during which M24 is precharged, which is much more than issuing 4096 requests consecutively and generating a precharge in response to all of these requests within a single time frame. short. In addition, other requests (higher priority) can be serviced by the priority handler and state machine 18d during these burst times. In fact, many of these other requests are directed to already active rows, so during this time these rows are not disturbed by the refresh operation (ie,
Not precharged). Turning now to the implementation details of these operations, the traffic controller 18 determines whether the automatic refresh burst size (eg, 4, 8,
16) programmable register 18f for storing
A timer circuit 18f including _R is included. In response to the reset of the timer circuit 18f, the programmable register 18f _R
A number of burst requests indicating a number in the request stack 1
8c with a normal priority (for example, 6 in Table 2). At this point, while the burst of the automatic refresh request is not determined, the timer circuit 18f starts progressing toward the timeout value (for example, 256 microseconds). FIG.
As described in detail above in connection with, the priority handler and state machine 18d proceeds by issuing a request to the DRAM controller 18a in response to the relative priority of the pending request in the stack 18c. Thus, when the requests of the priority level 6 arrive, these pending automatic refresh requests are issued to the DRAM controller 18a.
Thus, one of two events occurs first while timer circuit 18c is progressing toward its timeout value. One event is that all pending automatic refresh requests are issued to the DRAM controller 18a, and the other event is when the timer circuit 18f reaches its timeout value. DR of all pending automatic refresh requests
When issued to the AM controller 18a, the timer circuit 18
f is reset to zero and another burst of autorefresh requests is added to request stack 18c. Conversely, if the timer circuit 18f reaches its timeout value while one or more automatic refresh requests of the previous burst are pending, the priority handler and state machine 18d
Dynamically increases the normal priority of the pending automatic refresh request to a high priority (for example, 2 in Table 2). In addition, the timer circuit 18f is reset to zero again and another burst of normal priority automatic refresh requests is sent to the request stack 1
8c. However, as method 80 continues to process pending requests, a significant change in priority (eg, 6
When 2) is given, the chance of servicing an automatic refresh request with a higher priority is considerably increased.

From the foregoing, those skilled in the art will recognize numerous advantages of the automatic refresh methodology in the preferred embodiment. For example, bursts of automatic refresh requests generally avoid precharging the bank too frequently. In contrast, if the auto-refresh command is selected to be evenly spread within the maximum refresh interval, the auto-refresh command will be applied to the SDRAM 24 every 15.62 microseconds (ie, 64 milliseconds / 4096 lines = 15.62 microseconds). Sent to In this way, all banks are precharged every 15.62 microseconds. In contrast to and looking at the preferred embodiment which groups auto-refresh request commands into bursts,
Priority capabilities allow auto-refresh requests to be left pending, often allowing them to service during gaps between higher priority requests. This increases the time between two overall precharges. For example, 16
If the auto refresh requests are clustered, the gap between the two global precharges (DCAB commands) is 250 microseconds. This clearly illustrates the advantage of relating this automatic refresh burst mechanism to the DRAM controller 18a. This burst of automatic refresh can, of course, be interrupted by a higher priority request.

In ending this description of priority, Table 2
Note that there are two types of access requests with priorities that cannot be changed. The first of these access requests includes access requests received from the SBUS, most notably, access requests from the host processor 12. In this regard, it should be noted that during normal operation, that is, when other requests have not been changed to have a higher priority, host processor 12 has the highest priority. Thus, there is usually a sufficient gap between the times that the host processor 12 needs access to the memory, and during these gaps from other request sources given normal priority. It can be expected that access requests can be serviced. However, if these gaps are not sufficient, the priority scheme of the preferred embodiment will further prioritize and service these other access requests,
Thus, they can be serviced without creating locking problems to the system. A final item related to the priority of the preferred embodiment as shown in Table 2 is that access requests for transfers from flash memory 26 to SDRAM 24 are always given the lowest priority (priority 8). Please be careful.

To illustrate other inventive advantages that are desirably included in the traffic controller 18, FIG. 10 illustrates a method 90 also performed by the priority handler and state machine 18d and directed to burst requests. I do. Initially, it should be noted that the method 90 occurs in parallel with the method 80 described in connection with FIG. The method 90 begins at step 92, where the access request stored in the request stack 18c is selected for analysis by the priority handler and the state machine 18d. Next, at step 94, the priority handler and state
The machine 18d determines whether the pending access request is a burst request, and if so, determines whether the size S of the requested number of bytes is greater than a predetermined base size / number of bytes B. As an example, assume that B is equal to eight. If S is greater than B, the method 90 proceeds to step 96, while if S is less than or equal to B, the method 90 returns to step 92 and proceeds to analyze the next pending access request.

At step 96, the priority handler and state machine 18d effectively splits the burst request from step 94 into multiple burst requests. The advantages of this operation will be described later, but first a description of the technique of the preferred embodiment of request splitting will be presented. Preferably, this operation is performed by replacing the burst requests from step 94 with S / B burst requests, where each replacement burst request is a burst of B bytes. For example, assume that step 94 is performed for a burst request size having a size S equal to 32 bytes. In this case, S is greater than B (ie, 32> 8) and the method proceeds to step 96. Stage 9
6, in this example, the priority handler and state machine 18d sends a 32-byte access request to four access
Replace with a burst request (ie, S / B = 32/8 = 4), where each new request is a burst of 8 bytes (ie, B = 8).

The traffic controller 18 operates as described above.
Note that in the preferred embodiment, which includes DRAM controller 18a, the split requests are indicated by DRAM controller 18a in such a way as to be considered as a continuous burst request, thereby allowing for more efficiency with respect to address transmission. In particular, when a burst request is split into multiple requests, the first request is the DRAM controller 18a
And is coded as shown in Table 5 below. Generally, for each of the remaining multiple requests, each is indicated as a continuous request SREQ to the DRAM controller 18a. Thus, for the example in which the burst request from the request source S1 is divided into four requests, the DRAM controller 18a
Requests issued to: (1) REQ [s1]; (2) SREQ [s
1]; (3) SREQ [s1]; (4) SREQ [s1]. Returning now to the advantage of this difference, the DRAM controller 18a generally has the SDRAM 24 for continuous access in some cases.
Recall that it operates to keep the row active. In the present example, the DRAM controller 18a
It is known that when a request is received, the instruction directs the request to a data group that follows the immediately preceding request in sequence. Therefore, two advantages arise from this. First
In a preferred embodiment, the traffic controller 18 responds to the SREQ request by the DRAM controller 18a.
No extra addresses are transmitted, thus reducing overhead. Second, by using the increment of the currently accessed address, the DRAM controller 18a
Can determine whether the data retrieved by the SREQ request is on the same line as the currently active one,
If so, causing an access of that data without pre-charging the row between the time of the previous access and the time of the access corresponding to the SREQ access. However, finally, in the preferred embodiment, the DRAM controller 18a provides a continuous
It is also determined from the number of SREQ accesses and the burst size whether or not a page crossing has occurred. If a page crossing has occurred, the DRAM controller 18a precharges the currently accessed row and responds to the SREQ request. Activate next line.

Also, in the preferred embodiment, given the priority capability of the priority handler and state machine 18d,
Further, while the split request is still pending, the traffic controller 1
Note that if 8 is received, multiple requests resulting from a split burst request will be handled differently with respect to REQ and SREQ designations. In particular, in such a case, the REQ indication is again given to the first of the multiple requests, but also to the first request following the inserted higher priority request. For example, again, the first burst request from request source s1 is 4
Assume that the request has been split into two requests, but that a higher priority request has been received after sending the second of the four split requests to DRAM controller 18a. In this case, the order of requests to the DRAM controller 18a is:
(1) REQ [s1]; (2) SREQ [s1]; (3) REQ [s2];
(4) REQ [s1]; (5) SREQ [s1]. in this way,
The request (2) is a continuous request to the same row address as the request (1), and the request (5) is a continuous request to the same row address as the request (4). However, a higher priority request (3) is inserted between requests (2) and (4). Therefore, again, each SREQ is processed in the manner described above,
No address transmission to the DRAM controller 18a is required, and the same row as the preceding request will be accessed.

At the end of method 90, after step 96, it returns to step 92 to analyze the next pending access request. Finally, note that in connection with step 96, the above example assumes that B can be evenly divided by S. However, if not, step 96 replaces the single access request with a burst request integer equal to one plus an integer portion of the S / B, where each of the S / B requests is a burst of B bytes. And the additional request is preferably the number of remaining bytes. For example, for a pending DMA burst request where S is equal to 35, step 96
Will search the request for bursts of 8 bytes each.
One access request and a fifth access request of a 3-byte burst.

Although the method 90 has been described, when combined with the ability to hold the row active, as described in connection with the DRAM controller 18a above, the priority 90 described further in connection with FIGS. Note that combining with the degree aspect can provide unique advantages. To appreciate this, recall the invention background section of this document, which describes how burst size affects efficiency. In particular, it was stated that some prior art schemes increased the burst size to avoid overhead penalties, but this scheme prevented long bursts from accessing other circuits during the burst. There is also the problem of doing so. In contrast, the method 90 allows a long burst request to be broken into a number of smaller bursts. However, in the absence of a higher pending priority request, under the teachings of the present invention, these small bursts
Issued continuously by the DMA controller to the DRAM controller. In addition, because the bursts are accessing consecutive memory locations, each successive small burst accesses a row of the SDRAM 24 that is actively held,
Therefore, there is no overhead between successive accesses corresponding to each successive burst. In addition, when the DMA controller receives a higher priority request, the present invention can effectively provide a valid interrupt, albeit a long burst. In particular, since the long burst was broken into multiple small bursts, the high priority request was inserted to occur between the occurrences of the two small bursts, and servicing that high priority request would require that all of the small bursts be completed. Successive small bursts are serviced again. In this way, it is believed that a high priority request is inserted substantially in the middle of what was originally a long burst request, and that the burst can be restarted with minimal overhead.
In conclusion, therefore, the present invention enables large effective bursts in many cases, and otherwise can service higher priority requests without waiting for long bursts to complete.

Although various general and special features of the traffic controller 18 have been described in detail in connection with the SDRAM 24, this document is provided here to illustrate to one skilled in the art one way of achieving the various foregoing operations. End with the following presentation of the various ports and signals. In this regard, Table 3 below shows the traffic controller 18
List the general interface ports to 4.

[Table 3]

In addition, the following signals in Table 4 may include traffic from various circuits requiring DMA access or direct access (eg, host processor 12, DSP 14a, peripherals from peripheral interface 14b, video or LCD controller 20). Illustrates a preferred embodiment method of the traffic controller 18 for providing an access request to the SDRAM 24 in response to an access request issued to the controller 18, and immediately following Table 5 implements different access types. The states of these signals are illustrated.

[Table 4]

[Table 5]

^* Access is generated by the traffic controller 18. Traffic controller 1
The two requests by 8 are not generated at the same time, so only one bit is active at a time, which avoids having to decode the request. Before the traffic controller 18 sends a continuous request, it must first receive a / SDRAM_Req_grant signal. This authorization indicates that the request has been captured and is currently being processed. ^{** When the} MRS command is executed to program the SDRAM internal control registers, the DMA data bus is placed on the SDRAM address bus. ^{*** When} SET_MODE_SDRAM is read, local registers from the SDRAM controller module (not SDRAM internal registers) are read.

[0062] Finally, Table 6 below illustrates yet another control signal on the control bus 24 _c between the traffic controller 18 and SDRAM 24.

[Table 6]

From the above description, it can be seen that the above embodiment reduces memory access latency and can be implemented in a DRAM controller, a DMA system, or both, and in any case can provide various improvements over the prior art. While this embodiment has been described in detail in addition to the above teachings, it should be noted that various substitutions, modifications or changes may be made to the above description without departing from the scope of the invention. . For example, different control signals may be used to achieve the described functions, especially if different types of memory are associated with DRAM control. As another example, while FIGS. 4, 8, and 9 illustrate a generally continuous method by way of a flowchart, the preferred embodiment implements a state machine to perform these steps, and thus the flow is a flowchart. It should be understood that the flow is not continuous as shown in FIG. As yet another example, various priority concepts have been described, but the order of some of the above request sources may be re-arranged or even others (eg, DSP 14a) removed from the priority scheme. Others may be implemented to reduce waiting time. As yet another example, wireless data platform 10 is a general block diagram. Therefore, other features can be included or modified, but such
Not shown to simplify the illustration of the control plane and to focus on the description. As a simple memo of possible functions, not shown, the platform 10 includes an I / O controller and an RA.
Includes memory such as M / ROM. Further, a plurality of devices can be coupled to the wireless data platform 10 as peripherals via an I / O controller or via a peripheral interface 14b. Such devices are:
Smart card, keyboard, mouse, or Universal Serial Bus ("USB") port or RS232
Includes one or more serial ports, such as a serial port. As an example of a specific change to the platform 10,
The separate caches of the processor 12 and the DSP 14a can be combined into an integrated cache. In addition, a hardware acceleration circuit is an optional item for accelerating the execution of a language such as JAVA, but this circuit is not necessary for the operation of the device. Finally, although the illustrated embodiment shows a single DSP, multiple DSPs (or other coprocessors) can also be coupled to the bus. As a final example, Platform 1
It should be understood that 0 is merely an example, and that many of the concepts of the present invention may be implemented in other systems having either or both DRAM control and DMA control. Accordingly, the above description, examples thereof, and other matters which can be ascertained by those skilled in the art given the present teachings should help illustrate the scope of the invention as set forth in the appended claims.

[Brief description of the drawings]

FIG. 1 is a prior art timing diagram for issuing an access signal by a DRAM controller in response to four consecutive memory requests.

FIG. 2 is a block diagram of a wireless data platform implementing the embodiment.

FIG. 3 is a block diagram illustrating details of an SDRAM 24 and a DRAM controller 18d in FIG. 2;

FIG. 4 is a flow diagram of an embodiment for processing a memory access request by a DRAM controller 18d to reduce system latency.

FIG. 5 is a timing chart of issuing an access signal according to the method of the flowchart of FIG. 4;

6 is a timing diagram of access signal issuance generated in response to four consecutive memory requests according to the method of the flowchart of FIG.

FIG. 7 is a more detailed diagram of the DRAM controller 18a shown in FIG. 3 and further described in the illustrations of FIGS. 4-6.

FIG. 8 is a block diagram illustrating details of the traffic controller 18 of FIG. 2 in connection with various priority aspects.

FIG. 9 is a flow diagram of an embodiment of processing a memory access request by the traffic controller 18 to reduce system latency using various priority considerations.

FIG. 10 shows a relatively large burst access request
5 is a flowchart of an embodiment of processing a memory access request by the traffic controller 18 to reduce system latency by splitting into one or more smaller mars and access requests.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 General purpose data platform 12 Host processor 14b Peripheral interface 16 DMA interface 18 Traffic controller 18a DRAM controller 18b FIFO 18c Request stack 18d Priority handler and state machine 20 Video or LCD controller 24 SDRAM 30 Comparison logic and state machine

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Sergi Lasserre, France, Saint-Jean-de-Cannes, Rue du Marceau 29 (72) Inventor, Dominique D'Amberne, France Bueneuve, Le La Rival Bachman Bee, Shman Basse Ginestiere 47 F term (reference) 5B060 AB13 AB19 CD04 5B061 BA03 DD01 DD06 DD09 DD11 RR02

Claims (2)

[Claims] 1. A memory controller circuit coupled to a memory having a plurality of rows, the circuit receiving a signal representing a request to access the memory, wherein the first signal representing a first request to access the memory is received. A second signal received by the circuit and including a first address of the memory, and representing a second request to access the memory, wherein the second signal is received by the receiving circuit after the first signal and includes a second address of the memory; A circuit; a determining circuit for determining whether the second address is directed to any of the same plurality of rows as the first address; and issuing a control signal to the memory in response to receiving a signal representing a request to access the memory. The control signal generates a first memory access in response to a first request and issues a second memory access in response to a second request. Responsive to a determining circuit that determines whether the second address is directed to any of the same plurality of rows as the first address.
A memory controller circuit coupled to the memory having a plurality of rows for issuing the control signal to the memory so as to keep the same of a plurality of rows active during the first and second accesses. 2. A computing system, comprising: a memory having a plurality of rows; a circuit for issuing a request to access the memory; and a memory controller, the circuit receiving a signal representing the request to access the memory. A first signal representing a first request to access the memory is received by the receiving circuit and includes a first address of the memory, and a second signal representing a second request to access the memory is received by the receiving circuit after the first signal. A signal receiving circuit including a second address of the memory, a determining circuit for determining whether the second address is directed to any of the same plurality of rows as the first address, and a request to access the memory. A circuit for issuing a control signal to a memory in response to receiving a signal, the control signal comprising a first memory access response in response to a first request. And an issuing circuit for generating a second memory access in response to a second request; and determining whether the second address is directed to any of the same plurality of rows as the first address. In response to the decision circuit to decide,
A memory controller for issuing control signals to the memory to keep the same of a plurality of rows active during the first and second accesses.