JPH0828390B2 - Pad formation method - Google Patents
Pad formation methodInfo
- Publication number
- JPH0828390B2 JPH0828390B2 JP2338108A JP33810890A JPH0828390B2 JP H0828390 B2 JPH0828390 B2 JP H0828390B2 JP 2338108 A JP2338108 A JP 2338108A JP 33810890 A JP33810890 A JP 33810890A JP H0828390 B2 JPH0828390 B2 JP H0828390B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- pattern
- pad
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0504—14th Group
- H01L2924/05042—Si3N4
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関するもので、特に
パッドの形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a pad forming method.
従来の技術 近年、半導体はますます進歩し高集積度で高速動作を
目指したLSIが開発されている。高速動作を要求されるL
SIではデバイスの高速性はもちろんのことパッド抵抗に
よる遅延が問題となっている。特に超高速動作が可能な
GaAsICやマイクロ波帯で使用するHEMTでは厚膜のAuパッ
ドが用いられている。2. Description of the Related Art In recent years, semiconductors have advanced more and more, and LSIs aiming at high-speed operation with high degree of integration have been developed. L that requires high-speed operation
In SI, not only the speed of the device but also the delay due to the pad resistance is a problem. Especially high speed operation possible
HEMTs used in GaAs ICs and microwave bands use thick Au pads.
第３図は従来のHEMTに用いられているAuパッド形成工
程の製造方法を説明する製造工程の断面図である。第３
図において21はGaAsHEMT構造基板、22は第１の金属、23
はAu薄膜、24はフォトレジストパターン、25はメッキA
u、26は絶縁膜、27は絶縁膜開口部である。FIG. 3 is a cross-sectional view of the manufacturing process for explaining the manufacturing method of the Au pad forming process used in the conventional HEMT. Third
In the figure, 21 is a GaAs HEMT structure substrate, 22 is the first metal, and 23
Is Au thin film, 24 is photoresist pattern, 25 is plating A
u and 26 are insulating films, and 27 is an insulating film opening.
ソース・ドレインオーミック電極、およびゲートショ
ットキー金属を形成したGaAsHEMT基板21上に基板21とAu
薄膜23の密着性がよくないので第１の金属22として例え
ばTiを500Å蒸着した後、Au薄膜23を1000Å蒸着により
形成する（ａ）。次に所望のパッドパターンを抜きのフ
ォトレジストパターン24で形成し、メッキ法により厚さ
１μｍのメッキAuパターン25を形成してパッドとする
（ｂ）。次に前記フォトレジストパターン24を除去し、
前記メッキAuパターン25以外のAu薄膜23を除去し、さら
に第１の金属21を除去して配線を形成する（ｃ）。次に
全面に保護膜となる絶縁膜26を形成し、所望のパターン
でパッド部の絶縁膜開口部27を形成してパッド部が完成
する。Substrate 21 and Au on GaAs HEMT substrate 21 with source / drain ohmic electrodes and gate Schottky metal formed
Since the adhesion of the thin film 23 is not good, for example, Ti is vapor-deposited as the first metal 22 by 500 Å and then the Au thin film 23 is formed by 1000 Å vapor deposition (a). Next, a desired pad pattern is formed by using a photoresist pattern 24 without the plating, and a plated Au pattern 25 having a thickness of 1 μm is formed by a plating method to form a pad (b). Next, the photoresist pattern 24 is removed,
The Au thin film 23 other than the plated Au pattern 25 is removed, and then the first metal 21 is removed to form wiring (c). Next, an insulating film 26 serving as a protective film is formed on the entire surface, and insulating film openings 27 of the pad portion are formed in a desired pattern to complete the pad portion.
発明が解決しようとする課題 しかしながら、第３図で説明したようなパッドの形成
方法では、Au薄膜除去時にメッキAuもエッチングされる
ためパッド厚が小さくなるという問題やまた、組立時の
ワイヤボンドの際、メッキAu25表面荒れによりワイヤボ
ンド不良が発生するといった問題があった。However, in the method of forming a pad as described with reference to FIG. 3, since the plating Au is also etched when the Au thin film is removed, the thickness of the pad becomes small, and the wire bond at the time of assembly is reduced. At that time, there was a problem that a wire bond failure occurred due to the surface roughness of the plated Au25.
本発明はAu薄膜を除去する時にパッド部の上面を絶縁
膜あるいは金属膜で覆うことによりパッド表面を保護
し、パッド厚が小さくならず、かつパッド表面荒れがな
いパッド形成方法を提供することを目的とする。The present invention provides a pad forming method that protects the pad surface by covering the upper surface of the pad portion with an insulating film or a metal film when removing the Au thin film, does not reduce the pad thickness, and does not roughen the pad surface. To aim.
課題を解決するための手段 前記したように本発明はAuパターンの膜減りや表面荒
れによるワイヤボンド不良という課題を解決するために
半導体基板上に第１の金属膜およびAu膜を全面に形成す
る工程と、全面に第１の絶縁膜を形成する工程と、所望
のパッドパターンをフォトレジストで形成し、エッチン
グにより前記第１の絶縁膜およびAu膜および第１の金属
膜を所望のパッドパターンに加工する工程と、前記フォ
トレジストを除去する工程と、全面に第２の絶縁膜を形
成する工程と、所望のパターンで前記パッドパターン上
に開口パターンを形成する工程と、前記開口パターンの
前記第２の絶縁膜および第１の絶縁膜を除去する工程と
からなる方法を提供する。Means for Solving the Problems As described above, according to the present invention, the first metal film and the Au film are formed on the entire surface of the semiconductor substrate in order to solve the problem of wire bond failure due to film loss and surface roughness of the Au pattern. Step, forming a first insulating film on the entire surface, forming a desired pad pattern with a photoresist, and etching the first insulating film, Au film and first metal film into a desired pad pattern. A step of processing, a step of removing the photoresist, a step of forming a second insulating film on the entire surface, a step of forming an opening pattern on the pad pattern with a desired pattern, and a step of forming the opening pattern And a step of removing the second insulating film and the first insulating film.
また本発明は、半導体基板上に第１の金属膜およびAu
薄膜を形成する工程と、前記Au薄膜上に所望のフォトレ
ジストパターンを抜きパターンで形成する工程と、前記
フォトレジストパターン内にAuを選択的にメッキ法で形
成する工程と、全面に第２の金属膜を形成する工程と、
リフトオフ法により前記メッキAuパターン上にのみ前記
第２の金属膜を残存させる工程と、メッキAuパターン部
外のAu薄膜を除去する工程と、第１の金属膜および第２
の金属膜を除去する工程と、全面に絶縁膜を形成する工
程と、前記メッキAuパターン上に所望の前記絶縁膜開口
部を形成する工程からなる方法を提供するものである。The present invention also provides a first metal film and an Au film on a semiconductor substrate.
A step of forming a thin film, a step of forming a desired photoresist pattern on the Au thin film in a blank pattern, a step of selectively forming Au in the photoresist pattern by a plating method, and a second step on the entire surface. A step of forming a metal film,
A step of leaving the second metal film only on the plated Au pattern by a lift-off method, a step of removing an Au thin film outside the plated Au pattern portion, a first metal film and a second
And a step of forming an insulating film on the entire surface, and a step of forming a desired insulating film opening on the plated Au pattern.
作用 本発明は上記の方法により、パッドとなるAuの上面に
絶縁膜あるいは金属膜を形成するために、パッド部以外
の基板上にある薄膜を除去する時に、パッドのAuの厚み
が減ることを防止できる。また、パッド表面が製造工程
の際に露出することもないので、パッド表面が荒れた
り、変質したりすることもなく清浄に保たれ、ワイヤボ
ンドする時に密着性のよいパッドを実現できる。Effect The present invention reduces the Au thickness of the pad when the thin film on the substrate other than the pad portion is removed in order to form the insulating film or the metal film on the upper surface of the Au serving as the pad by the above method. It can be prevented. Further, since the pad surface is not exposed during the manufacturing process, the pad surface is kept clean without being roughened or deteriorated, and a pad having good adhesion at the time of wire bonding can be realized.
実施例 本発明、パッド形成方法の第１の実施例を第１図
（ａ）〜（ｄ）に示す。第１図は本発明を用いて作製し
たAuパッドの製造工程断面図である。第１図において、
１は半導体基板、２は第１の金属、３はAu薄膜、４は第
１の絶縁膜、５はフォトレジストパターン、６は配線パ
ターン、７は第２の絶縁膜、８は開口部である。Embodiments A first embodiment of the pad forming method of the present invention is shown in FIGS. 1 (a) to (d). FIG. 1 is a cross-sectional view of a manufacturing process of an Au pad manufactured by using the present invention. In FIG.
1 is a semiconductor substrate, 2 is a first metal, 3 is an Au thin film, 4 is a first insulating film, 5 is a photoresist pattern, 6 is a wiring pattern, 7 is a second insulating film, and 8 is an opening. .
オーミック電極およびゲートショットキー電極を形成
したHEMT構造のGaAs半導体基板１上に金属である第１の
金属２として例えばTiを500Å蒸着し、その上にAu膜３
を8000Å蒸着により形成し、さらに第１の絶縁膜４とし
て例えばシリコン窒化膜を500Å形成する（ａ）。次に
所望の配線パターンをフォトレジストパターン５で形成
し、イオンシリングで前記フォトレジストパターン５を
マスクに前記第１の絶縁膜４、Au膜３および第１の金属
２をエッチングし、配線パターン６を形成する（ｂ）。
次に前記フォトレジストパターン５を除去し、全面に表
面保護膜用に第２の絶縁膜７として例えばシリコン窒化
膜を7000Å形成する（ｃ）。次に所望のパターンで前記
配線パターン６上の前記第２および第１の絶縁膜に開口
部８を形成する（ｄ）。On the GaAs semiconductor substrate 1 of the HEMT structure on which the ohmic electrode and the gate Schottky electrode are formed, for example, Ti as a first metal 2 is vapor-deposited by 500Å, and the Au film 3 is formed thereon.
Is formed by vapor deposition, and further, for example, a silicon nitride film is formed as 500 Å as the first insulating film 4 (a). Next, a desired wiring pattern is formed with the photoresist pattern 5, and the first insulating film 4, the Au film 3 and the first metal 2 are etched by ion schilling using the photoresist pattern 5 as a mask, and the wiring pattern 6 is formed. Is formed (b).
Next, the photoresist pattern 5 is removed, and, for example, a silicon nitride film is formed on the entire surface as a second insulating film 7 for a surface protective film by 7,000 Å (c). Next, openings 8 are formed in the second and first insulating films on the wiring pattern 6 in a desired pattern (d).
本発明の第１の実施例ではパッド金属であるAu膜３を
形成後直ちに第１の絶縁膜４を形成しているためAu膜３
の表面は保護されており、フォトレジストにさらされた
り、Au膜３表面をどの工程において直接処理されること
はない。このため、Au表面は安定であり、組立時のワイ
ヤボンドの際、密着不良等の不良は発生しない。In the first embodiment of the present invention, since the first insulating film 4 is formed immediately after the Au film 3 which is the pad metal is formed, the Au film 3 is formed.
The surface of the Au film 3 is protected and is not exposed to the photoresist, and the surface of the Au film 3 is not directly processed in any step. Therefore, the Au surface is stable, and defects such as poor adhesion do not occur during wire bonding during assembly.
次に本発明を用いた第２の実施例を第２図（ａ）〜
（ｅ）に示す。第２図において11は半導体基板、12は第
１の金属、13はAu薄膜、14はフォトレジストパターン、
15はメッキAuパターン、16は第２の金属膜、17は絶縁
膜、18は開口部である。Next, a second embodiment using the present invention is shown in FIG.
It shows in (e). In FIG. 2, 11 is a semiconductor substrate, 12 is a first metal, 13 is an Au thin film, 14 is a photoresist pattern,
Reference numeral 15 is a plated Au pattern, 16 is a second metal film, 17 is an insulating film, and 18 is an opening.
オーミック電極およびゲート電極を形成したHEMT構造
のGaAs半導体基板11上に第１の金属12として例えばTiを
500Å形成し、その上にAu薄膜13を1000Å形成する
（ａ）。前記Au薄膜13上に所望のフォトレジストパター
ン14を抜きパターンで形成し、前記フォトレジストパタ
ーン14内にAuをメッキ法で選択的に形成し、メッキAuパ
ターン15を形成する（ｂ）。次に全面に第２の金属膜16
として例えばTiを700Å蒸着により形成し、リフトオフ
法により前記メッキAuパターン15上にのみ前記第２の金
属膜16を形成する（ｃ）。メッキAuパターン15以外のAu
薄膜13をウエットエッチングにより除去し、さらに第１
の金属12および第２の金属16を同時に除去する（ｄ）。
その後、全面に保護膜になる絶縁膜17として、例えばシ
リコン窒化膜を8000Å形成し、前記メッキAuパターン15
上に所望の開口部18を形成する（ｅ）。For example, Ti is used as the first metal 12 on the GaAs semiconductor substrate 11 of the HEMT structure on which the ohmic electrode and the gate electrode are formed.
500 Å is formed, and 1000 Å of Au thin film 13 is formed thereon (a). A desired photoresist pattern 14 is formed on the Au thin film 13 in a blank pattern, and Au is selectively formed in the photoresist pattern 14 by a plating method to form a plated Au pattern 15 (b). Next, the second metal film 16 is formed on the entire surface.
For example, Ti is formed by 700Å vapor deposition, and the second metal film 16 is formed only on the plated Au pattern 15 by the lift-off method (c). Au other than plated Au pattern 15
The thin film 13 is removed by wet etching, and the first
The metal 12 and the second metal 16 are simultaneously removed (d).
Then, for example, a silicon nitride film is formed on the entire surface as an insulating film 17 serving as a protective film 8000 Å and the plated Au pattern 15
Form the desired opening 18 on top (e).
本発明第２の実施例ではメッキAuパターン15表面を第
２の金属膜16で保護し、Au薄膜13除去時のエッチングに
よる表面の荒れ防止と、パッド厚が減少するのを防止し
ている。そしてその後第１の金属膜12と同時に第２の金
属膜16を除去し、直ちに絶縁膜17を形成して表面を保護
している。In the second embodiment of the present invention, the surface of the plated Au pattern 15 is protected by the second metal film 16 to prevent the surface from being roughened by etching when removing the Au thin film 13 and to prevent the pad thickness from decreasing. Then, after that, the second metal film 16 is removed simultaneously with the first metal film 12, and the insulating film 17 is immediately formed to protect the surface.
また、本実施例において第１の金属と第２の金属とし
てともにTiを用い、しかも第１の金属膜厚より第２の金
属膜厚を大きくしておけば、第１の金属膜のエッチング
が完了しても第２の金属膜がパッド表面には残っており
表面は保護されたままであり、表面荒れや変質が起こっ
たりすることはない。Further, in the present embodiment, if Ti is used as both the first metal and the second metal, and if the second metal film thickness is made larger than the first metal film thickness, the etching of the first metal film is prevented. Even after the completion, the second metal film remains on the pad surface and the surface remains protected, so that the surface is not roughened or deteriorated.
なお本発明の第１および第２の実施例で第１の金属を
Ti、第２の金属をTiを用いて説明したがこれはCrであっ
ても良い。また絶縁膜もシリコン窒化膜を用いて説明し
たがシリコン酸化膜であってもよい。The first metal is used in the first and second embodiments of the present invention.
Although Ti and the second metal have been described using Ti, this may be Cr. Further, the insulating film has been described using the silicon nitride film, but may be a silicon oxide film.
発明の効果 本発明は、Auパッドの形成において、パッド表面に絶
縁膜を形成したり、金属膜を形成することによりAuパッ
ド表面を保護し、他の工程でのいかなる処理があって
も、パッド表面荒れやパッド厚減少を防止することがで
き、組立工程のワイヤボンドにおいても密着の良いパッ
ドが得られ、信頼性の高いデバイスが歩留りよく得られ
るので、その実用的効果は大きい。EFFECTS OF THE INVENTION The present invention protects the Au pad surface by forming an insulating film or a metal film on the pad surface in the formation of the Au pad, and the pad can be treated by any other process. Roughness of the surface and reduction of the pad thickness can be prevented, a pad with good adhesion can be obtained even in wire bonding in the assembly process, and a highly reliable device can be obtained with a high yield, so that its practical effect is great.
第１図（ａ）〜（ｄ）および第２図（ａ）〜（ｅ）はそ
れぞれ第１および第２の実施例におけるパッド形成方法
を説明するため工程断面図、第３図（ａ）〜（ｄ）は従
来のパッド形成方法を説明するための工程断面図であ
る。 1,11……半導体基板、2,12……第１の金属膜、３……Au
膜、４……第１の絶縁膜、13……Au薄膜、14……フォト
レジストパターン、15……パッド用メッキAuパターン、
16……第２の金属、７……第２の絶縁膜、17……絶縁
膜。1A to 1D and 2A to 2E are process cross-sectional views for explaining the pad forming method in the first and second embodiments, respectively, and FIGS. (D) is a process sectional view for explaining a conventional pad forming method. 1,11 …… Semiconductor substrate, 2,12 …… First metal film, 3 …… Au
Film, 4 ... First insulating film, 13 ... Au thin film, 14 ... Photoresist pattern, 15 ... Pad plating Au pattern,
16 ... second metal, 7 ... second insulating film, 17 ... insulating film.
Claims (3)
全面に形成する工程と、前記Au膜上に第１の絶縁膜を形
成する工程と、所望のパッドパターンをフォトレジスト
で形成し、エッチングにより前記レジスト下の前記第１
の絶縁膜および前記Au膜および前記第１の金属膜を所望
のパッドパターンに加工する工程と、前記フォトレジス
トを除去する工程と、全面に第２の絶縁膜を形成する工
程と、所望パターンで前記パッドパターン上に開口パタ
ーンを形成する工程と、前記開口パターンの前記第２の
絶縁膜および前記第１の絶縁膜を除去する工程とを有す
ることを特徴とするパッド形成方法。1. A step of forming a first metal film and an Au film on a whole surface of a semiconductor substrate, a step of forming a first insulating film on the Au film, and a desired pad pattern made of photoresist. Then, the first portion under the resist is etched by etching.
Process the insulating film, the Au film, and the first metal film into a desired pad pattern, removing the photoresist, forming a second insulating film on the entire surface, and forming a desired pattern. A pad forming method comprising: a step of forming an opening pattern on the pad pattern; and a step of removing the second insulating film and the first insulating film of the opening pattern.
形成する工程と、前記Au薄膜上に所望のフォトレジスト
パターンを形成する工程と、前記フォトレジストパター
ン内にAuを選択的にメッキ法で形成する工程と、全面に
第２の金属膜を形成する工程と、リフトオフ法により前
記メッキAuパターン上にのみ前記第２の金属膜を残存さ
せる工程と、メッキAuパターン部外の前記Au薄膜を除去
する工程と、前記第１の金属膜および前記第２の金属膜
を除去する工程と、全面に絶縁膜を形成する工程と、前
記メッキAuパターン上に所望の前記絶縁膜開口部を形成
する工程を有することを特徴とするパッド形成方法。2. A step of forming a first metal film and an Au film on a semiconductor substrate, a step of forming a desired photoresist pattern on the Au thin film, and selectively forming Au in the photoresist pattern. Forming by a plating method, forming a second metal film on the entire surface, leaving the second metal film only on the plated Au pattern by a lift-off method, and forming the second metal film outside the plated Au pattern portion. A step of removing the Au thin film, a step of removing the first metal film and the second metal film, a step of forming an insulating film on the entire surface, and a desired insulating film opening on the plated Au pattern. A method of forming a pad, comprising the step of forming a pad.
膜であり、かつ第２の金属膜厚が第１の金属膜厚より厚
いことを特徴とする請求項２記載のパッド形成方法。3. The second metal film is a metal film of the same kind as the first metal film, and the second metal film thickness is thicker than the first metal film thickness. Pad formation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2338108A JPH0828390B2 (en) | 1990-11-30 | 1990-11-30 | Pad formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2338108A JPH0828390B2 (en) | 1990-11-30 | 1990-11-30 | Pad formation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04206842A JPH04206842A (en) | 1992-07-28 |
| JPH0828390B2 true JPH0828390B2 (en) | 1996-03-21 |
Family
ID=18314991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2338108A Expired - Fee Related JPH0828390B2 (en) | 1990-11-30 | 1990-11-30 | Pad formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0828390B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0737887A (en) * | 1993-07-22 | 1995-02-07 | Mitsubishi Electric Corp | Method of forming, repairing, and modifying wiring |
-
1990
- 1990-11-30 JP JP2338108A patent/JPH0828390B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04206842A (en) | 1992-07-28 |
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