JPH08279733A - Oscillator circuit and semiconductor memory device - Google Patents

Abstract

PURPOSE: To provide an oscillator circuit subjected to power source bumping measures and to stabilize the operation of a refresh timer circuit or the like by providing a resistor of the oscillator circuit with a poly-Si layer formed on an insulated layer of a semiconductor substrate and arranging the poly-Si layer so as to be overlapped on first and second well areas. CONSTITUTION: The refresh timer circuit has seven inverter circuits (and capacitor C1 ), four circuits of them are operated as a delay circuit DL and the inverted signal of its output signal is fed back to the gate of an MOSFET QP3 constituting the leading inverter circuit, so that a ring oscillator is constituted. The charge potential of the capacitor C1 is monitored by the following inverter circuit provided with an N channel MOSFET QN7. A constant current source including MOSFET P4 and QN2 has a resistor R1 installed between these FETs. The resistor R1 is formed from poly-Si on the SiO2 insulated layer on the surface of P type semiconductor substrate. In order to avoid power source vamp, at a pseudo static RAM, an N well area NW1 is formed in a lower layer at the half of poly-Si layer consistuting the resistor R1 and an N well area NW2 is formed in the lower layer of the remaining part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit and a semiconductor memory device, and is particularly effective when applied to an oscillator circuit forming a refresh timer circuit and a pseudo static RAM (random access memory) including the oscillator circuit. Related technology.

[0002]

2. Description of the Related Art Dynamic RAM capable of high integration
There is a quasi-static type RAM having a basic configuration and designed to have an interface compatible with a normal static type RAM. Pseudo static RA
In addition to the normal write and read modes, M performs an address refresh mode and an auto-refresh mode in which a refresh operation is sporadically executed by external control, and a refresh operation is autonomously and periodically executed during battery backup, for example. It has a self-refresh mode. Pseudo static RAM
Includes a refresh counter for sequentially designating a word line to be refreshed in the auto-refresh and self-refresh modes, and a refresh timer circuit for periodically activating the refresh operation in the self-refresh mode. .

A pseudo static RAM having an auto-refresh and a self-refresh mode is disclosed in, for example, "Hitachi IC Memory Data Book", pages 229 to 23, published by Hitachi, Ltd. in March 1987.
It is described on page 4.

[0004]

In the pseudo-static RAM and the like described above, the average current consumption of the memory array in the self-refresh mode is large in proportion to the reciprocal of the refresh cycle, that is, the number of refreshes per unit time. Become. The refresh cycle in the self-refresh mode depends on the information holding ability of the memory cell itself and the stability of the refresh timer circuit that sets the refresh cycle, and this reduces the low level of the pseudo static RAM during battery backup. Power consumption is limited.

Therefore, prior to the present invention, the inventors of the present invention used a refresh timer circuit as an oscillation circuit having a small power supply voltage dependency and a pulse signal output from the oscillation circuit to start a predetermined refresh operation. Composed of a refresh timer counter circuit that forms a signal,
Further, the initial count value of the refresh timer counter circuit can be arbitrarily set by selectively cutting the corresponding fuse means, thereby stabilizing the refresh cycle of the pseudo static RAM and as much as possible for the memory cell. I thought about approaching my information retention ability.

However, the above-mentioned oscillation circuit requires a relatively large resistance value with a capacitor charged or discharged in a relatively long cycle in addition to its operating current being limited, and a relatively long distance between semiconductor substrate surfaces. And a polysilicon (polycrystalline silicon) resistor formed over the same. Therefore, for example, when a bump occurs in the power supply voltage of the circuit during the discharge period of the capacitor, the discharge current changes, or the value of the substrate capacitance parasitic between the polysilicon resistor and the semiconductor substrate is large. As a result, the power supply bumps cannot be absorbed rapidly, and the oscillation frequency of the oscillation circuit fluctuates. As a result, it becomes necessary to set the frequency of the oscillation circuit with a margin for the information holding capacity of the memory cell.

On the other hand, the oscillation circuit and the refresh timer counter circuit provided in the pseudo static RAM have the function of selectively switching their cycles, but have no way to test and confirm their oscillation characteristics and fluctuation characteristics. . Therefore, until the actual data on these characteristics are gathered and the variations are fully converged,
There is no choice but to set the refresh cycle by trial and error. This similarly requires a margin for the information holding capacity of the memory cell, limits the reduction in power consumption of the pseudo static RAM and contributes to an increase in the number of test steps.

A main object of the present invention is to provide an oscillation circuit provided with measures against power supply bumps and to stabilize the operation of a refresh timer circuit and the like.

Another main object of the present invention is to provide a test system capable of accurately and efficiently testing and confirming the characteristics of a refresh timer circuit and a semiconductor memory device including the refresh timer circuit.

Another main object of the present invention is to provide an output buffer for speeding up the operation, a voltage generating circuit for stabilizing the operation and a fuse circuit for simplifying the operation, and to provide a pseudo static RAM or the like. To provide a suitable layout method.

A further object of the present invention is to promote speeding up of a pseudo static RAM having a self-refresh mode and having the above-mentioned circuits while reducing power consumption and stabilizing operation.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, pseudo static RAM
Of a refresh timer circuit or the like, which constitutes a charge or discharge current path for the capacitor of the oscillation circuit included in the refresh timer circuit, and determines the frequency of the oscillation circuit,
In addition to the current mirror coupling with the MOSFET constituting the constant current source, it was coupled to the power supply voltage of the circuit under the portion corresponding to approximately one half of the polycrystalline silicon layer constituting the resistor for setting the current value of the constant current source. A well region is formed, and a well region coupled to the ground potential of the circuit is formed in the lower layer corresponding to the remaining half. A test mode in which the initial count value of the refresh timer counter circuit of the refresh timer circuit can be arbitrarily set to the pseudo static RAM or the like, for example, via an address input terminal, or a test in which the refresh cycle is supplied from a predetermined external terminal Prepare a test mode that can be set arbitrarily by the control signal. Further, a refresh timer circuit for setting a refresh cycle is provided in a pseudo static RAM having a self-refresh mode so that the cycle of its output signal can be selectively switched.

According to the above means, the discharge current of the capacitor of the oscillation circuit such as the refresh timer circuit is stabilized, and substantially the same parasitic capacitance is coupled between the polycrystalline silicon resistor and the power supply voltage and the ground potential of the circuit. Therefore, fluctuations in the power supply can be canceled out, and fluctuations in the oscillation frequency of the oscillation circuit due to power supply bumps or the like can be suppressed. Since the operating characteristics of the oscillation circuit and the refresh timer counter circuit and the address dependency of the information holding characteristics of the memory cell can be efficiently tested and confirmed,
The refresh cycle of the pseudo-static RAM can be set accurately and at a value closer to the information holding capacity of the memory cell. Furthermore, for example, a PS (pseudo) refresh mode, which is performed in a relatively long cycle at the time of battery backup, and a VS, which is performed in a relatively short cycle, between the activation of the pseudo static RAM.
It is possible to provide a pseudo static RAM or the like that can selectively realize the (virtual) refresh mode with one common semiconductor substrate. As a result, low power consumption can be promoted while stabilizing the operation of the pseudo static RAM.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

3.1. Basic configuration or method and its features 3.1.1. Block Configuration FIG. 1 shows a pseudo static type R to which the present invention is applied.
A block diagram of one embodiment of an AM selection circuit, a timing generation circuit, and a voltage generation circuit is shown. Also,
2 and 3 show the above pseudo static RAM.
A block diagram of one embodiment of the memory array, the direct peripheral circuit, and the data input / output circuit is shown. The circuit elements forming each block in FIGS. 1 to 3 are not particularly limited, but are formed on one semiconductor substrate made of P-type single crystal silicon. In addition, in FIG. 1 to FIG. 3 and the following circuit diagrams and the like, signal lines regarding input or output signals are shown starting from a bonding pad formed on the semiconductor substrate surface. The specific circuit configuration of each block and its operation and characteristics will be described later in detail.

Pseudo-static RAM of this embodiment
Has a basic structure of a dynamic RAM, and its memory array is composed of so-called one-element dynamic memory cells, whereby high integration of the circuit and low power consumption can be achieved. Further, X address signals X0 to X10 and Y address signals Y11 to Y18 are input via separate address input terminals A0 to A10 and A11 to A18, respectively, and further, as a control signal, a chip enable signal CEB and a write enable signal WEB. By providing the output enable signal OEB and the output enable signal OEB, an input / output interface compatible with a normal static RAM is provided.

Further, the pseudo-static RAM is an address refresh mode in which a refresh address is specified from the outside to perform a one-time refresh operation (here, the type of system such as the refresh operation and the test operation is referred to as a mode. In addition, the actual memory access in each mode etc. is called an operation cycle, for example, an address refresh cycle. Has an auto refresh mode for performing a refresh operation, and by using the refresh counter RFC and the built-in refresh timer circuit TMR and refresh timer counter circuit SRC, And the refresh operation relating to word line autonomously and a self-refresh mode for intermittently executed at a predetermined cycle.

In this embodiment, the output enable signal OEB is also used as the refresh control signal RFSHB although it is not particularly limited.
The operation mode of the pseudo static RAM is selectively set by the EB and the write enable signal WEB.

In FIG. 1, a chip enable signal CEB, a write enable signal WEB and an output enable signal OEB, ie, a refresh control signal RFSHB, which are externally supplied as a start control signal, are passed through corresponding input buffers CEB, WEB and OEB, and timing. It is supplied to the generation circuit TG. This timing generation circuit TG
From the X address buffer XAB to the 3-bit complementary internal address signals B X0, B X1 and B X10 (here, for example, the non-inverted internal address signal BX0 and the inverted internal address signal BX0B are combined together.
It is expressed as B X0. In addition, a so-called inverted signal or the like that is selectively brought to a low level when it is validated is indicated by adding B to the end of the name, but in each drawing, a straight line is added above the name of the inverted signal or the like. In some cases, it is attached with. The same shall apply hereinafter) is supplied. Timing generation circuit T
G is the chip enable signal CE, as will be described later.
B, write enable signal WEB, output enable signal OEB, and complementary internal address signals B X0, B X1
And B X10 based forms various timing signals necessary for the operation of each circuit block of the pseudo-static RAM.

On the other hand, the 11-bit X address signals X0 to X10 supplied from the outside via the corresponding address input terminals A0 to A10 are supplied to one input terminal of the X address buffer XAB, although not particularly limited thereto. The 8-bit Y address signals Y11 to Y18 are supplied to the Y address buffer YAB. The other input terminal of the X address buffer XAB is supplied with 11-bit refresh address signals AR0 to AR1 from the refresh counter RFC.
0 is supplied. Further, in the X address buffer XAB, the inverted timing signal φ from the timing generation circuit TG is supplied.
refB and φxlB are supplied, and the inverted timing signal φylB is supplied to the Y address buffer YAB. Here, the inversion timing signal φrefB is selectively set to a low level when the pseudo static RAM is brought into a selected state in the auto refresh mode or the self refresh mode, as will be described later, and the timing signals φxl and φyl are pseudo static. When the type RAM is in the selected state, X address signals X0 to X10 or refresh address signals AR0 to AR10 or Y
When the levels of the address signals Y11 to Y18 are determined, they are selectively set to the low level.

The X address buffer XAB is supplied with X address signals X0 to X0 through an external terminal when the pseudo static RAM is selected in the normal write or read mode and the inversion timing signal φrefB is set to the high level. X10 is fetched and held in accordance with the inverted timing signal φxlB. Further, when the pseudo static RAM is selected in the refresh mode and the inversion timing signal φrefB is set to the low level, the refresh address signals AR0 to AR10 supplied from the refresh address counter RFC are fetched and held according to the inversion timing signal φxlB. The X address buffer XAB further includes X address signals X0 to X10.
Alternatively, complementary internal address signals B X0 to B X10 are formed based on the refresh address signals AR0 to AR10. Of these, the lower 2 bits of the complementary internal address signal B
As described above, X0 and B X1 are supplied to the timing generation circuit TG, and the 3-bit complementary internal address signal B X1 is supplied.
2, B X3 and B X10 are supplied to the word line selection drive signal generation circuit PWD. The remaining 6-bit complementary internal address signals B X4 to B X9 are supplied to the X predecoder PXD. The complementary internal address signals B X2 to B X9 are also supplied to the X system redundancy circuit XR.

As will be described later, each memory array of the pseudo static RAM is provided with four redundant word lines and eight sets of redundant complementary data lines. X system redundant circuit XR
Among them, (XRU, XRD) compares the defective address assigned to each redundant word line with the complementary internal address signals B X2 to B X9 supplied via the X address buffer XAB at the time of memory access. Collate. As a result, when all these addresses match, the corresponding inverted redundant word line selection signal XR0B ...
XR3B is selectively set to low level. The inverted redundant word line selection signals XR0B to XR3B are supplied to the redundant word line selection drive signal generation circuit PRWD provided along with the word line selection drive signal generation circuit PWD.

The word line selection drive signal generation circuit PWD is
The complementary internal address signals B X2, B X3 and B X10
And the word line drive signal φxG supplied from the word line drive signal generation circuit φXG.
00U to X11U and X00D to X11D
Are selectively formed. Further, the redundant word line selection drive signal generation circuit PRWD, based on the word line drive signal φx, the inverted redundant word line selection signals XR0B to XR3B and the complementary internal address signal B X10, the corresponding redundant word line selection drive signal XR0U to XR3U or XR0D ~
XR3D is selectively formed. Here, the word line drive signal φx is set to a predetermined boost level that exceeds the power supply voltage of the circuit, and the word line selection drive signals X00U to X11.
U (X00D to X11D) and redundant word line selection drive signals XR0U to XR3U (XR0D to XR3D)
Similarly, the boost level is set.

The X predecoder PXD sequentially combines the complementary internal address signals B X4 to B X9 by 2 bits and decodes them to decode the corresponding predecode signal AX4.
50 to AX453, AX670 to AX673 and A
X890 to AX893 are alternatively formed. These predecode signals are commonly supplied to each X decoder.

Similarly, the Y address buffer YAB converts the Y address signals Y11 to Y18 supplied through the external terminals into the inverted timing signal φylB when the pseudo static RAM is selected in the normal write or read mode. Uptake and hold. Also, based on these Y address signals, the complementary internal address signal A
Y11~ A Y18 to form. Complementary internal address signal A Y
11 to A Y18 are supplied to the Y predecoder PYD and the Y system redundancy circuit YRAC.

The Y-system redundant circuit YRAC compares the defective address assigned to each redundant data line with the complementary internal address signals A Y11 to A Y18 supplied via the Y address buffer YAB at the time of memory access. Collate. As a result, when all the bits of these addresses match, the corresponding redundant data line selection signal YR0
~ YR7 is selectively set to a high level. The redundant data line selection signals YR0 to YR7 are supplied to each Y decoder via the Y predecoder PYD.

The Y predecoder PYD sequentially combines the complementary internal address signals A Y11 to A Y18 by 2 bits to decode the complementary internal address signals A Y11 to A Y18.
Y120-AY123, AY340-AY343, AY
560 to AY563 and AY780 to AY783 are alternatively formed. These predecode signals are commonly supplied to each Y decoder via the corresponding signal lines.

In this embodiment, the predecode signals AY560 to AY563 and AY780 to AY7 are used.
The signal line for transmitting 83 to each Y decoder is shared as a signal line for transmitting the redundant data line selection signals YR0 to YR7. Therefore, the Y predecoder PY
D is the predecode signal AY56 according to the complementary internal control signal φ yr supplied from the Y system redundancy circuit YRAC.
0 to AY563 and AY780 to AY783 or redundant data line selection signals YR0 to YR7 are selectively transmitted to the signal lines.

As shown in FIG. 1, the pseudo static RAM further includes a substrate back bias voltage generating circuit VBBG which forms a substrate back bias voltage VBB having a negative potential based on the power source voltage of the circuit, and a power source of the circuit. And a voltage generation circuit HVC that forms an internal voltage HVC that is a potential that is approximately one half of the voltage. Further, the word line drive signal generation circuit φxG is provided which forms the word line drive signal φx based on the inversion timing signal CE3B supplied from the timing generation circuit TG.

In FIG. 2, this pseudo static type R
The AM includes eight memory arrays MARY0L and MARY0R to MARY3L and MARY3R which are substantially divided in the extension direction of the data lines. These memory arrays have corresponding sense amplifiers SA0L and SA.
0R to SA3L and SA3R and column switches CS0L and CS0R to CS3L and CS3R are arranged symmetrically with the corresponding Y address decoders YD0 to YD3 in between. Also, the sense amplifiers, column switches, and Y decoders corresponding to these memory arrays are arranged in the upper and lower parts across the corresponding X address decoders XD0L and XD0R to XD3L and XD3R, respectively, and correspond to the arrangement positions. (U) or (D). In the following description, in order to avoid complication, the symbol (U) or (D) is omitted unless it is necessary. Further, among the memory arrays, those arranged on the upper side of the X decoder are collectively called an upper side array, and those arranged on the lower side are called a lower side array.

By the way, the memory arrays MARY0L to M
In ARY3L and MARY0R to MARY3R, the designated word line is selectively set to the selected state,
It is selectively activated. In this embodiment, when the pseudo static RAM is set to the normal write or read mode or the auto refresh mode,
The above eight memory arrays are MARY0L and MARY
2L (or MARY0R and MARY2R) or M
ARY1L and MARY3L (or MARY1R and M
Two of them are simultaneously activated by a combination of ARY3R). At this time, in each memory array, the upper side array or the lower side array is the complementary internal address signal of the most significant bit.
In accordance with BX10, four data lines are simultaneously selected from the two memory arrays which are selectively activated and further activated, and the corresponding main amplifier MAL is selected.
L and MALR or MARL and MARR or write circuits DILL and DILR or DIRL and DIR
It is connected to the corresponding unit circuit of R. As a result, this pseudo-static RAM is a RAM having a so-called x8-bit configuration that simultaneously inputs / outputs 8-bit storage data.

On the other hand, when the pseudo static RAM is set to the self refresh mode, the eight memory arrays are simultaneously operated, although not particularly limited thereto. At this time, in each memory array, the upper side array or the lower side array is the complementary internal address signal B X of the most significant bit.
The refresh operation is simultaneously performed on a total of eight word lines selectively activated in these memory arrays in accordance with 10.
These refresh operations are autonomously and periodically executed at a cycle that is four times the normal refresh cycle, and the refresh address counter RFC is sequentially updated each time. As a result, the number of refresh operations per unit time in the self-refresh mode is substantially reduced to one quarter, and the average current consumption of the memory array is correspondingly reduced.

In FIG. 3, this pseudo static type R
The AM includes eight data input / output terminals IO0 to IO7 provided corresponding to 8-bit input or output data,
In addition, a data input buffer DIB and a data output buffer DOB each including eight unit circuits corresponding to these data input / output terminals are provided. Data input / output terminal IO0
.About.IO7 is coupled to the input terminal of the corresponding unit circuit of the data input buffer DIB, and is also coupled to the output terminal of the corresponding unit circuit of the data output buffer DOB. The data input buffer DIB is supplied with the timing signal φdic from the timing generation circuit TG, and the data output buffer DOB is supplied with the timing signal φdoc.

Here, the timing signal φdic is not particularly limited, but when the pseudo static RAM is selected in the normal write mode, the level of the input data supplied through the data input / output terminals IO0 to IO7. Is set to high level selectively.
Further, the timing signal φdoc is selectively set to the high level when the levels of the read signals of the eight selected memory cells are determined when the pseudo static RAM is selected in the normal read mode. To be done.

The output terminals of the lower four unit circuits of the data input buffer DIB are the write circuits DILL and DIR.
Are connected to the input terminals of the corresponding unit circuits of L,
The output terminals of the upper four unit circuits of the data input buffer DIB are respectively coupled to the input terminals of the corresponding unit circuits of the write circuits DILR and DIRR. Similarly, the input terminals of the lower four unit circuits of the data output buffer DOB are respectively coupled to the output terminals of the corresponding unit circuits of the main amplifiers MALL and MARL, and the input terminals of the upper four unit circuits of the data output buffer DOB are input. The terminals are respectively coupled to the output terminals of the corresponding unit circuits of the main amplifiers MALR and MARR. The timing signal φma0 is supplied from the timing generation circuit TG to the main amplifiers MALL and MALR, and the main amplifiers MALL and MLR are supplied.
The timing signal φma1 is supplied to the ARR.

The data input buffer DIB takes in the input data supplied through the data input / output terminals IO0 to IO7 according to the timing signal φdic when the pseudo static RAM is selected in the write operation cycle, Write circuit DILL or DI
Data is simultaneously written into eight memory cells which are brought into the selected state via the corresponding unit circuit of RR. Further, the data output buffer DOB fetches an 8-bit read signal amplified by the main amplifiers MALL to MARR according to the timing signal φdoc when the pseudo static RAM is selected in the read operation cycle, and outputs the corresponding data. It is sent to the outside through the input / output terminals IO0 to IO7. When the timing signal φdoc is at low level, the output of the data output buffer DOB is in a high impedance state.

3.1.2. Operation Cycle Table 1 shows a pseudo static type R to which the present invention is applied.
The operation cycle of AM is displayed. 5 to 11 are timing charts showing one embodiment of each operation cycle shown in Table 1. Based on these tables and figures, an outline of each operation cycle of the pseudo static RAM of this embodiment and its features will be described.

[0038]

[Table 1]

(1) Read cycle As shown in FIG. 5, the pseudo static RAM has the following structure.
A read cycle is performed on condition that the write enable signal WEB and the output enable signal OEB, that is, the refresh control signal RFSHB are both at the high level at the falling edge of the chip enable signal CEB. The output enable signal OEB is temporarily set to the low level at a predetermined timing that does not delay the output operation of the read data. An 11-bit X address signal and an 8-bit Y address signal are supplied to the address input terminals A0 to A10 and A11 to A18 in synchronization with the falling edge of the chip enable signal CEB. Also,
The data input / output terminals IO0 to IO7 are normally in a high-impedance state, and when a predetermined access time elapses, 8-bit read data output from eight memory cells that are simultaneously selected are transmitted. .

(2) Write cycle As shown in FIG. 6, the pseudo static RAM has the following structure.
At the falling edge of the chip enable signal CEB, the output enable signal OEB is set to the high level, and the write enable signal WEB is set to the chip enable signal C.
The write cycle is performed on the condition that it is set to the low level before the EB or is temporarily set to the low level at a predetermined timing after the chip enable signal CEB. Address input terminals A0-A10 and A11-A18
Are input with X and Y address signals, and 8-bit write data is supplied to the data input / output terminals IO0 to IO7 at a predetermined timing that does not delay the write operation.

(3) Read Modify Write Cycle This operation cycle is, so to speak, an operation cycle in which the above read cycle and write cycle are combined. In the pseudo static RAM, as shown in FIG. 7, the chip enable signal CEB is used. Output enable signal OEB and write enable signal WE at the falling edge
Since B is at a high level, the read cycle is started first. Then, after the read data of the specified address is transmitted from the data input / output terminals IO0 to IO7, the 8-bit data supplied from the data input / output terminals IO0 to IO7 at the time when the write enable signal WEB is temporarily set to the low level. Write data is written to the above address.

(4) Address refresh cycle As shown in FIG. 8, the pseudo static RAM has the following structure.
The address refresh cycle is executed on the condition that the write enable signal WEB and the output enable signal OEB are set to the high level at the falling edge of the chip enable signal CEB, and thereafter they are continuously fixed to the high level. Address input terminals A0 to A10
Is supplied with an 11-bit X address signal designating a word line to be refreshed in synchronization with the chip enable signal CEB.

In the pseudo static RAM, as in the above read cycle, two memory arrays are simultaneously selected, and one word line in each memory array, that is, two word lines in total are simultaneously selected. And
The stored data of a total of 2048 memory cells, which are 1024 each coupled to these word lines, are output to the corresponding complementary data lines all at once, and undergo refresh or rewrite by the corresponding unit amplifier circuit of each sense amplifier.

(5) Auto-refresh cycle As shown in FIG. 9, the pseudo static RAM has the following structure.
With the chip enable signal CEB fixed at the high level, the auto refresh cycle is executed on condition that the output enable signal OEB, that is, the refresh control signal RFSHB is temporarily set to the low level in a relatively short time. At this time, the refresh address for designating the word line to be refreshed is the refresh counter R incorporated in the pseudo static RAM.
Supplied from FC.

In the pseudo static RAM, a total of two word lines designated by the refresh counter RFC are simultaneously selected, and a total of 2048 corresponding memory cells are simultaneously refreshed. The refresh counter RFC is automatically updated at a time point after its output signal, that is, the refresh address is fetched in the X address buffer.

(6) Self-Refresh Cycle In the pseudo static RAM, as shown in FIG. 10, the output enable signal OEB, that is, the refresh control signal RFSHB is relatively long while the chip enable signal CEB is fixed at the high level. The self-refresh mode is set on condition that the low level is continuously maintained for a time.

In the pseudo static RAM, the refresh timer counter circuit SRC is activated and at the same time, one self refresh cycle in the self refresh mode is executed first. And then
When the refresh timer counter circuit SRC outputs a refresh start signal having a predetermined frequency, the self-refresh cycle is repeated at a corresponding cycle. At this time, the refresh address is sequentially designated by the refresh counter RFC.

By the way, in this self-refresh cycle, in the pseudo-static RAM, eight memory arrays are simultaneously activated, and a total of eight word lines are selected. As a result, the refresh operation is simultaneously performed on a total of 8192 memory cells coupled to these word lines, and the average operating current of the memory array is reduced.

(9) Test Cycle In the pseudo static RAM, as shown in FIG. 11, the output enable signal OEB, the write enable signal WEB or the chip enable signal CEB is set to a predetermined high voltage exceeding the power supply voltage of the circuit. Under the condition, the test cycles in the three test modes are selectively executed.

In the pseudo static RAM, one of the activation control signals is set to the high voltage to determine the type of the test mode and activate the corresponding test cycle. The specific contents of each test mode and the operation of the pseudo static RAM in each test cycle will be described in detail later.

3.1.3. Test Method This pseudo static RAM has three test modes, which are not particularly limited, but can be carried out through the external terminals after the product is completed, as shown in Table 2.

[0052]

[Table 2] ECRF: Extra Control Refresh RCC: Refresh Counter Check STIC: Self Timer Check

(1) ECRF test mode In the pseudo static RAM, as shown in FIG. 11A, the chip enable signal CEB is fixed to the high level and the output enable signal OEB exceeds the power supply voltage of the circuit. The test cycle in the ECRF test mode is carried out by using the high voltage. At this time,
A predetermined test control signal is supplied to the address input terminal A11 of the pseudo static RAM. That is, at the rising edge of the output enable signal OEB, the pseudo static RAM is set to the self refresh mode when the test control signal is at the high level, and is set to the auto refresh mode when it is at the low level.

In these self-refresh and auto-refresh modes, a pseudo static RAM
Is supplied with a refresh address via the address input terminals A0 to A10. Further, these refresh cycles are repeatedly executed by repeatedly changing the test control signal from the low level to the high level, and the refresh address supplied to the address input terminals A0 to A10 is updated every time the test control signal rises. It is captured.

As a result, the address dependency and the like in the refresh operation of the pseudo static RAM can be tested and confirmed, and the refresh cycle can be arbitrarily set by the test control signal.
It is possible to test and confirm the information retention characteristics and the like.

(2) RCC Test Mode In the pseudo static RAM, as shown in FIG. 11B, the chip enable signal CEB is fixed to the high level, the output enable signal OEB is set to the normal low level, and By setting the write enable signal WEB to a predetermined high voltage exceeding the power supply voltage of the circuit before and after the falling edge of the output enable signal OEB,
A test cycle in the RCC test mode is selectively performed. That is, when the write enable signal WEB is set to the high voltage after the falling edge of the output enable signal OEB, the pseudo static RAM is set to the self refresh mode and the output enable signal OEB is set.
When the high voltage is applied prior to the falling edge of, the auto refresh mode is set.

At this time, the address of the word line to be refreshed is specified by the refresh counter RFC, and at the falling edge of the test control signal supplied via the address input terminal A11, the refresh counter RFC is set. Will be updated. Further, in these refresh cycles, in the pseudo-static RAM, the word line is sequentially selected, and at the same time, the write operation to the memory cell of the specific column address is performed. As a result, it is possible to test and confirm the counting function of the refresh counter incorporated in the pseudo static RAM by sequentially reading and collating the data written in the specific address of each word line in a normal read cycle.

(3) STIC Test Mode In the pseudo static RAM, as shown in FIG. 11C, the chip enable signal CEB is set to a predetermined high voltage exceeding the power supply voltage of the circuit, and the output enable signal OEB is STI is set to a low level with a slight delay.
Perform a test cycle in the C test mode. At this time, the pseudo static RAM is set to the self refresh mode. The output signal of the refresh timer circuit TMR, that is, the inverted timing signal φ counted by the refresh timer counter circuit SRC.
clB is output via the data input / output terminal IO6,
The output signal of the refresh timer counter circuit SRC, that is, the inversion timing signal φsrfB that determines the refresh cycle in the self-refresh mode is output via the data input / output terminal IO7. As a result, the refresh cycle in the self-refresh mode can be tested and confirmed from the outside of the pseudo static RAM.

Thus, this pseudo-static RA
In M, the start control signals such as the chip enable signal CEB, the write enable signal WEB, and the output enable signal OEB are selectively set to a high voltage exceeding the power supply voltage of the circuit to determine the type of test mode. It is the start condition of the test cycle. As a result, the setting of the test mode and the activation of the test cycle are realized at the same time, and the test operation of the pseudo static RAM can be simplified.

By the way, the refresh timer counter circuit SRC incorporated in the pseudo static RAM is
An 8-bit binary counter is provided, and the fuse means provided corresponding to each bit is selectively cut to selectively set the initial count value, that is, the counter modulo. Therefore, although not used in the pseudo static RAM of this embodiment, a method shown in FIG. 50 can be considered as a method for effectively testing the characteristics of the refresh timer counter circuit SRC.

That is, in FIG. 50, the pseudo static RAM has, for example, address input terminals A0 to A7.
The initial count value of the refresh timer counter circuit SRC is supplied via. These counting initial values, that is, the inversion internal signal aiB, are the inversion timing signal φextB.
Is set to a low level, the bit is taken into the corresponding bit of the refresh timer counter circuit SRC, and thereby the initial count value of the refresh timer counter circuit SRC is set. As a result, the characteristics of the refresh timer circuit TMR and the refresh timer counter circuit SRC corresponding to the initial count value can be tested and confirmed, and the operation characteristics thereof can be tested and confirmed while switching the refresh cycle of the pseudo static RAM.

3.1.4. Address configuration and selection method As described above, the pseudo static RAM adopts the non-address multiplex method, the X address signal and the Y address.
A total of 19 address input terminals A0 to A18 for simultaneously inputting address signals are provided. In addition, a total of 16 memory arrays, each of which is paired and is substantially divided into upper and lower parts, are provided. Each memory array is selectively selected and divided into groups of four, as will be described later. group,
It includes a total of 256 word lines and a total of 1024 sets of complementary data lines which are selectively selected by four sets at a time. As a result, each memory array has an address space of substantially 262144, which is a so-called 256 kilobit, and a pseudo static RAM has a so-called 4 address space.
It has a storage capacity of megabits.

When the quasi-static RAM is selected in the normal operation mode, the 16 memory arrays are pair-selected so that substantially two memory arrays are simultaneously selected. Then, a total of eight memory cells, four in total, are simultaneously selected from the two memory arrays that are simultaneously activated, and are connected to the corresponding common I / O lines. These memory cells are further connected to the corresponding unit circuit of the data input buffer DIB or the data output buffer DOB via the corresponding write circuit or main amplifier.

[0064]

[Table 3]

In this pseudo static RAM,
The address signals input via the 19 address input terminals A0 to A18 are classified as shown in Table 3 and provided for corresponding uses, respectively, although not particularly limited thereto. That is, first, 11 bits input via the address input terminals A0 to A10 are used as the X address signal, and the lower 2 bits of the address signals A0 and A1 and the uppermost bit of the address signal A10 are sent to the timing generation circuit TG. Supplied. In the timing generation circuit TG, the memory array pair is selected by the address signals A0 and A1, and the upper side array or the lower side array is selected by the address signal A10. As a result, 16 memory arrays are selected, so to speak, one eighth, and two memory arrays are simultaneously activated. As described above, when the pseudo static RAM is in the self-refresh mode, the address signals A0 and A1 have no meaning, and the eight upper side or lower side arrays are simultaneously activated.

Next, the 6-bit address signals A4 to A9 are supplied to the X predecoder PXD, and 2 bits are supplied to each of them.
Bits are combined and decoded. as a result,
Corresponding predecode AX450 to AX453 to A
X890 to AX893 are alternatively set to the high level. These predecode signals are supplied to the X decoder and are used to selectively select the word line group of each memory array. Furthermore, a 2-bit address signal A
2 and A3 are supplied to the word line selection drive signal generation circuit PWD, and combined with the word line drive signal φx output from the word line drive signal generation circuit φXG, the word line selection drive signals X00, X01, X10, and X11
Is provided to form the alternative. As described above, the word line drive signal φx and the word line selection drive signal X0
0 to X11 are predetermined boost levels exceeding the power supply voltage of the circuit. As a result, one of the 256 word lines forming the two memory arrays specified by the address signals A0, A1 and A10 is selectively selected according to the 8-bit address signals A2 to A9. To be in a state.

Similarly, address input terminals A11 to A18
8-bit address signals A11 to A input via
Reference numeral 18 is a Y address signal, which is used for data line selection. That is, the address signals A11 to A18 are supplied to the Y predecoder PYD, and as shown in Table 3, A
11 and A12, A13 and A14, A15 and A16
And the combination of A17 and A18, each 2
Decoded bit by bit. As a result, the corresponding predecode signals AY120 to AY123 and AY340 to AY are generated.
343, AY560 to AY563 and AY780
AY783 is alternatively set to the high level.
These pre-decoded signals are further combined by the decoder tree of the Y-decoder, resulting in four sets each from two memory arrays that are activated, for a total of eight.
A set of complementary data lines is selected and connected to the corresponding common I / O line. As a result, eight memory cells are selected from so-called 4-megabit memory cells, and 8-bit storage data is input / output through the data input / output terminals IO0 to IO7.

3.1.5. Redundant Configuration Pseudo-static RAM is provided with a total of 16 memory arrays that are paired and are substantially divided into upper and lower parts, as described above. These memory arrays are not particularly limited, but four redundant words are included. Line and 32 sets of redundant complementary data lines, respectively. The redundant word line and the redundant complementary data line are selectively switched at the same time and in common with respect to the common defective element in the 16 memory arrays, and one or four of them are replaced with the corresponding defective word line or defective complementary data line, respectively. The groups are selectively brought into a selected state. Therefore, the pseudo static RAM corresponds to four X-system redundant circuits XR0 to XR3 which are commonly provided corresponding to redundant word lines of all memory arrays and four redundant complementary data lines. Eight Y-system redundant circuits YRAC0 to YRAC7 provided in common are provided.

Of these, the X system redundant circuits XR0 to XR3
Are 8-bit address signals A2 to A9 other than those used for array selection, that is, complementary internal address signals B X2.
~ B X9 and the defective address assigned to the corresponding redundant word line are compared and collated. As a result, when all the bits of both addresses match, the output signal, that is, the corresponding inverted redundant word line selection signals XR0B to XR3B are set to the low level. As described above, these inverted redundant word line selection signals are generated by the word line selection drive signal generation circuit PWD as well as the word line drive signal φx and the complementary internal address signal.
A redundant word line selection drive signal XR0U to XR3U or X, which is combined with B X10 and corresponds to the upper side array or the lower side array.
R0D to XR3D. These redundant word line selection drive signals are supplied to each X decoder and used for the redundant word line selection operation. Needless to say, when the redundant word line is selected, the operation of selecting the defective word line designated by the address signals A2 to A9 is stopped.

By the way, this pseudo static RAM
45, the X system redundant circuits XR0 to XR3 receive the 4-bit X address signal, that is, the complementary internal address signals B X4 to B X7 and are arranged on the upper side of the semiconductor substrate surface. Redundant circuits XR0U to XR3U,
The remaining 4-bit X address signals B X2 and B X3 and B X8 and B X9 are received and divided into X system redundant circuits XR0D to XR3D arranged on the lower side of the semiconductor substrate surface. These X-system redundancy circuits are redundant ROMs.
Complementary internal address signal B X2 including two fuse means serving as (read-only memory) and substantially corresponding to a defective address held by these fuse means.
Of four redundant address comparison circuits for determining that B X9 match, and a redundant address comparison circuit corresponding to the gate provided in series between the match detection node N9 or N10 and the ground potential of the circuit. A match detection circuit including a cascade MOSFET (metal oxide semiconductor field effect transistor, which is a generic term for an insulated gate field effect transistor in the present specification) that receives an output signal is included.

The coincidence detection nodes N9 and N10 are further coupled to corresponding input terminals of a 2-input NOR gate circuit which constitutes a substantial negative logical product circuit. As a result, the coincidence detection nodes N9 and N10 are both pulled out to the low level, and the output signal of each X-system redundant circuit, that is, the above-mentioned inverted redundant word line, is provided on condition that the output signal of the corresponding redundancy enable circuit XRE is at the high level. Selection signal XR0
B to XR3B are selectively set to low level.

As described above, the cascade MOSFETs forming the coincidence detection circuit of the redundant circuit are divided into a plurality of address input pads or address buffers which are arranged dispersedly on the upper side or the lower side of the semiconductor substrate surface, and each of them is divided. By logically combining output signals with a logic circuit,
The operation of the redundant circuit can be substantially speeded up, and the access time of the pseudo static RAM can be speeded up accordingly.

As shown in FIG. 44, the redundancy enable circuit XRE includes a fuse logic gate circuit including fuse means F1 and F2, respectively. These fuse logic gate circuits are P-channel MOSFET Q provided between the internal node N7 or N8 and the power supply voltage of the circuit.
The fuse means F1 corresponding to P16 or QP18 and the internal node N7 or N8 and the ground potential of the circuit.
Alternatively, an N-channel MOSF provided in series with F2
ETQN21 or QN22.

The MOSFETs QP16 and QN21 and QP18 and QN22 act as one CMOS inverter circuit provided that the corresponding fuse means is not blown. At this time, the internal nodes N7 and N8
Is set to the low level on condition that the inverted timing signal CE1B is set to the low level or the timing signal XDP is set to the high level. When the corresponding fuse means F1 or F2 is blown by, for example, a laser beam or the like, the levels of the internal nodes N7 and N8 become the above-mentioned inverted timing signal CE1B and timing signal XD.
It is fixed at the high level regardless of P.

The output signals of the fuse logic gate circuits, that is, the levels of the internal nodes N7 and N8 are unchanged or inverted, and then the NAND gate circuits NAG7 to NAG9.
Is supplied to the exclusive OR circuit. The output signal of the NAND gate circuit NAG9 is the redundancy enable circuit XRE.
Output signal XRE. For these reasons, the output signal XRE of the redundancy enable circuit XRE is set to the low level regardless of the cut state of the corresponding fuse means when the inversion timing signal CE1B is set to the high level and the timing signal XDP is set to the low level. Further, when the inversion timing signal CE1B is set to the low level or the timing signal XRE is set to the high level, it is selectively set to the high level on condition that either the corresponding fuse means F1 or F2 is cut. At this time,
When both the fuse means F1 and F2 are cut or both are not cut, the output signal XRE of the redundancy enable circuit XRE is kept at the low level.

As described above, the fuse circuit included in the redundancy enable circuit XRE or the like is basically a so-called fuse logic gate circuit in which fuse means is provided between the N-channel or P-channel MOSFET of the CMOS logic gate circuit and the output node. With this configuration, the configuration of the fuse circuit can be simplified and the cost can be reduced. Further, two fuse logic gate circuits are provided in the fuse circuit, and the output signals of these fuse logic gate circuits are subjected to an exclusive OR operation to make an equivalent X-system redundant circuit to which a defective address is once assigned. The original initial state can be restored. As a result, it is possible to give flexibility to the redundant allocation of the pseudo-static RAM and increase the yield thereof.

The fuse circuit can be used for each redundant address comparison circuit of the X system redundant circuit and the Y system redundant circuit, and the refresh timer counter circuit S to be described later.
It can also be used for various fuse circuits such as RC preset fuse circuits.

[0078] Next, Y-based redundancy circuit YRAC0~YRAC3 pseudo static RAM is an 8-bit address signal A11~A18 i.e. complementary internal address signal A Y
11 to A Y18 are compared with the defective addresses assigned to the corresponding four sets of redundant complementary data lines. As a result, when both the addresses match in all bits, the output signal, that is, the corresponding redundant data line selection signals YR0 to YR7 are selectively set to the high level. As described above, these redundant data line selection signals are transmitted to each Y decoder via the Y predecoder PYD and used for the redundant complementary data line selection operation. Needless to say, when the redundant complementary data line is selected, the operation of selecting the defective complementary data line designated by the address signals A11 to A18 is stopped.

By the way, the redundant data line selection signals YR0 to YR7 supplied to the Y decoder YD via the Y predecoder PYD are the predecode signals AY560 to AY563 and AY780 to AY as shown in FIG.
8 signal lines for supplying 783 are shared and transmitted. Therefore, the Y predecoder PYD has the predecode signals AY560 to AY563 and AY780 to AY in accordance with the inversion timing signal φyrB which is brought to the low level when any of the redundant complementary data lines is selected.
Y783 or redundant data line selection signals YR0 to YR7
A multiplexer for selectively transmitting is provided. When the inversion timing signal φyrB is at a high level, the Y decoder YD outputs the signals transmitted via the signal lines to the predecode signals AY560 to AY563 and AY78.
0 to AY783, and inverted timing signal φ
When yrB is at a low level, it receives as redundant data line selection signals YR0 to YR7. As a result, the layout around the array where the signal lines are relatively crowded can be made more efficient, and the layout required area can be reduced.

On the other hand, as described above, 32 sets of redundant complementary data lines provided in each memory array are simultaneously brought into a selected state by 4 sets respectively, and substantially form eight redundant data line groups RY0 to RY7. . Pseudo static RA
M is paired as an array of upper and lower sides 16
The memory cell array includes a plurality of memory arrays, and the redundant data line group is switched to defective elements common to these memory arrays at the same time. Therefore, in the pseudo static RAM of this embodiment, the redundant complementary data line groups RY0 to RY7 of the two memory arrays forming a pair are lined up with the center line of the semiconductor substrate surface as an axis, as illustrated in FIG. Arranged in a symmetrical order.

As is well known, the failure occurrence rate of each element becomes higher as the arrangement position becomes closer to each side of the semiconductor substrate surface. By arranging the redundant complementary data line groups RY0 to RY7 in such a line-symmetrical order, the failure occurrence rate on the redundant complementary data line group RY0 side is intentionally increased, and conversely, the other redundant complementary data line groups are arranged. The incidence of disability in the group is reduced. As a result, the average failure occurrence rate of the entire redundant complementary data line is suppressed, and the yield of the pseudo static RAM is increased.

The redundant complementary data line layout method as described above can obtain the same effect when it is adopted for the redundant word line.

3.1.6. Refresh Method This pseudo static RAM has three kinds of refresh modes, namely, address refresh, auto refresh and self refresh modes, as described above. The refresh address for designating the word line to be refreshed is supplied from, for example, an externally provided memory control unit in the address refresh mode, and from the built-in refresh counter RFC in the case of auto refresh and self refresh. .

On the other hand, the cycle for performing the refresh operation, that is, the refresh cycle is set by the information holding capacity of the memory cell as described above, and is defined as the product specification. As is clear from the above description of the operation cycle, this refresh cycle is managed by an external memory control unit or the like that accesses the pseudo static RAM in the address refresh and auto refresh modes, and in the self refresh mode, it is simulated. It is managed by the refresh timer circuit TMR and the refresh timer counter circuit SRC included in the timing generation circuit TG of the static RAM.

The refresh timer circuit TMR is shown in FIG.
As shown in FIG. 5, it includes a ring oscillator in which seven inverter circuits whose operating currents are limited are substantially connected in series in a ring shape, and an output signal thereof, that is, a timing signal φtmr is formed in a predetermined cycle. . As shown in FIG. 14, the timing signal φtmr is passed through a 2-input NOR gate circuit and an inverter circuit to be a timing signal φcl, and the refresh timer counter circuit S
It serves as an RC counting pulse.

Refresh timer counter circuit SRC
Has an 8-bit binary counter structure, and the unit circuit corresponding to each bit has a pair of master latches and slave latches, and its initial value is a logical "0" or a logical "1", as shown in FIG. Includes a fuse circuit for selectively setting "". In the refresh timer counter circuit SRC, the initial count value is set by selectively disconnecting the fuse means of each unit circuit, and thereby the count cycle, that is, the counter modulo is set. The output signal of the refresh timer counter circuit SRC, that is, the output carry signal SCA7, is combined with the timing signal φcl, and is further used to form the inversion timing signal φsrfB that determines the refresh cycle of the self-refresh mode.

When the pseudo static RAM is set to the STIC test mode, the timing signal φcl and the inverted timing signal φsrfB are the same as the data input / output terminal IO6 or IO7 as described in the section of the test method.
Be monitored via.

By the way, the self-refresh mode of the pseudo static RAM is used when the pseudo static RAM is kept in the non-selected state for a relatively long time, for example, during battery backup as in this embodiment. There are a PS (pseudo) refresh mode and, for example, a VS (virtual) refresh mode which is intermittently performed between memory accesses. As is well known, the refresh cycle of the VS refresh mode that is performed between the activation of the pseudo static RAM and the refresh cycle of the PS refresh mode that is performed when the pseudo static RAM is almost inactive is compared with the refresh cycle. It gets shorter.

Therefore, as shown in FIGS. 51 and 52, by setting different refresh cycles in the VS and PS refresh modes, respectively, one common semiconductor substrate (base chip) can be used. It is possible to provide a pseudo static RAM applicable to both refresh modes. That is, in FIG.
The inverted timing signal φsrfB for activating the self-refresh cycle in the S refresh mode is formed by combining the carry signal SCAj + 2 of the most significant bit of the refresh timer counter circuit SRC and the output signal of the refresh timer circuit TMR, that is, the timing signal φcl. It The inverted timing signal φsrfB for activating the self-refresh cycle in the VS refresh mode is formed by combining the carry signal SCAj + 1 of the next bit of the refresh timer counter circuit SRC and the timing signal φcl. As a result, the cycle of the inversion timing signal φsrfB in the VS refresh mode is half that of the inversion timing signal φsrfB in the PS refresh mode, as shown in FIG.

3.1.7. Basic Layout FIG. 4 shows a pseudo static type R to which the present invention is applied.
A layout of one embodiment on the surface of the AM semiconductor substrate is shown. The basic layout of the pseudo static RAM of this embodiment will be described with reference to FIG. Note that, in FIG. 4, the semiconductor substrate is illustrated in a lateral direction due to space limitations, and therefore the left side of FIG. 4 is referred to as the upper side of the semiconductor substrate surface in the following description.

As described above, the pseudo static RAM
Are eight (substantially 16) memory arrays MARY0L to MARY3, each of which is divided into an upper side and a lower side.
L and MARY0R to MARY3R, and X address decoder X provided corresponding to these memory arrays
D0L to XD3L and XD0R to XD3R, and four Y address decoders YD0 to Y provided corresponding to two memory arrays and divided into upper and lower sides, respectively.
And D3.

In FIG. 4, X address decoders XD0L to XD3L and XD0 are provided at the center of the semiconductor substrate surface.
R to XD3R are arranged, and corresponding word line drive circuits WD0LU to WD3LU (WD0 are provided on the upper and lower sides thereof.
LD to WD3LD) and WD0RU to WD3RU
(WD0RD to WD3RD) are arranged. Then, the memory arrays MARY0L to MARY3L and MARY0R to MA are arranged so as to sandwich these X-system selection circuits.
The RY3Rs are arranged in a so-called vertical type so as to sandwich the corresponding Y decoders YD0 to YD3 and extend their word lines in the vertical direction. Although not shown, the corresponding sense amplifiers SA0L to SA3L and SA0R to SA3R and the column switches CS0L to CS3L and CS0R to CS are provided close to the Y address decoders YD0 to YD3.
3Rs are arranged respectively.

Memory arrays MARY0L to MARY3L
A pre-Y address decoder PYD, a Y address redundancy control circuit YRAC, etc. are arranged above MARY0R to MARY3R. Further, below the memory arrays, main amplifiers MALL to MARR, write circuits DILL to DIRR, etc. are arranged.

Bonding pads are arranged on each side of the semiconductor substrate surface so as to avoid a position close to each corner of the semiconductor substrate surface and a position close to the center of the left and right side sides. In addition, corresponding unit circuits of the X address buffer XAB and the Y address buffer YAB, and the data input buffer DIB and the data output buffer DOB are arranged close to these pads.

3.2. Specific Structure and Layout of Each Part and Operation and Characteristics thereof FIG. 12 to FIG. 38 are circuit diagrams of one embodiment of each part of the pseudo static RAM to which the present invention is applied. Further, FIGS. 39 to 41 show signal waveform diagrams of one embodiment of the pseudo static RAM. With reference to the circuit diagrams of FIGS. 12 and 38, the specific configuration and layout of each part of the pseudo static RAM of this embodiment, and the operation and characteristics thereof will be described. FIG.
Please refer to the signal waveform diagrams of FIGS. 9 to 41 as necessary.

3.2.1. Memory Array and Direct Peripheral Circuit As described above, the pseudo-static RAM of this embodiment has a total of 16 memory arrays MAR each forming a pair.
Y0L to MARY3L and MARY0R to MARY3R
Is provided. The two memory arrays forming a pair are symmetrically arranged with respect to the X-system selection circuit arranged at the center of the semiconductor substrate surface, and the corresponding four sets of common I / O lines and the pair of common sources are arranged. Lines are placed through the memory arrays in a skewered manner.

(1) Memory array Memory arrays MARY0L to MARY3L and MARY
As illustrated in FIG. 38, the upper and lower arrays of 0R to MARY3R have 256 word lines W0 to W255 and four redundant word lines RW0 to RW3 not shown arranged in parallel in the vertical direction of the drawing. And 1024 sets of complementary data lines D 0 to
D 1023 and 32 sets of redundant complementary data lines R D0 to R D31 (not shown) are provided. At the intersection of these word lines and complementary data lines, a dynamic memory cell composed of an information storage capacitor and an address selection MOSFET is coupled with a predetermined regularity.

One of the word lines constituting each memory array has a corresponding X decoder XD0L to XD3.
L or XD0R to XD3R are coupled to each other, and the selected state is selected. In the other side, it is coupled to the ground potential of the circuit through an N-channel MOSFET which receives an inverted signal of the word line clear signals WC0U to WC3U corresponding to the gate. These word line clear signals are normally at low level, and the pseudo static RAM
Is selected, it is selectively set to a high level in accordance with 3-bit complementary internal address signals B X2, B X3 and B X10. As a result, the word line of each memory array is normally in a low-level clear state, and when the pseudo static RAM is in the selected state, at least the corresponding word line is in the selected state,
It is selectively released from its clear state.

On the other hand, the complementary data lines forming each memory array are not particularly limited, but as shown in FIG. 38, the corresponding sense amplifiers SA0L to SA3L to S3.
Unit precharge circuit UP corresponding to A0R to SA3R
Corresponding unit amplifier circuit US via C0-UPC3 etc.
Column switch C connected to A0-USA3, etc.
Four sets of common I / O lines via corresponding switch MOSFETs of S0L to CS3L to CS0R to CS3R
I O00L to I O03L to I O34L to I O37L
Alternatively, I O00R to I O03R to I O34R to I
Four sets are selectively connected to O37R.

(2) Sense Amplifier and Data Line Precharge Circuit Sense Amplifiers SA0L to SA3L to SA0R to SA
3R is not particularly limited, but the sense amplifier S of FIG.
As represented by A0L, 1,056 unit precharge circuits UPC0 to UPC3 and the like and unit amplifier circuits USA0 to 0 provided respectively corresponding to the complementary data lines and the redundant complementary data lines of the corresponding memory array.
Including USA3 etc.

Of these, the unit precharge circuit UPC0
Up to UPC3 and the like respectively include three N-channel MOSFETs provided in series-parallel form between the non-inverted and inverted signal lines of the corresponding complementary data lines. These MOSFETs
Gates of the timing generator circuit T are commonly connected.
An inverted timing signal PC0ULB and the like are commonly supplied from G. Here, the inversion timing signal PC0ULB or the like is normally set to a high level, and the pseudo static RAM
Is selected, the complementary internal address signal B X0
And B X1 and B X10 are selectively set to the low level.

As a result, the three MOSFETs constituting each unit precharge circuit are normally turned on, and the non-inversion and inversion signal lines of the corresponding complementary data lines are short-circuited to halve the power supply voltage of the circuit. Is set to the half precharge level HVC. Pseudo static RAM is selected and inverted timing signal PC0UL
When B and the like are set to low level, the above three MOSFETs are
Is turned off, whereby the corresponding complementary data line is selectively released from its short-circuited state.

On the other hand, the unit amplifier circuit of each sense amplifier is
Although not particularly limited, as shown in FIG. 18, a basic structure is a latch in which two CMOS inverter circuits are cross-connected. The source of the P-channel MOSFET that constitutes each unit amplifier circuit is the common source line S
It is commonly coupled to P and further coupled to the power supply voltage of the circuit through four P-channel drive MOSFETs in parallel form. The gates of these drive MOSFETs are
Corresponding inversion timing signals P10ULB to P40ULB and the like are respectively supplied from the corresponding sense amplifier drive circuits SP0L to SP3L or SP0R to SP3R.
Similarly, an N channel MOS that constitutes each unit amplifier circuit
The sources of the FETs are commonly coupled to a common source line SN,
Furthermore, two N-channel drive MOs arranged in parallel
Coupled to the circuit ground potential through the SFET. The gates of these drive MOSFETs have corresponding sense amplifier drive circuits SN0L to SN3L or SN0R to SN3.
From R to the corresponding timing signals P10UL and P20
UL etc. are supplied respectively.

Each sense amplifier is not particularly limited,
Further, each of the common source lines SP and SN includes three N channels provided in a serial-parallel configuration. The gates of these MOSFETs are commonly connected to each other, and an inverted timing signal PC0B or the like is supplied. The inversion timing signal PC0B is the same as the inversion timing signal PC0UL.
It is set to a high level or a low level under substantially the same timing condition as B and the like. As a result, pseudo static RAM
Are in the non-selected state, the common source lines SP and SN
Are short-circuited to the half precharge level HVC. When the pseudo static RAM is selected, the precharge operation of the common source lines SP and SN is selectively stopped.

The unit amplifier circuit of each sense amplifier has a corresponding inversion timing signal P10ULB to P49ULB.
Etc. are set to low level, and the corresponding timing signals P10UL to P20UL etc. are set to high level, thereby selectively operating. In this operating state, each unit amplifier circuit amplifies a minute read signal output from the memory cell coupled to the selected word line of the corresponding memory array through the corresponding complementary data line, and outputs the high level or It is a low level binary read signal. These binary read signals are transmitted to the main amplifier via the corresponding common I / O line when the pseudo static RAM is in a normal read cycle, and the pseudo static RAM is in any refresh cycle. Then, the corresponding memory cell is rewritten.

By the way, in the pseudo static RAM of this embodiment, one layout is devised for the sense amplifier. That is, as illustrated in FIG. 43, a pair of Ps forming each unit amplifier circuit of the sense amplifier.
The source of each of the channel MOSFETs QP23 and QP24 or the N-channel MOSFETs QN25 and QN26 is formed by a common diffusion layer L, and the source S, drain D, and gate G of the source S form a right angle with the corresponding complementary data line. It is formed extending in the direction. The sources S of the MOSFETs of each pair formed by the common diffusion layer L are coupled to the common source line SP or SN formed of, for example, aluminum or an alloy thereof in the upper layer through the corresponding contacts. As shown in FIG. 43, the diffusion layer L is extended as it is, so that a pair of adjacent MOSFETs is
Are commonly combined with a similar source S. As a result, compared with a conventional pseudo-static RAM in which the diffusion layer L is not extended, the occurrence rate of a failure in which the characteristics of the unit amplifier circuit are deteriorated due to, for example, a contact failure, is reduced, and the product yield of the pseudo-static RAM is reduced. Is increased.

As shown in FIG. 22, the sense amplifier drive circuits SP and SN have the timing signals P1 to P4 and P1a to P1c supplied from the timing generation circuit TG.
Alternatively, based on P1D to P2D and P1Da to P1Dc and the internal address signals AX0U and AX1U or AX0U and AX1U and AX10, the inversion timing signals P10ULB to P40ULB and the like and timing signals P10UL and P20UL and the like are selectively formed.

(3) Column switch and common I / O line Column switches CS0L to CS3L and CS0R to
CS3R is a total of 1056 pairs of switch MOSFs provided for each complementary data line of the corresponding memory array.
Including ET. One of these switch MOSFETs
Coupled to the corresponding complementary data lines through the unit circuit of the corresponding sense amplifier, the other of the corresponding four pairs of common I / O lines I O00L~ I O03L and I O00R~ I
O03R to I O34L to I O37L and I O34R
The ~ I O37R, which in turn commonly coupled alternately. The gates of the respective switch MOSFETs are commonly connected to each other in groups of four sets, and from the corresponding Y address decoders YD0 to YD3,
Corresponding data line selection signals YS0 and the like are supplied.

Each of the four pairs of switches MO constituting the column switches CS0L to CS3L and CS0R to CS3R.
The SFET is selectively and simultaneously turned on by the corresponding data line selection signal YS0 or the like being alternatively set to the high level. As a result, the designated four sets of complementary data lines of the corresponding memory array are associated with the corresponding four sets of common I.
/ O line I O00L to I O03L or I O00R to I O0
3R to I O34L to I O37L or I O34R to I
It is selectively connected to O37R.

[0110] Incidentally, in the pseudo static RAM in this embodiment, common I / O lines I O00L~ I O0
3L and I O00R~ I O03R to I O34L~ I
As described above, the O37L and I O34R to I O37R are arranged so as to penetrate the pair of memory arrays arranged on the upper side and the lower side of the semiconductor substrate surface so as to be skewered. At this time, the non-inverted and inverted signal lines of each common I / O line are arranged so as to intersect in the middle of the upper side array and the lower side array, as shown in FIG. Therefore, in the manufacturing process of the quasi-static RAM, for example, the photomask for forming the polysilicon layer to be the gate G of the switch MOSFET of the corresponding column switch is displaced with respect to the diffusion layer L to be its source and drain. Even when the above occurs, the change in the parasitic capacitance coupled to the non-inverted signal line IO and the inverted signal line IOB of the common I / O line is canceled by the upper side array and the lower side array. As a result, each common I
The level difference in the / O line is eliminated, and the read operation of the pseudo static RAM is stabilized.

Furthermore, these common I / O lines I O00
L to I O03L and I O00R to I O03R to I O
Although not shown in FIG. 38, 34L to I O37L and I O34R to I O37R are arranged in the middle of the corresponding upper side and lower side arrays and at three positions outside each of them when the pseudo static RAM is deselected. The non-inverted and inverted signal lines are short-circuited and subjected to so-called equalization processing to set the half precharge level HVC. Then, the pseudo static RAM is set to the selected state, and the corresponding memory array is set to the selected state.
The equalizing process is selectively stopped. as a result,
Since the equalization processing of the common I / O line is performed reliably and at high speed, the signal transmission delay time of the common I / O line is correspondingly reduced, and the speed of the pseudo static RAM is increased.

3.2.2. X System Selection Circuit (1) X Address Buffer The X address buffer XAB includes eleven unit circuits provided corresponding to the address input terminals A0 to A10, as shown in FIG. These unit circuits have corresponding address input terminals A0 to A0 according to the inverted timing signal φrefB supplied from the timing generation circuit TG.
X address signals X0 to X10 supplied via A10
Alternatively, it includes a multiplexer for selectively transmitting refresh address signals AR0 to AR10 supplied from refresh counter RFC, and a latch circuit for fetching and holding the address signal transmitted through this multiplexer in accordance with timing signal φxls.
The output signal of each latch circuit is further gate-controlled in accordance with the timing signal φxls and then becomes the corresponding complementary internal address signal B X0 to B X10.

(2) Refresh Counter The refresh counter RFC includes eleven counter unit circuits CNTR provided corresponding to the refresh address signals AR0 to AR10, as shown in FIG. As shown in FIG. 19, these counter unit circuits each include a master latch and a slave latch which are serially coupled in a ring shape. Then, the carry input terminal and the carry output terminal are sequentially coupled to each other, so that the carry input terminals and the carry output terminals are substantially coupled in series to form one binary counter, and the stepping operation according to the inverted count pulse CUPB is performed.

Here, the inverted count pulse CUPB is
Timing after the inversion timing signal φrefB is set to the low level by setting the pseudo static RAM to the auto refresh mode or the self refresh cycle and the inversion timing signal CE2B is set to the low level by setting the pseudo static RAM to the selected state It is temporarily set to low level until the signal P1 is set to high level. As a result, the refresh address signals AR0 to AR10 are the X address buffer X when the pseudo static RAM is initially selected.
After being taken into the corresponding unit circuit of AB, it is updated to the next step state.

(3) X Predecoder The X predecoder PXD, as shown in FIG. 18, is a 2-bit complementary internal address signal B X4 and B X 4, respectively.
5, a total of 12 decoder unit circuits for receiving B X6 and B X7 and B X8 and B X9 in a predetermined combination. The output signals of these decoder unit circuits are predecode signals AX450 to AX453, AX670 to A.
X673 and AX890 to AX893, each X
Supplied to the decoder.

The X predecoder PXD has complementary internal address signals B X0, B X1 and B X for array selection.
Based on 10, several decoder unit circuits for forming various array selection signals are included. Of these, the inverted array selection signals XDS0LB and XDS0RB to XDS
3LB and XDS3RB are X decoders XD0L and XDS
The array selection signals AXD0L and AX are provided to selectively activate the D0R to XD3L and XD3R.
D1L, AXD0R, and AXD1R are supplied to the array selection circuit, and are used for switching the common I / O line, for example.

(4) Array Selection Circuit The array selection circuit ASL, as shown in FIG.
Array selection signal AX supplied from the predecoder PXD
Inversion selection timing signals IOS0LB and IO for common I / O line equalization based on D0L, AXD1L and AXD0R, AXD1R and timing signal CE3D.
S2LB or IOS0RB and IOS2RB or I
OS1LB and IOS3LB or IOS1RB and IO
S3RB is selectively formed. An inversion for selectively connecting the common I / O line and the main amplifier based on the array selection signal and the timing signal CE3D and the timing signal φwe which is selectively set to the high level in the write system operation cycle. Array selection signal MAT0L
B and MAT2LB or MAT0RB and MAT2RB
Or MAT1LB and MAT3LB or MAT1R
B and MAT3RB are selectively formed. The array selection circuit ASL further adds the logic condition of the timing signal φiou which is temporarily set to the high level immediately before the main amplifier is put into the operating state, thereby timing signal IOU0L for presetting the common I / O line. And IOU2L or IOU0R and IOU2R or IO
U1L and IOU3L or IOU1R and IOU3R are selectively formed.

(5) X System Redundant Circuit The pseudo static RAM includes the four X system redundant circuits XR0 to XR3 provided corresponding to the redundant word lines RWL0 to RWL3 of the memory array as described above. As shown in FIG. 20, these X system redundant circuits include an X system redundant circuit XRU arranged on the upper side of the semiconductor substrate surface and an X system redundant circuit XRD and a redundancy enable circuit XRE arranged on the lower side, respectively. .

Of these, the redundancy enable circuit XRE is
As described above, it includes two fuse logic gate circuits whose output signals are exclusive ORed. Of the output signals XRE0 to XRE3 of these redundancy enable circuits, when the inverted timing signal CE1B is set to the low level or the timing signal XDP is set to the high level, only the fuse means included in one of the fuse logic gate circuits is cut off. On the condition that it is set to high level selectively. As a result, these output signals XRE0 to XRE3
Indicates that the defective address is written in the corresponding X-system redundant circuit and the corresponding redundant word line is in use.

On the other hand, the X system redundancy circuits XRU and XRD are
Four redundant address comparison circuits each including a pair of fuse means which are selectively blown when the corresponding bit of the defective address assigned to the corresponding redundant word line is set to logic "0" or logic "1" Have. These redundant address comparison circuits are selectively activated when the output signals XRE0 to XRE3 of the corresponding redundancy enable circuit XRE are set to the high level. At this time, each redundancy enable circuit has a corresponding complementary internal address signal.
The B X2, B X3 and B X8, B X9 or B X4 no <br/> and B X7, by selectively transmitting the condition that the corresponding fuse unit is not disconnected, functions as a kind of address comparator To do. The output signals of these redundant address comparison circuits are supplied to the gates of cascade MOSFETs provided in series between the corresponding coincidence detection nodes and the ground potential of the circuit as described above.

The pair of coincidence detection nodes of the X system redundant circuit are
Further, it is coupled to the input terminal of the corresponding NOR gate circuit. The output signal of this NOR gate circuit, after being inverted,
Corresponding inverted redundant word line selection signals XR0B to XR
3B.

Inverted redundant word line selection signals XR0B to XR
As described above, 3B is supplied to the redundant word line selection drive signal generation circuit PRWD and also to the corresponding input terminal of the 4-input NAND gate circuit, and the internal control signal X is supplied.
Used to form R. The internal control signal XR is selectively set to the high level when any of the redundant word line selection signals XR0 to XR3 is set to the low level, that is, when any of the redundant word lines is set to the selected state, for example, the word line. It serves to selectively stop the formation of the word line selection drive signals X00 to X11 in the selection drive signal generation circuit PWD.

On the other hand, the output signals XRE0 to XRE3 of the redundancy enable circuit XRE of each X-system redundancy circuit are also supplied to the corresponding input terminals of the 4-input NOR gate circuit and are used to form the internal control signal SIGX. . As shown in FIG. 35, the internal control signal SIGX is provided on the condition that the inverted internal control signal φeh4B is at a low level, in other words, on the condition that a predetermined high voltage is supplied to the address input terminal A4. , A so-called signature signal indicating that one of the redundant word lines is in use is output from the address input terminal A5.

The X system redundancy circuits XR0 to XR3 further include
When the inverted internal control signal FCKB is set to low level,
It has a so-called fuse check function for testing the half-breakage of fuse means provided in each redundant address comparison circuit.

(6) Word Line Drive Signal Generation Circuit The word line drive signal generation circuit φXG includes a boost capacitor CB for forming a boost level drive signal, as shown in FIG. When the pseudo static RAM is in a non-selected state, the boost capacitor CB has its right electrode at a high level like the power supply voltage of the circuit and its left electrode at a low level like the ground potential of the circuit. To be precharged. Then, when the pseudo static RAM is in the selected state, the electrode on the left side thereof is set to the high level at the timing when both the inversion timing signals CE2B and CE3B are set to the low level. As a result, the right electrode is pushed up to the boost level higher than the power supply voltage of the circuit, and the boost level word line drive signal φx is selectively formed.

The word line drive signal φx is supplied to the word line selection drive signal generation circuit PWD and the redundant word line selection drive signal generation circuit PRWD, and further the word line selection drive signals X00 to X11 or the redundant word line selection drive signals XR0 to XR0. It is selectively transmitted as XR3.

By the way, as described above, the number of memory arrays which are simultaneously activated by the memory access of the pseudo static RAM of this embodiment is two in the normal operation mode and eight in the self-refresh mode. It is said that Therefore, in these operation modes, the number of simultaneously selected word lines is different, the magnitude of the load capacitance with respect to the word line drive signal φx is different, and as a result, the boost level changes. Therefore, in this pseudo static RAM, the word line drive signal generation circuit φ
A level correction capacitor Cw selectively coupled between the output terminal of XG and the ground potential of the circuit when the pseudo static RAM is selected in the self refresh mode and the inversion timing signal φsrB is set to the low level.
Is provided. The capacitor Cw is designed to have a difference in the number of simultaneously selected word lines in the normal operation mode and the self-refresh mode, that is, an electrostatic capacity corresponding to the load capacity of six word lines.

(7) Word line selection drive signal generation circuit and redundant word line selection drive signal generation circuit As shown in FIG. 21, the word line selection drive signal generation circuit PWD includes a timing signal XDP and a group of upper side or lower side arrays. By selectively transmitting the word line drive signal φx according to the 3-bit complementary internal address signals B X2, B X3, and B X10 for selecting the inner word line, the boost level word line select drive signals X00U, X01
U, X10U or X11U or X00D, X01
Alternatively, D, X10D or X11D is formed. As described above, the word line selection drive signal generation circuit PWD has X
The system redundancy circuit supplies the internal control signal XR that is selectively set to the high level when the address supplied at the time of memory access matches the defective address assigned to any one of the redundant word lines. This internal control signal XR
Is set to a high level, the operation of the word line selection drive signal generation circuit PWD is substantially stopped and the word line selection drive signal is not formed.

On the other hand, the redundant word line selection drive signal generation circuit PRDW selectively transmits the word line drive signal φx in accordance with the inverted redundant word line selection signals XR0B to XR3B corresponding to the timing signal XDP, so that the boost level is increased. The redundant word line selection drive signals XR0 to XR3 are selectively formed. As described above, when the address supplied at the time of memory access matches the defective address assigned to any one of the redundant word lines and one of the inverted redundant word line selection signals XR0B to XR3B is set to the low level, it is paraphrased. Then, when the redundant word line selection drive signal generation circuit PRWD is substantially operated, the operation of the word line selection drive signal generation circuit PWD is substantially stopped.

(8) X Decoder X Decoders XD0L and XD0R to XD3L and X
The D3R includes 64 unit circuits provided corresponding to the respective word line groups of the corresponding memory array and another unit circuit provided corresponding to the four redundant word lines. As shown in FIG. 36, each of these unit circuits includes four word line driving MOSFETs provided corresponding to the four word lines forming each word line group. The source of the word line drive MOSFET is coupled to the corresponding word line, and the drain thereof is supplied with the corresponding word line selection drive signal X00 to X11 or redundant word line selection drive signal XR0 to XR3. The gate of the word line drive MOSFET has a corresponding cut MO
It is commonly coupled to the internal node N12, that is, the output terminal of the inverter circuit N9 via the SFET.

The input terminal of the inverter circuit N9 has its gates predecode signals AX450 to AX453, AX.
670-AX673 and AX890-AX893 are received in a predetermined combination, and are coupled to the output terminal of the inverter circuit N10 via three series MOSFETs that form a so-called decoder tree. This inverter circuit N
From the X predecoder PXD to the input terminal of 10,
Corresponding inversion array selection signal lines XDS0LB and XDS
0RB to XDS3LB and XDS3RB are provided. As a result, in the internal node N12, the corresponding inverted array selection signal XDS0LB or the like is set to the low level,
Further, when the predecode signals are simultaneously set to the high level in the corresponding combinations, the predecode signals are selectively set to the high level. As a result, the word line selection drive signals X00 to X11 which are alternatively set to the boost level are transmitted to one designated word line in the corresponding word line group, and this word line is selectively selected. To be in a state.

Although not shown in FIG. 36, when a defective address assigned to any redundant word line is designated, redundant word line selection drive signals XR0 to XR3 are selected.
Is transmitted to the corresponding redundant word lines WR0 to WR3 regardless of the predecode signal.

3.2.3. Y-system selection circuit (1) Y-address buffer The Y-address buffer XAB includes, as shown in FIG. 23, eight unit circuits provided corresponding to the address input terminals A11 to A18. These unit circuits convert the Y address signals Y11 to Y18 transmitted through the corresponding address input terminals into the inverted timing signal CE0.
B and φylsB are included and latch circuits for holding the latch circuits are included. The output signal of each latch circuit is gate-controlled in accordance with the inversion timing signal φyeB and then supplied to the Y predecoder PYD as complementary internal address signals A Y11 to A Y18.

(2) Y Predecoder The Y predecoder PYD, as shown in FIGS. 23 to 25, each has a 2-bit complementary internal address signal A.
Y11 and A Y12, A Y13 and A Y14, A Y15
And a total of 16 decoder unit circuits for receiving the non-inverted and inverted signals of A Y16 or A Y17 and A Y18 in a predetermined combination. The output signals of these decoder unit circuits are predecode signals AY120 to AY12.
3, AY340 to AY343, AY560 to AY563
Alternatively, it is supplied to each Y decoder as AY780 to AY783.

By the way, the predecode signals AY120-
AY123, AY340 to AY343, AY560 to A
Transmits Y563 and AY780-AY783 1
The six signal lines are arranged over a relatively long distance in a relatively small space along the Y decoders YD0 to YD3 arranged between two memory arrays forming a pair. Eight signal lines for transmitting the redundant word line selection signals YR0 to YR7 output from the Y-system redundant circuit YRAC to the respective Y decoders need to be arranged in these regions, but the layout margin is actually provided. There is no.

To deal with this, in the pseudo static RAM of this embodiment, as shown in FIGS. 24 and 25, the eight signal lines for transmitting the predecode signals AY560 to AY563 and AY780 to AY783 are provided. It is shared as a signal line for a redundant data line selection signal. That is, 8 corresponding to these predecode signals
The individual decoder unit circuits have the inverted timing signal φyrB.
Are provided as the gate control signals. Here, the inversion timing signal φyrB is selected when the Y address signals Y11 to Y18 supplied at the time of memory access and the defective address assigned to any one of the eight redundant data line groups match, as will be described later. Is set to low level. At this time, the multiplexer of each decoder unit circuit selects the corresponding redundant data line selection signal YR0 to YR7 and transmits it to each Y decoder. On the other hand, when these addresses do not match and the inversion timing signal φyrB is set to the high level, the multiplexer of each decoder unit circuit causes the corresponding predecode signals AY560 to AY563 and AY780 to AY780A.
Y783 is selected and transmitted to the Y decoder. As a result, by only adding one signal line for transmitting the gate control timing signal φyr to each Y decoder, eight signal lines are equivalently realized, and the chip area of the pseudo static RAM is reduced. be able to.

On the other hand, predecode signals AY120 to AY
123, AY340 to AY343, AY560 to AY5
63 and AY780 to AY783 are gated by a selection signal indicated by * symbol in FIGS. To be done. In this embodiment, the NAND gate circuit for performing the gate control and the three-stage inverter circuit are arranged in proximity to the corresponding Y decoders as shown in FIG. As a result, the delay time of the signal transmission circuit for the predecode signal is shortened.

(3) Y System Redundant Circuit As described above, the pseudo static RAM has 32 sets of redundant complementary data lines R D0 to R D31 for each memory array.
And eight Y-system redundant circuits YRAC0 to YRAC7 provided corresponding to four sets of these redundant complementary data lines, that is, each redundant data line group. As shown in FIG. 26, these X-system redundant circuits include one redundant enable circuit YRE and complementary internal address signals A Y11 to AY11.
It includes eight redundant address comparison circuits provided corresponding to each bit of AX18. The redundant enable circuit and the redundant address comparison circuit function in the same manner as the above-mentioned X-system redundant circuit, and selectively outputs the output signal thereof, that is, the redundant data line selection signals YR0 to YR7.

That is, the redundancy enable circuit YRE of each Y-system redundant circuit is selectively cut off when the corresponding Y-system redundant circuit is made valid, in other words, when the defective address is assigned to the corresponding redundant data line group. When the fuse means is cut, the output signals YRE0 to YRE7 are set to the high level. On the other hand, the eight redundant address comparison circuits of each Y-system redundant circuit are
The fuse circuit includes two fuse means which are selectively cut off when the corresponding bit of the defective address assigned to the corresponding redundant data line group is set to logic "0" or logic "1".
By cutting these fuse means, the corresponding bit of the defective address is stored. Then, the output signals YRE0 to YRE7 of the corresponding redundancy enable circuits are selectively operated under the condition that they are at a high level, and the defective address and the Y address signals Y11 to Y18 supplied at the time of memory access, that is, complementary internal addresses are supplied. signal
The corresponding bits of A Y11 to A Y18 are compared and collated. As a result, when both bits match, the output signal is selectively set to high level.

The output signal of the redundant address comparison circuit is
It is supplied to the gates of eight cascade MOSFETs provided in series between a predetermined detection node and the ground potential of the circuit. Then, on condition that the output signals of the eight redundant address comparison circuits are all at the high level,
In other words, the defective address held in each Y-system redundant circuit and the Y-address signal Y supplied at the time of memory access
The detection node is selectively set to a low level on condition that all bits of 11 to Y18 match. The level of the detection node is set to the redundant data line selection signals YR0 to YR7 and the inverted redundant data line selection signals YR0B to YR7B via the inverter circuit.

That is, the Y-system redundant circuits YRAC0 to YRA
C7 is corresponding with acting as a defective address ROM for holding a defective address to be assigned to redundant data line group, Y address signal Y11~Y18 i.e. complementary internal address signals A Y11～ supplied upon these defective address memory access It operates as a redundant address comparison circuit for comparing and collating A Y18 bit by bit.
Then, the corresponding defective address and complementary internal address signal
All bits of A Y11 to A Y18 match,
The output signal, that is, the redundant data line selection signals YR0 to YR
R7 is selectively set to high level, and the corresponding inverted redundant data line selection signals YR0B to YR7B are selectively set to low level.

The redundant data line selection signals YR0 to YR7 are
As described above, it is supplied to each Y decoder via the Y predecoder PYD. In addition, the inverted redundant data line selection signal Y
R0B to YR7B are supplied to the corresponding input terminals of the negative logical sum circuit having substantially eight inputs, and the inverted timing signal φyrB is supplied.
Are provided to form the. Needless to say, the inversion timing signal φyrB is selectively set to the low level when any of the redundant data line selection signals YR0 to YR7 is set to the low level, in other words, when any of the redundant data line groups is set to the selected state. To be done. The inverted timing signal φyrB is gate-controlled by the timing signal φyed, and then becomes the timing signal φyr.
Timing signal φyr and inverted timing signal φyrB
Is used as a multiplexer control signal for the Y predecoder PYD as described above, and
Of the complementary data line or redundant complementary data line selection operation.

On the other hand, the output signals YRE0 to YRE7 of the redundancy enable circuit YRE of each Y-system redundant circuit are not particularly limited, but are also supplied to the corresponding input terminals of the logical OR circuit of substantially eight inputs to output the internal control signal SIGY. Served to form. Needless to say, the internal control signal SIGY is
Output signal YRE of either redundancy enable circuit YRE
When 0 to YRE7 are set to the high level, in other words, when a defective address is assigned to any of the redundant data line groups, it is selectively set to the high level. The internal control signal SIGY is output from the address input terminal A5 as a so-called signature signal when a predetermined high voltage is supplied to the address input terminal A4, like the internal control signal SIGX described above.

The Y system redundancy circuits YRAC0 to YRAC7 are
Further, when the inverted internal control signal FCKB is set to low level, it has a so-called fuse check function for testing a half disconnection of the fuse means provided in each redundant address comparison circuit.

(4) Y Decoder Y decoders YD0 to YD3 are provided corresponding to four sets of complementary data lines of the corresponding pair of left and right memory arrays.
It includes 56 unit circuits and 8 unit circuits provided corresponding to four sets of redundant complementary data lines, that is, redundant data line groups. Of these, the unit circuits provided corresponding to the four sets of complementary data lines are, as illustrated in FIG. 37, the power supply voltage of the detection node and the circuit or the corresponding inverted Y decoder control signal YDSiUB or YDSiDB, that is, YDS0UB to YDS3UB. Or YDS0DB ~ Y
It includes a plurality of P-channel and N-channel MOSFETs provided in parallel or in series with the DS3DB. These MOSFETs have at their gates predecode signals AY120 to AY123 and AY340 to AY.
343, AY560 to AY563 and AY780
By supplying AY783 in a corresponding combination,
One NAND gate circuit is constructed.

Therefore, the detection node of each unit circuit is
The corresponding inverted Y decoder control signal is set to low level,
Further, it is selectively set to low level on condition that all of the corresponding predecode signals are set to high level.
As a result, the corresponding data line selection signals YS0 to YS25
5 is alternatively set to the high level, and the corresponding four sets of complementary data lines are selected. The predecode signal lines AY560 to AY563 and AY780 to AY are used.
When redundant data line selection signals YR0 to YR7 are transmitted via 783, predecode signals AY340 to AY3
All 43 are low level. Therefore, all the data line selection signals for selecting the normal complementary data lines are set to the low level.

On the other hand, the four unit circuits provided corresponding to each redundant data line group are not particularly limited, but as illustrated in FIG. 37, predecode signals AY560 to AY563 corresponding to timing signal φyr or AY780
To AY783, that is, redundant data line selection signals YR0 to YR
2 input NAND gate circuits for receiving 7 are respectively included. The output signals of these NAND gate circuits have the corresponding inverted Y
The decoder control signal is set to the low level, the timing signal φyr and the corresponding redundant data line selection signal YR are set.
When 0 to YR7 are set to the high level, they are selectively set to the low level. As a result, the corresponding redundant data line selection signals RYS0 to RYS7 are alternatively set to the high level, and the corresponding four sets of redundant complementary data lines are selected.

3.2.4. Data input / output circuit (1) Data input buffer The data input buffer DIB has a data input / output terminal IO0.
8 unit circuits provided corresponding to IO7. The input terminals of these unit circuits are coupled to corresponding data input / output terminals IO0-IO7 as shown in FIG. On the other hand, the output terminals of the first to fourth unit circuits corresponding to the data input / output terminals IO0 to IO3 of the data input buffer DIB are commonly coupled to the corresponding unit circuits of the adjacent write circuits DILL and DIRL, respectively.
The output terminals of the fifth to eighth unit circuits corresponding to the data input / output terminals IO4 to IO7 are commonly coupled to the input terminals of the corresponding unit circuits of DILR and DIRR, respectively.

Each unit circuit of the data input buffer DIB has a pseudo static type R as shown in FIG.
Inverted timing signal φd which is brought to a low level at a predetermined timing when AM is set to a write operation cycle
According to icB, corresponding data input / output terminals IO0-I
The write data supplied via O7 is fetched and transmitted to the corresponding unit circuit of the corresponding write circuits DILL and DIRL or DILR and DIRR.

(2) Write Circuit and Write Select Circuit The write circuit DILL is, as illustrated in FIG.
Each of the two memory arrays MARY0L and MARY0R is provided with four unit circuits commonly provided corresponding to each common I / O line. These unit circuits have complementary write signals D IijA based on the write signals transmitted from the first to fourth unit circuits of the data input buffer DIB.
That is, D I00A to D I03A are formed, respectively.
These complementary write signals are, as shown in FIG. 30, provided that the corresponding write select signal WS0L or WS0R is set to the high level, to the write select circuit W.
Memory array MARY0L or M selected by S
It is transmitted to the four sets of common I / O lines of ARY0R.

Similarly, the write circuit DIRL includes common I / Os for the memory arrays MARY1L and MARY1R.
Each of the four unit circuits commonly provided corresponding to the line is provided. These unit circuits consist of the data input buffer D
Complementary write signals D I10B to D I13B based on the write signals transmitted from the first to fourth unit circuits of the IB.
Are formed respectively. These complementary write signals are supplied to the memory array MARY0L provided that the corresponding write selection signal WS1L or WS1R is set to the high level.
Alternatively, it is selectively transmitted to the four sets of common I / O lines of MARY0R.

On the other hand, the write circuit DILR includes four unit circuits commonly provided corresponding to the common I / O lines of the memory arrays MARY2L and MARY2R, respectively. These unit circuits are the data input buffer DI
Complementary write signals D I24A to D I27A are formed based on the write signals transmitted from the fifth to eighth unit circuits B. These complementary write signals are selectively transmitted to the four sets of common I / O lines of the memory array MARY2L or MARY2R on condition that the corresponding write selection signal WS2L or WS2R is set to the high level.

Similarly, the write circuit DIRR includes common I / Os of the memory arrays MARY3L and MARY3R.
Each of the four unit circuits commonly provided corresponding to the line is provided. These unit circuits consist of the data input buffer D
Complementary write signals D I34B to D I37B based on the write signals transmitted from the fifth to eighth unit circuits of the IB.
Are formed respectively. These complementary write signals are supplied to the memory array MARY3L provided that the corresponding write select signal WS3L or WS3R is set to the high level.
Alternatively, it is selectively transmitted to the four sets of common I / O lines of MARY3R.

(3) Main Amplifier The main amplifier MALL, as illustrated in FIG.
It includes four unit circuits provided corresponding to the common I / O lines of the memory arrays MARY0L and MARY0R.
These unit circuits each have two sets of input terminals and one set of output terminals. Of these, one of the input terminals of each unit circuit is connected to the corresponding common I of the memory array MARY0L.
/ O line I O0iL, that is, I O00L to I O03L, and the other one is connected to the memory array MARY0.
Common I / O line I O0iR corresponding to R, that is, I O0
It is coupled to 0R~ I O03R. The input terminal of each unit circuit has a corresponding inverted array selection signal MAT0LB.
Alternatively, when MAT0RB is set to the low level, the complementary internal node I MA0i of the corresponding unit circuit, that is, I MA
00 to I MA03 are selectively bound. The output terminal of each unit circuit of the main amplifier MALL is an output selection circuit OS.
Via L, it is coupled to the input terminals of the first to fourth unit circuits of the data output buffer DOB. Main amplifier MALL
Includes two pairs of static type amplifier circuits provided substantially in series between the complementary internal node I MA0i and its output terminal, and is selectively activated according to the corresponding timing signal φma0.

Similarly, the main amplifier MARL is a common I / O for each of the memory arrays MARY1L and MARY1R.
It includes four unit circuits provided corresponding to the lines. The four pairs of input terminals of these unit circuits are connected to the memory array MARY.
Corresponding common I / O line I O1 of 1L or MARY 1R
coupled to iL or I O1iR, and an output terminal, via the output selection circuit OSL, it is commonly coupled to the input terminal of the first to fourth unit circuit of the data output buffer DOB. The main amplifier MARL has a corresponding timing signal φma.
1 is selectively activated.

On the other hand, the main amplifier MALR includes four unit circuits provided corresponding to the common I / O lines of the memory arrays MARY2L and MARY2R. The four pairs of input terminals of these unit circuits are connected to the memory array MARY2.
Common I / O line I O2j corresponding to L or MARY2R
L, that is, I O24L to I O27L or I O2jR
That respectively coupled to I O24R~ I O27R,
The output terminals thereof are respectively coupled to the input terminals of the fifth to eighth unit circuits of the data output buffer DOB via the output selection circuit OSL. The main amplifier MARL is
It is selectively activated according to the corresponding timing signal φma0.

Similarly, the main amplifier MARR is a common I / O for each of the memory arrays MARY3L and MARY3R.
It includes four unit circuits provided corresponding to the lines. The four pairs of input terminals of these unit circuits are connected to the memory array MARY.
3L or MARY3R corresponding common I / O lines I O3
They are respectively coupled to jL or I O3jR, an output terminal, each of which is commonly coupled to the input terminal of the fifth through the unit circuit of the eighth of the data output buffer DOB through the output selection circuit OSL. The main amplifier MARL is selectively activated according to the corresponding timing signal φma0. Hereinafter, the main amplifier of the pseudo static RAM will be outlined and its characteristics will be described by taking the main amplifier MALL as an example.

The unit circuit of each main amplifier has a corresponding 2
Three equalize MOs provided between non-inverted and inverted signal lines such as a pair of common I / O lines I O0iL and I O0iR
Each includes an SFET. These equalize MOSF
ET is the corresponding internal control signal IOS0L or IOS0
When R or the like is set to a low level, it is selectively turned on, and the corresponding non-inverted and inverted signal lines of the common I / O line are set to the half precharge level HVC.

The unit circuit of each main amplifier further has a corresponding common I / O line I O as shown in FIG.
0iL or the like non-inverted signal line IO 0iL or the like and inverted signal line I
Each includes a pair of preset MOSFETs QN23 and QN24 provided between O0iLB and the like and the power supply voltage of the circuit. These preset MOSFETs are selectively turned on when the corresponding internal control signal IOU0L or the like is set to a high level, and the corresponding common I / Os are set.
The non-inverted and inverted signal lines of the line are preset to a level lower than the circuit power supply voltage by the threshold voltage thereof. As a result, the DC levels of the non-inverted and inverted signal lines of each common I / O line have a predetermined bias voltage that maximizes the sensitivity of the static amplifier circuit.

By the way, this pseudo static RAM
In FIG. 48, the internal control signals IOU0L and the like supplied to the preset MOSFET are as shown in FIG.
Immediately before the operation of each main amplifier, in other words, immediately before the timing signal φma0 or the like is set to the high level, it is temporarily set to the high level, whereby the preset MOSFETs QN23 and QN24 and the like are temporarily turned on. . Therefore, these presets M
The power consumption of the main amplifier can be reduced as compared with the conventional dynamic RAM or the like in which the OSFET is continuously turned on while the main amplifier is in the operating state.

(4) Output Selection Circuit As shown in FIG. 32, the output selection circuit OSL outputs the 4-bit read data output from the main amplifiers MALL, MARL, MALR and MARR in accordance with the timing signals φma0 and φma1. It is selected and selectively transmitted to the corresponding unit circuit of the data output buffer DOB.

That is, the output selection circuit OSL outputs the read data output from each unit circuit of the main amplifier MALL to the first to fourth unit circuits DO0 of the data output buffer DOB when the timing signal φma0 is at the high level. To DO3, and the main amplifier MAL
The read data output from each R unit circuit is used as the fifth to eighth unit circuits DO4 to D of the data output buffer DOB.
Transmit to O7 respectively. Also, the timing signal φma
When 1 is set to the high level, the read data output from each unit circuit of the main amplifier MARL is transferred to the first to fourth unit circuits DO0 to DO3 of the data output buffer DOB.
Read data output from each unit circuit of the main amplifier MARR to the data output buffer D.
It is transmitted to the fifth to eighth unit circuits DO4 to DO7 of the OB, respectively.

(5) Data output buffer The data output buffer DOB has the data input / output terminal IO0.
~ 8 unit circuits DO0 provided corresponding to IO7
It is equipped with DO7. As shown in FIG. 31, these unit circuits are provided between a latch circuit in which the input terminals and output terminals of a pair of NAND gate circuits are cross-connected, and the timing provided between the non-inverting and inverting input terminals of the latch circuit. A pair of precharge MOSFETs that are selectively turned on in accordance with the signal φmad, and an inverted signal of the complementary output signal of the latch circuit are inverted timing signals φ for output control.
It includes a pair of CMOS NAND gate circuits that selectively transmit according to docB, and a pair of N-channel output MOSFETs that receive an inverted signal of the output signal of the NAND gate circuit through corresponding resistors. The complementary input terminals of the latch circuit are provided with two pairs of MOs which are selectively turned on in accordance with the timing signal φma0 or φma1.
A complementary internal output signal of the corresponding main amplifier, that is, read data is transmitted via the SFET. Also, the commonly connected nodes of the pair of output MOSFETs are
It is coupled to corresponding data input / output terminals IO0-IO7, respectively.

Each unit circuit of the data output buffer DOB is practically operated by setting the inversion timing signal φdocB to the low level, and outputs the read data transmitted from the corresponding main amplifier via the output selection circuit OSL. , From the corresponding data input / output terminals IO0 to IO7. When the inversion timing signal φdocB is set to the high level, the outputs of the respective unit circuits of the data output buffer DOB are all set to the high impedance state.

By the way, this pseudo static RAM
The data output buffer DOB is a pair of N-channel MOSs provided in series between the power supply voltage and the ground potential of the circuit, as shown in FIGS. 49 (a) and 49 (b).
Let FETQN3 and QN4 be output MOSFETs. Therefore, when high-level read data is sent from the corresponding unit circuit, the corresponding data input / output terminal IO
Output MOS as the level of 0 to IO7 increases
The gate-source voltage of the FET QN3 decreases, and the output operation is equivalently delayed.

To deal with this, in the pseudo static RAM of this embodiment, as shown in FIG. 49 (a), a NAND gate circuit NAG forming the above latch circuit.
The timing signal CE3D is input to the third input terminal of No. 2 to preset the latch circuit. That is, the timing signal CE3D is normally at a low level as shown in FIG. 49 (c), and when the pseudo static RAM is in a selected state, it is temporarily at a high level so as to include the inverted timing signal φdocB. To be done. Therefore, when the pseudo static RAM is in the non-selected state and the timing signal CE3D is at the low level, the latch circuit is preset to the logic "1", that is, the high level output state, and the timing signal CE is set.
When 3D is set to the high level, the latch state is set according to the read data. As a result, the data output buffer DOB once enters the high level output state regardless of the read data at the beginning of its output operation, and then performs the output operation according to the read data. As a result, the high level output operation of the data output buffer DOB is equivalently speeded up.

3.2.5. Timing Generation Circuit The timing generation circuit TG is not particularly limited, but CE
A system timing generation circuit CE, a WE system timing generation circuit WE, an OE system timing generation circuit OE, a word line clear circuit WC, and a precharge control circuit PC are provided. Of these, the OE timing generation circuit OE is
It also functions as an SH system, that is, a timing generation circuit for refresh control. Hereafter, this pseudo static type R
An outline of each part of the AM timing generation circuit TG and its features will be described.

(1) CE System Timing Generating Circuit CE system timing generating circuit CE includes an input circuit provided corresponding to pad CE to which chip enable signal CEB is input, as shown in FIG. The chip enable signal CEB input through this input circuit first becomes the inverted timing signal CE0B and is supplied to one input terminal of the 2-input NAND gate circuit. The other input terminal of the NAND gate circuit is supplied with the inversion timing signal φpceB, and the output signal thereof passes through a predetermined number of logic gate circuits, and a plurality of inversion timing signals CE1B, CE2 for advancing the operation of the pseudo static RAM.
B and CE3B are sequentially formed.

Here, the inversion timing signal φpceB
Is selectively set to a low level by setting any of the inversion timing signals φsrf′B, φsrfB, and φarfB to a low level, and the inversion timing signal CE4B
Is set to the low level and is returned to the high level. As will be described later, the inversion timing signal φsrf′B is temporarily set to the low level at the beginning of the pseudo static RAM, and the inversion timing signal φsrfB is set to the pseudo static RAM.
After being set to the self-refresh mode, it is temporarily set to the low level each time a predetermined refresh cycle elapses. Further, the inversion timing signal φarfB is temporarily set to the low level when the pseudo static RAM is initially set to the auto refresh mode.

As a result, the pseudo static RAM
The pseudo static RAM is brought into a selected state in response to the low level of the chip enable signal CEB, and the pseudo static RAM is initially refreshed or self refreshed, or the pseudo static RA.
Every time M is set to the self-refresh mode and a predetermined refresh cycle elapses, a series of operations controlled by the inversion timing signals CE1B to CE3B and the like are started.

Inversion timing signals CE1B and CE2B
Form timing signals φxls and φyls for fetching the X address signal and the Y address signal through a two-input NAND gate circuit that substantially constitutes a negative OR circuit and a predetermined number of inverter circuits. On the other hand, the inversion timing signal CE2B is inverted and then supplied to one input terminal of the 2-input NAND gate circuit. The inverted timing signal C is applied to the other input terminal of the NAND gate circuit.
The inverted delay signal of E3B is supplied, and its output signal is passed through a predetermined number of logic gate circuits and then the pseudo static RA
A plurality of timing signals P1, P2, P3, P4, etc. for controlling M sense amplifiers etc. are formed. These timing signals are inverted timing signals CE2B and C2.
When a predetermined delay time elapses after both E3B are set to the low level, they are sequentially changed to valid, that is, to the high level, and when the inversion timing signal CE2B is returned to the high level, they are invalid, that is, to the low level.

On the other hand, the inverted timing signal CE3B, after being inverted, is combined with the timing signal φxls, and further passes through a predetermined number of logic gate circuits to pass through a timing signal P1D for controlling the sense amplifier of the pseudo static RAM. And P2D and the like are sequentially formed. Also,
Inversion timing signal φsrB and inversion timing signal φ
refB is high level, that is, pseudo static type R
Inversion timing signal φy for activating the data input / output circuit, provided that AM is not in the refresh mode.
The eB, the timing signal φys, etc. are selectively formed.

Further, the timing signal P1 is selectively transmitted through a predetermined number of logic gate circuits under the condition that the inverted timing signal φsrB is at the high level, that is, the pseudo static RAM is in the self refresh mode, and the timing is changed. The signals P1A to P1C are sequentially formed.

These timing signals P1 to P4, P1D and P2D, and P1A to P1C are supplied to the sense amplifier drive circuits SP and SN, as described above, whereby a plurality of sense amplifier drive MOSFETs are supplied.
A timing signal for turning on the switch is formed under a predetermined condition.

(2) WE Timing Generator Circuit WE timing generator circuit WE includes an input circuit provided corresponding to pad WE to which write enable signal WEB is input, as shown in FIG. The write enable signal WEB input through this input circuit is first negatively ORed with the inversion timing signal φehwB and then forms the inversion timing signal φdicB. Also,
After being ANDed with the timing signal P1, the write control timing signals WE0 and WE2 and the inversion timing signals φwyB, φweB and φwesB are formed.

Here, the inversion timing signal φehwB
Indicates that when the inversion timing signals φrefB and φeh2B are both at the low level, that is, the pseudo static RAM is in the refresh mode and the pad WE
When a predetermined high voltage is supplied to the RAM, in other words, when the pseudo static RAM is in the RCC test mode described above, it is selectively set to the low level.

From these facts, the inversion timing signal φ
The dicB is selectively set to the low level when the pseudo static RAM receives the low level of the write enable signal WEB for the write operation cycle or the RCC test mode, and receives the low level. The 8-bit write data supplied via the data input / output terminals IO0 to IO7 is taken into the corresponding unit circuit of the data input buffer DIB. These write data are inverted timing signals φweB
And the like are set to the low level, the data is transmitted via the corresponding write circuit, and the data is simultaneously written to the selected eight memory cells.

(3) OE Timing Generation Circuit The OE timing generation circuit OE is not particularly limited, but as shown in FIG. 14, the output enable signal OE is used.
B, that is, an input circuit provided corresponding to the refresh control signal RFSHB. The output enable signal OEB input through this input circuit is the timing signal OE.
0 and further combined with the timing signal P2D, the inverted timing signal φdo for output control
Form cB. This inversion timing signal φdocB
Is supplied to the data output buffer DOB and is used for output control of read data as described above.

On the other hand, the timing signal OE0 is provided on condition that the inverted timing signal CE0B is at the high level.
That is, on the condition that the chip enable signal CEB is at the high level, it is transmitted through the latch circuit, and thereby the inversion timing signal RF0B is set to the low level. The inverted timing signal RF0B is sequentially transmitted through a predetermined delay circuit, and as a result, the timing signal R0B is first transmitted.
F1 is set to high level, and the inverted timing signal RF2B is set to low level with a slight delay.

The timing signal RF1 and the inverted timing signal RF2B are further added to the inverted timing signal CE0.
In combination with B, the inverted timing signal φar
Form fB. The inversion timing signal φarfB is temporarily set when the output enable signal OEB, that is, the refresh control signal RFSHB is set to the low level while the chip enable signal CEB is set to the high level, that is, when the pseudo static RAM is initially set to the auto refresh mode. It becomes a low level.

In the pseudo static RAM, the internal control signal E is received in response to the high level of the internal timing signal RF1.
NB is set to a high level and the refresh timer circuit T
MR is activated. As a result, the timing signal φtm
r, inversion timing signal φclB and timing signal φ
cl is formed in a predetermined cycle. Of these, the timing signal φcl is the refresh timer counter circuit SR.
The output signal, that is, the internal timing signal SCA7, counted by C is repeatedly set to a high level repeatedly in a cycle of a predetermined multiple of the inversion timing signal φclB.

On the other hand, the inversion timing signal RF2B is transmitted on condition that both the inversion timing signals CE1B and CE3B are at the high level, and when the inversion timing signal φclB is at the low level, the inversion timing signal φsrB is set to the low level. To do. This allows
The inversion timing signal φsrB is the inversion timing signal R
When F2B, that is, the output enable signal OEB is continuously set to the low level over the cycle of the inversion timing signal φclB, it is set to the low level and becomes an internal control signal for designating the self-refresh mode.

The inverted timing signal φsrB is gate-controlled in accordance with the timing signal φxls after the logical AND of the inverted signal of the inverted timing signal RF0B, that is, the non-inverted timing signal RF0 and the inverted timing signal RF2B is taken. It is transmitted to the latch circuit. As described above, the output signal of the latch circuit is the output signal of the refresh counter RFC in the X address buffer XAB, that is, the refresh address signals AR0 to AR1.
The inverted timing signal φrefB for taking in 0 is set. As a result, the inversion timing signal φrefB becomes
When the pseudo static RAM is set to the auto refresh or self refresh mode, it is set to the low level when the timing signal φxls is set to the high level.

The inverted timing signal φsrB further includes
It is also supplied to a one-shot circuit formed by combining a NAND gate circuit, an inverter circuit, and a predetermined delay circuit DL to form an inverted timing signal φsrf′B. The inversion timing signal φsrf′B is the inversion timing signal φ
srB is at a low level, that is, it is temporarily set to a low level at the beginning when the self-refresh mode of the pseudo static RAM is identified, and the inversion timing signal φpce is set.
This is one of the causes for making B low.

On the other hand, the timing signal φcl formed by the refresh timer circuit TMR in a predetermined cycle is
Output signal S of refresh timer counter circuit SRC
After being logically ANDed with CA7, the signal is selectively transmitted under the condition that the timing signal RF1 is at the high level, that is, the refresh control signal RFSHB is at the low level, and becomes the inverted timing signal φsrfB. Further, the logical product signal is the refresh timer counter circuit SR.
An internal control signal LOAD for presetting C is formed, and an internal control signal FSET for setting the fuse circuit is formed on condition that the inversion timing signal CE0B is at a high level. Inversion timing signal φ
srfB contributes to setting the inversion timing signal φpceB to the low level, like the above-described inversion timing signal φsrf′B.

(4) Refresh Timer Circuit The refresh timer circuit TMR includes, as shown in FIG. 15, seven inverter circuits and capacitors C1 which are substantially in series. As shown in FIG. 53A, four of these inverter circuits act as one delay circuit DL, and the inverted signal of the output signal thereof is a P-channel MOS circuit forming the leading inverter circuit.
By being fed back to the gate of the FET QP3, one ring oscillator is formed. The capacitor C1 is the above M
When the OSFET QP3 is turned on, it is charged, and when the MOSFET QP3 is turned off,
It is discharged through the N-channel MOSFET QN1. At this time, the discharge current flowing through the MOSFET QN1 is the N-channel MOSFET QN in a current mirror form with the MOSFET QN1.
2 is set by a constant current source.

The charge potential of the capacitor C1 is monitored by the subsequent inverter circuit including the N-channel MOSFET QN7. This inverter circuit functions as a so-called level determination circuit, and its logic threshold level is such that a P-channel MOSFET QP5 that constitutes this level determination circuit together with the MOSFET QN7 constitutes a P-channel MOSFET QP4 that constitutes the constant current source.
Since it is a current mirror type, it is almost MOSFET
It becomes the threshold voltage V _THN itself of QN7. Therefore, MOSFET QN7 is turned on when the charge potential of capacitor C1 is higher than the logic threshold level, and turned off when it is low. As a result, the seven inverter circuits function as one ring oscillator, and the oscillation frequency thereof is set by the magnitude of the discharge current flowing through the MOSFET QN1.

The constant current source including MOSFETs QP4 and QN2 further includes a resistor R1 provided between these MOSFETs. As shown in FIG. 53 (b), this resistor R1 has a silicon dioxide (S
Polycrystalline silicon (PolySi) is formed on the insulating layer formed of iO ₂ ) and a relatively large resistance value is required, so that it is formed over a relatively long distance. Therefore, a relatively large substrate capacitance is equivalently coupled between the polycrystalline silicon layer and the P-type semiconductor substrate, so that the characteristics of the refresh timer circuit TMR are affected by the power supply bumps and the like and fluctuate. Easier to do.

In order to deal with this, in this pseudo static RAM, as shown in FIG. 53 (b), the circuit of the circuit is formed under the portion corresponding to one half of the polycrystalline silicon layer forming the resistor R1. An N well region NW1 coupled to the power supply voltage is formed, and an N well region NW coupled to the ground potential of the circuit is formed under the portion corresponding to the remaining one half.
2 is formed. Substrate capacitances having substantially the same electrostatic capacitance are equivalently coupled between these well regions and the polycrystalline silicon layer forming the resistor R1, so that a steep fluctuation of the power source voltage due to the power source pad or the like is caused. Are offset. As a result, the characteristics of the refresh timer circuit TMR are stabilized, and the pseudo static RAM has a stable refresh cycle.

On the other hand, the refresh timer circuit TMR having the above circuit structure has another problem regarding the power supply bump. That is, as described above, the capacitor C1 is charged to a predetermined high level based on the power supply voltage of the circuit when the MOSFET QP3 is turned on, and the MOSFET QP3 is turned off so that M
It is discharged through the OSFET QN1. At this time, the value of the discharge current flowing through the MOSFET QN1 is set by the constant current source also with the power supply voltage of the circuit as a reference. Therefore, for example, MOSF
When a power supply bump or the like is generated in the power supply voltage of the circuit while the ETQP3 is in the off state, only the reference voltage for setting the discharge current fluctuates, which causes the characteristics of the refresh timer circuit TMR to fluctuate easily. .

To deal with this, for example, FIG.
As shown in (a), the MO that constitutes the constant current source.
N-channel MOS between SFETQP4 and resistor R1
FETQN15 is provided, and the gate potential is
When the FET QP3 is turned off, the capacitor C that is brought into a floating state like the above-mentioned capacitor C1.
A method of setting by 2 can be considered.

That is, one electrode of the capacitor C2, that is, the internal node N4 is connected to the P-channel MOSFET QP.
8 is turned on at the same time as the MOSFET QP3, so that the output voltage V1 of the constant voltage source including the P-channel MOSFETs QP9 to QP11 and the N-channel MOSFETs QN12 to QN14 is charged. The charge potential of the internal node N4 becomes a reference potential for setting the value of the discharge current by being supplied to the gate of the MOSFET QN15, and also the N-channel MOSFE.
By being supplied to the gate of TQN16, the capacitor C1
It also serves as a reference potential for setting the charge potential of. And
The charge potential of the capacitor C2 is MOSFET QP8.
Is turned off at the same time as the MOSFET QP3 to be in a floating state together with the MOSFET QP3, and is not affected by the power supply bump generated during this time. As a result, the characteristics of the refresh timer circuit TMR are stabilized, and the refresh cycle of the pseudo static RAM is further stabilized.

(5) Refresh Timer Counter Circuit As shown in FIG. 14, the refresh timer counter circuit SRC basically has an 8-bit binary counter in which eight unit counter circuits SCNTR are substantially connected in series. To do. These unit counter circuits SC
As illustrated in FIG. 16, the NTR includes a pair of master latches and slave latches, each of which is formed by connecting two CMOS inverter circuits in a cross connection and which are connected in series substantially in a ring shape. In addition, each unit counter circuit SCNTR includes a fuse circuit similar to that included in the above-described X-system redundancy circuit or the like in order to set the initial count value according to the internal control signal FSET. These unit counter circuits SCNTR carry out a stepwise operation according to the output signal of the refresh timer circuit TMR, that is, the timing signal φcl and the carry output signal SCAj-1 of the preceding unit counter circuit, and form the output signal, that is, the carry output signal SCAj. . It should be noted that, in the unit counter circuit SCNTR of the first bit, the timing signal RF1 is used instead of the carry output signal of the preceding circuit.
Is supplied as an activation control signal for the refresh timer counter circuit SRC.

Final bit unit counter circuit SCNTR
The carry output signal SCA7 of is the output signal of the refresh timer counter circuit SRC, and as described above,
Inverted timing signal φ that activates the self-refresh cycle when combined with timing signal φcl
Served to form srfB.

(6) Word line clearing circuit The word line clearing circuit WC, as shown in FIG.
Complementary internal address signals B X2, B X3 and B X10
Timing signal WC for word line clear control based on
0U to WC3U or WC0D to WC3D are selectively formed. These timing signals are normally set to low level, and when the complementary internal address signals are set to low level or high level in a corresponding combination, they are alternatively set to high level. As a result, the word line clear MOSFETs provided between all the word lines of each memory array and the ground potential of the circuit are selectively turned off, and the corresponding word lines are released from the clear state.

(7) Precharge Control Circuit The precharge control circuit PC has the inversion timing signal CE.
Based on 1B, CE3B, φsrB, etc., various control signals for precharging each part of the pseudo static RAM are formed. In addition, the internal address signal AX0
And AX1 are combined to invert the Y decoder control signal YDP for selectively setting the Y decoder in the operating state.
0B to YDP3B and the like are selectively formed.

3.2.6. Voltage Generation Circuit The pseudo static RAM includes a plurality of voltage generation circuits HVC, VBB and VL that form various internal voltages based on the power supply voltage VCC of the circuit set to + 5V, for example.

(1) HVC Voltage Generating Circuit As shown in FIG. 43, the voltage generating circuit HVC forms an internal voltage HVC which is a potential which is approximately one half of the voltage by lowering the power supply voltage VCC of the circuit. To do. This internal voltage HVC is a so-called half precharge potential,
It is supplied to each equalizing circuit.

The operation of the voltage generating circuit HVC is selectively stopped when an inversion internal control signal ICTB, which will be described later, is at a low level, whereby the standby current of the pseudo static RAM is reduced.

By the way, in the voltage generating circuit HVC, as shown in FIG.
As shown in FIG. 5 (b), a P channel M provided in a substantially series configuration between the power supply voltage and the ground potential of the circuit.
OSFET QP12 and N-channel MOSFET QN
The output potential, that is, the internal voltage HVC is set by the conductance ratio of 18. Then, an N channel MOSFET QN19 for output and a P channel MOSFE
TQP14 is provided, and these MOSFETs and N-channel MOSFETs QN17 and P in a current mirror form are provided.
By providing the channel MOSFET QP13 between the internal node N5 and the MOSFET QP12 or QN18, the fluctuation of the internal voltage HVC due to the fluctuation of the output current is suppressed. At this time, the output MOSFET QN1
9 and QP14 conductance gm19 and gm14
Is required to be gm19> gm17 gm14> gm13 with respect to the conductances gm17 and gm13 of the corresponding MOSFETs QN17 and QP13.

However, the output MOSFET Q
By increasing the conductance of N19 and QP14, a relatively large through current flows through these output MOSFETs. To deal with this, the threshold voltage V of the output MOSFETs QN19 and QP14 is
_THN19 and V _THP14 is compared to the threshold voltage V _THN17 and V _THP13 corresponding MOSFETQN17 and QP13, set the gate length such that _{V THN19 + V THP14> V THN17} + V THP13, to prevent a through current ing. However, the setting of the threshold voltage by the gate length is easily affected by the process variation, and the through current cannot be completely prevented. Further, the stop of the through current causes a dead zone of the internal voltage HVC, which causes a problem that the level control of the dead zone becomes difficult.

In order to deal with this, first, as shown in FIG. 55 (b), a method in which the well region of MOSFET QP13 is commonly coupled to its drain can be considered. That is, in the MOSFET QP13, the threshold voltage V _THP13 is reduced by the substrate effect due to the well region and the drain being commonly coupled, and the relationship of V _THP14 > V _THP13 is easily obtained. Therefore, the condition of the above equation can be easily realized without being affected by the process variation.

On the other hand, regarding the dead zone of the internal voltage HVC, as shown in FIG. 55 (a), the output MOSFET
Another pair of N-channel MOSFETs having a relatively small conductance in parallel with QN19 and QP14.
A method is conceivable in which the TQN 20 and the P-channel MOSFET QP15 are provided and the current flowing through the MOSFETs QN17 and QP13 is controlled. That is, these M
When the OSFET is added, the current I1 flowing through the MOSFETs QN17 and QP13 is
The conductance of QN20 and QP15 is gm
20 and gm15, and the current flowing through these MOSFETs is I2, I2 / I1 = (gm20 + gm15) / (gm17 + g
m13). As a result, by appropriately setting the conductance ratio of these MOSFETs, the MOSFET QN17
And the current I1 flowing through QP13 can be controlled relatively easily, which allows the internal voltage HV to be controlled.
Output MOSFET QN without giving dead zone to C
The through current of 19 and QP14 can be suppressed.

(2) VBB Voltage Generating Circuit The voltage generating circuit VBB forms the substrate back bias voltage VBB, which is, for example, a predetermined negative potential, on the basis of the power supply voltage VCC of the circuit, and the pseudo static RAM semiconductor substrate. Supply to.

The voltage generating circuit VBB is not particularly limited, but as shown in FIG. 33, an oscillating circuit OSC1 in which substantially five logic gate circuits are connected in series in a ring shape.
And a charge pump circuit VG1 that forms a predetermined substrate back bias voltage VBB in accordance with a pulse signal output from the oscillation circuit OSC1. By monitoring the level of the substrate back bias voltage VBB, the oscillation circuit OSC
A level detection circuit LVM for selectively setting 1 to the operating state is provided. The voltage generating circuit VBB further includes an oscillating circuit O in which nine inverter circuits are connected in series in a ring shape.
SC2 and a charge pump circuit VG2 that forms the substrate back bias voltage VBB in accordance with the pulse signal output from the oscillator circuit OSC2.

The level detection circuit LVM includes, but is not limited to, four P-channel MOSFETs and three N-channel MOSFETs provided in series between the circuit power supply voltage and the substrate back bias voltage supply point VBB. . These series MOSFETs selectively monitor the level of the substrate back bias voltage VBB on condition that the inverted internal control signal ICTB and the inverted timing signal φsrB are both set to the high level. As a result, when the absolute value of the substrate back bias voltage VBB exceeds a predetermined value, the output signal VB1 of the level detection circuit LVM is selectively set to the low level on condition that the inversion timing signal CE1B is at the high level.

When the inverted timing signal φsrB is low level, that is, when the pseudo static RAM is in the self refresh mode, the monitor operation of the level detection circuit LVM is stopped, and the oscillation circuit OSC1 has the inverted timing signal CE1B low level, that is, pseudo. The static RAM is selectively operated under the condition that it is operated in the self-refresh cycle. At this time, the oscillation circuit OSC2 is constantly operated.
As a result, in the self-refresh mode, the through current caused by the level detection circuit LVM is prevented, and the power consumption in the self-refresh mode of the pseudo static RAM is reduced.

On the other hand, when the inverted timing signal CE1B is at low level, that is, when the pseudo static RAM is in the selected state, the oscillation circuit OSC1 operates as the level detection circuit LV.
It is operated regardless of the output of M. As a result, the substrate back bias voltage VBB is prevented from lowering in the operating state of the pseudo static RAM. Furthermore, when the inverted internal control signal ICTB is at a low level, that is, when the power supply voltage of the circuit is supplied to the pad ICT, the level detection circuit LVM and the oscillation circuit OSC1 are unconditionally stopped from operating and oscillate. The circuit OSC2 is activated. As a result, in a predetermined probe test or the like, the standby current of the pseudo static RAM can be reduced and a confirmation test of leak current or the like can be performed.

The charge pump circuit VG1 has a boost capacitor C1 and forms a predetermined substrate back bias voltage VBB by the charge pump action of this boost capacitor. The charge pump circuit VG1 is designed so that the boost capacitor C1 has a relatively large electrostatic capacitance,
It has a relatively large current supply capability.

Similarly, the charge pump circuit VG2 has a boost capacitor C2 and forms a predetermined substrate back bias voltage VBB by the charge pump action of this boost capacitor. The boost capacitor C2 is designed to have a relatively small electrostatic capacity, and the charge pump circuit VG2 has a relatively small current supply capability.

By the way, this pseudo static RAM
In the voltage generating circuit VBB, the following measures are taken as a method of reducing the operating currents of the oscillation circuit OSC2 and the charge pump circuit VG2. That is, first,
As shown in FIG. 56 again, the oscillation circuit OSC2 basically has a ring oscillator in which nine inverter circuits are connected in series in a ring shape. In these inverter circuits, the conductance of each MOSFET is made extremely small, and the operating current thereof is supplied through a P-channel or N-channel MOSFET in the form of a current mirror, so that it is limited to an extremely small value. .

The output signal of the third-stage inverter circuit of the inverter circuits constituting the oscillation circuit OSC2, that is, the pulse signal φ1 is converted into an inverted pulse signal φ1B through the inverter circuit including the P-channel MOSFET QP7 and the N-channel MOSFET QN11. It is supplied to the gate of the P-channel MOSFET QP6 of the charge pump circuit VG2. The output signal of the sixth-stage inverter circuit is supplied as a pulse signal φ2 to the gate of the N-channel MOSFET QN8 of the charge pump circuit VG. As shown in FIG. 57, the inverted pulse signal φ1B and the pulse signal φ2 have their levels always in a complementary state and are not inverted in superposition with each other. In other words, one level is inverted. It has a predetermined phase relationship so that the level inversion of the other does not occur across.

As a result, MOSFETs QP6 and QN8
Cause the charge pump operation by the boost capacitor C2 while being turned on mutually exclusively. That is, the MOSFETs QP6 and QN8, when they constitute a normal CMOS inverter circuit, carry some shoot-through current when the corresponding pulse signal is inverted.
However, as described above, the MOSFETs QP6 and QN8 are turned on exclusively to each other, so that the MO
The through current due to the SFET is completely prevented, and the power consumption of the voltage generation circuit VBB is reduced.

(3) VL Voltage Generating Circuit As shown in FIG. 34, the voltage generating circuit VL lowers the power supply voltage VCC of the circuit to generate a predetermined internal voltage VL.
To form. This internal voltage VL is the voltage generation circuit VBB.
It is used as a reference potential for a clamp circuit or the like provided in the above.

The voltage generation circuit VL selectively stops its operation when the inverted internal control signal ICTB is set to the low level, whereby the pseudo static RAM.
Standby current is reduced.

3.2.7. Test circuit (1) High voltage detection circuit As described above, the pseudo static RAM selects the test mode by supplying a predetermined high voltage exceeding the power supply voltage of the circuit to the external terminal OEB, WEB or CEB. Is set automatically. Further, by supplying the high voltage as described above to the address input terminal A4, a signature signal relating to the redundant circuit is transmitted. For this reason, the pseudo static RAM includes four high voltage detection circuits EHG provided corresponding to these external terminals.

As shown in FIG. 35, high voltage detection circuit EHG includes a plurality of MOSFETs provided in series between each of the external terminals and the ground potential of the circuit. When the high voltage is supplied to the corresponding external terminal, its output signal, that is, the inverted internal control signal φeh1
B to φeh4B are selectively set to the low level. These inverted internal control signals φeh1B to φeh4B are supplied to the corresponding test circuit or signature circuit SG.

(2) ICT Signal Generating Circuit The ICT signal generating circuit ICT, when the circuit power supply voltage is supplied to the pad ICT, as shown in FIG.
Selectively its output signal, that is, inverted internal control signal ICTB
To low level. When the pad ICT is opened, the inverted internal control signal ICTB is fixed to the high level. As described above, the inverted internal control signal ICTB is supplied to the voltage generation circuits HVC, VBB, VL, etc., and is used to reduce the standby current of the pseudo static RAM during a predetermined probe test.

(3) FCK Signal Generating Circuit The FCK signal generating circuit FCK, as shown in FIG. 34, when the power supply voltage of the circuit is supplied to the pad FCK,
If the timing signal P4 is at high level,
Selectively its output signal, that is, inverted internal control signal FCKB
To low level. When the pad FCK is opened, the inverted internal control signal FCKB changes to the timing signal P
Fixed to high level regardless of 4. The inverted internal control signal FCKB is supplied to the X-system redundant circuit and the Y-system redundant circuit as described above, and is used for the confirmation test of the half-breakage of the fuse.

(4) Signature Circuit The signature circuit SG is as shown in FIG.
It includes one N-channel MOSFET provided between the address input terminal A5 and the ground potential of the circuit. This MO
In the SFET, the internal control signal SIGX or SIGY output from the X system redundant circuit or the Y system redundant circuit is set to the high level, and the output signal of the high voltage detection circuit EHG, that is, the inverted internal control signal φeh4B is set to the low level. Under the condition, it is turned on, and the address input terminal A5 is short-circuited to the ground potential of the circuit. As a result, pseudo-static RA
After the completion of M, by monitoring the address input terminal A5, it is possible to determine that the defective address is assigned to either the redundant word line or the redundant complementary data line.

As shown in the above embodiments, by applying the present invention to a semiconductor memory device such as a pseudo static RAM, the following operational effects can be obtained. (1) A pair of N-channel type output MOSFs provided in the form of a totem pole between the power supply voltage of the circuit and the ground potential.
In an output buffer including an ET and a latch circuit that holds output data corresponding to the ET, by presetting the latch circuit to a logic "0" or a logic "1", the rise of the output buffer at a low level or a high level is output. The effect that the speed can be selectively increased can be obtained.

(2) In an oscillating circuit that forms a predetermined pulse signal by repeating charging and discharging of a capacitor, a MOSFET that forms a charge or discharge current path for the capacitor and determines the frequency of the oscillating circuit is a constant current source. MOS that composes
A first well region, which is coupled to the power supply voltage of the circuit, is formed in the lower layer of the polycrystalline silicon layer, which constitutes a resistor for setting the current value of the constant current source, while being coupled to the FET by current mirror coupling. Then, by forming the second well region coupled to the ground potential of the circuit in the lower layer corresponding to the remaining half, the substrate capacitance between the resistor and the power supply voltage of the circuit and the ground potential can be made uniform. As a result, it is possible to suppress the characteristic deterioration of the oscillator circuit included in the refresh timer circuit or the like due to the power supply bump or the like.

(3) An odd number of inverter circuits substantially connected in series in a ring shape to an oscillation circuit included in the substrate back bias voltage generation circuit and the like, and provided between the output node and the power supply voltage or ground potential of the circuit. By providing a pair of P-channel and N-channel MOSFETs which are exclusively turned on by receiving output signals of two inverter circuits of different predetermined stages among the above-mentioned inverter circuits, a through current by these MOSFETs is provided. Is obtained, and the power consumption of the oscillation circuit and thus the substrate back bias voltage generation circuit can be reduced.

(4) Selective through a current mirror circuit which is selectively charged through a P-channel MOSFET which is turned on according to a predetermined timing signal and which transmits a predetermined discharge current formed by a constant current source. In an oscillating circuit including a capacitor to be discharged into a capacitor, the charge voltage of the capacitor and the reference potential of the constant current source are formed by another capacitor that is simultaneously floated when the P-channel MOSFET is turned off. Thus, it is possible to obtain the effect that it is possible to suppress frequency fluctuations due to power supply bumps or the like of the oscillation circuit included in the refresh timer circuit or the like.

(5) A first P-channel and N-channel MOSFET provided in series between the power supply voltage and the ground potential of the circuit, and a second P-channel and N-channel MOS provided in parallel with these MOSFETs.
FET and the first P channel and N channel M
The second P channel and N provided between the OSFETs
Channel MOSFETs and third P-channel and N-channel MOSFETs, each in current mirror form
In the voltage generating circuit including, by commonly coupling the drain of the third P-channel MOSFET and the well region thereof, the through current due to the second P-channel and N-channel MOSFET is suppressed without process fluctuation, The effect that the power consumption of the voltage generating circuit can be reduced can be obtained. (6) In the above item (5), the second P-channel and N-channel MOSFETs are arranged in parallel with each other and the third
And a fourth P-channel and N-channel MOSFET in a current mirror form with the P-channel and N-channel MOSFET of FIG.
By appropriately setting the conductance ratio with the P-channel and N-channel MOSFETs, the through-current caused by the second P-channel and N-channel MOSFETs is suppressed without causing a dead zone in the voltage generating circuit, It is possible to obtain the effect that the power consumption can be reduced.

(7) A fuse circuit provided in a redundant circuit or the like is basically constructed by a fuse logic gate circuit in which a fuse means is provided between an output node of the redundancy circuit and a P channel or N channel MOSFET. It is possible to obtain an effect that the circuit configuration of (3) can be simplified and the cost of the redundant circuit and the like can be reduced. (8) In the above item (7), the fuse circuit is provided with a pair of the fuse logic gate circuits, and the output signals of the fuse logic gate circuits are subjected to exclusive OR combination, whereby the fuses once cut, for example. Since it is possible to invalidate the means, it is possible to provide flexibility in assigning a defective address of the redundant circuit, and it is possible to improve the yield of the pseudo static RAM or the like.

(9) The refresh cycle of the pseudo static RAM is set to PS (pseudo) refresh or V
By adopting a configuration that can be selectively switched in the S (virtual) refresh mode, the pseudo static RAM applicable to both the PS refresh mode and the VS refresh mode can be efficiently used based on a common semiconductor substrate. The effect is that it can be developed and manufactured.

(10) For example, by selectively transmitting a plurality of signals having different meanings depending on the operation mode via a predetermined signal line provided between the Y predecoder and the Y decoder, a relatively large layout margin can be obtained. There is an effect that the number of signal lines arranged in a non-existing area can be reduced and the chip area of the pseudo static RAM or the like can be reduced.

(11) The main amplifier is connected to the static type main amplifier coupled to the common I / O line and the corresponding non-inverted and inverted signal lines of the common I / O line when the main amplifier is operated. In a pseudo-static RAM or the like including a preset MOSFET for providing a bias level that maximizes the sensitivity, the preset MOSFET is temporarily turned on immediately before the main amplifier is put into operation. The operation current can be reduced, and the power consumption of the pseudo static RAM or the like can be reduced.

(12) A plurality of redundant addresses for holding the corresponding bit of the defective address assigned to the corresponding redundant word line or redundant data line and comparing and collating this with the corresponding bit of the address signal supplied at the time of memory access. In a redundant circuit including a comparator circuit and a plurality of cascade MOSFETs provided in series between a predetermined detection node and the ground potential of the circuit and receiving the output signal of the redundant address comparator circuit corresponding to the gate, the redundant address By disposing the comparison circuit and the cascade MOSFET corresponding to the address input pads dispersedly arranged on the semiconductor substrate surface and closely arranged, the signal transmission delay time in the redundant circuit is reduced, and the pseudo static RA
The effect that the speed of M etc. can be increased can be obtained.

(13) A plurality of memory arrays, each of which forms a pair and two of which form a pair, are arranged symmetrically with each other, and are shared by the two memory arrays of the pair, and these memory arrays are pierced so as to be skewed. Pseudo-static RAM with common I / O lines arranged in parallel
Etc., by crossing the non-inverted and inverted signal lines of the common I / O line in the middle of the two memory arrays forming a pair, the parasitic capacitance of the common I / O line due to misalignment of the photomask and the like is reduced. The effect of offsetting the change and stabilizing the operation of the pseudo static RAM or the like is obtained. (14) In the above item (13), by equalizing the common I / O line in the middle of the corresponding two memory arrays and outside both of them, the equalization process of the common I / O line is speeded up and stabilized. The effect that it can be obtained.

(15) In a pseudo-static RAM or the like having a plurality of sense amplifiers provided corresponding to each complementary data line of the memory array, the source of the P-channel or N-channel MOSFET which constitutes the above-mentioned sense amplifier is corresponded to The common source line made of a metal wiring layer such as aluminum is commonly coupled via the contact, and the diffusion layer forming the source region is extended to form an adjacent P channel or N channel MOSFE.
By further commonly connecting the sources of T pairs, it is possible to improve the yield of the pseudo static RAM or the like by relieving a sense amplifier failure due to contact failure or the like.

(16) A plurality of memory arrays dispersedly arranged on the surface of the semiconductor substrate, a plurality of decoders provided corresponding to these memory arrays, and a predecode signal formed in accordance with a predetermined address signal for each decoder. Pseudo static RAM having a predecoder for supplying to
Etc., a driver for selectively transmitting the predecoded signal to the corresponding decoder is distributedly arranged in the vicinity of the corresponding decoder to reduce the transmission delay time of the predecoded signal, and thus the pseudo static type RAM
It is possible to obtain the effect that the processing speed can be increased.

(17) In a pseudo static RAM or the like having a plurality of memory arrays each including a plurality of redundant word lines or redundant complementary data lines and arranged in line symmetry with respect to the center line of the semiconductor substrate surface, By arranging the redundant word lines or the redundant data lines in a line-symmetrical order with the center line as an axis, the fault occurrence rate of the redundant word lines or the redundant data lines arranged outside is intentionally increased and It is said that the failure rate of the redundant word line or the redundant data line arranged inside can be lowered, the failure rate of the entire redundant word line or the redundant data line can be suppressed, and the yield of the pseudo static RAM or the like can be improved. The effect is obtained.

(18) In a pseudo static RAM or the like including a refresh timer counter circuit, etc., whose counting initial value is selectively set by cutting the fuse means, in a predetermined test mode, for example, when an address input terminal is By making it possible to equivalently and selectively set the blown state of the fuse means by the test signal supplied via the test signal, the characteristic evaluation of the refresh timer counter circuit or the like of the pseudo static RAM or the like can be surely and efficiently performed. The effect that it can be carried out is obtained.

(19) In a pseudo static RAM having a self-refresh mode and having a refresh timer counter circuit for starting a refresh operation in the self-refresh mode in a predetermined cycle, a refresh timer counter is used in a predetermined test mode. A test activation signal supplied via a predetermined external terminal can be used instead of the refresh activation signal by the circuit, so that the refresh cycle in the self-refresh mode of the pseudo static RAM or the like is arbitrarily set, and The effect that the characteristic evaluation can be efficiently performed is obtained. (20) In the above item (19), the refresh address in the self-refresh mode can be arbitrarily designated, for example, via an address input terminal, so that the address dependency in the refresh operation of the pseudo static RAM or the like can be made efficient. The effect that it can be tested is obtained.

(21) A predetermined high voltage whose absolute value exceeds the power supply voltage of the circuit is selectively combined and supplied to the plurality of external terminals to selectively set the test mode, and By adopting a configuration capable of starting a substantial test operation, it is possible to simplify a test circuit such as a pseudo static RAM and reduce the cost thereof. (22) Due to the above effects, the pseudo static type R
It is possible to obtain the effect that the operation speed of the AM and the like can be reduced and the power consumption can be reduced while stabilizing the operation of the AM and the like.

(23) A pseudo static RAM having a self-refresh mode is provided with a refresh timer circuit for setting a refresh cycle, and the cycle of its output signal can be selectively switched. PS that is performed in a relatively long cycle during battery backup in the refresh mode
(Pseudo) refresh mode and pseudo static type R
(EN) Provided is a pseudo static RAM or the like which can selectively realize a VS (virtual) refresh mode which is performed in a relatively short period between AM activation states with a single common semiconductor substrate. The effect of being able to be obtained is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the number of divisions of the memory array and the combination with each peripheral circuit are arbitrary, and the number of word lines, redundant word lines, complementary data lines, redundant complementary data lines, common I / O lines, etc. provided in each memory array. Is also optional. Various embodiments may be considered for the operation mode and test mode provided in the pseudo static RAM, the type of operation cycle, and the combination of the corresponding start control signals.
The same applies to the number of start control signals, address signals, input / output data, etc., logic levels, and combinations thereof. Furthermore, the specific circuit configurations and layouts of the respective parts shown in the circuit diagrams and layout diagrams, the logic levels of the internal control signals and the timing signals, combinations thereof, and the like are not restricted by this embodiment.

In the above description, the case where the invention made by the present inventor is mainly applied to the pseudo static RAM which is the field of application which is the background of the invention has been described. The inventions relating to the buffer, the oscillation circuit, the voltage generating circuit, the fuse circuit, the layout system and the test system can be applied to various other semiconductor memory devices and semiconductor integrated circuit devices. These inventions can be widely applied to semiconductor memory devices or semiconductor integrated circuit devices that include or require at least corresponding circuits.

[0241]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, pseudo static RAM
Of a refresh timer circuit or the like, which constitutes a charge or discharge current path for the capacitor of the oscillation circuit included in the refresh timer circuit, and determines the frequency of the oscillation circuit,
In addition to the current mirror coupling with the MOSFET constituting the constant current source, it was coupled to the power supply voltage of the circuit under the portion corresponding to approximately one half of the polycrystalline silicon layer constituting the resistor for setting the current value of the constant current source. A well region is formed, and a well region coupled to the ground potential of the circuit is formed in the lower layer corresponding to the remaining half. A test mode in which the initial count value of the refresh timer counter circuit of the refresh timer circuit can be arbitrarily set to the pseudo static RAM or the like, for example, via an address input terminal, or a test in which the refresh cycle is supplied from a predetermined external terminal Prepare a test mode that can be set arbitrarily by the control signal. Further, a refresh timer circuit for setting a refresh cycle is provided in a pseudo static RAM having a self-refresh mode so that the cycle of its output signal can be selectively switched.

As a result, the discharge current of the capacitor of the oscillation circuit such as the refresh timer circuit is stabilized, and almost the same parasitic capacitance is coupled between the polycrystalline silicon resistor and the power supply voltage of the circuit and the ground potential. Fluctuations can be offset, and fluctuations in the oscillation frequency of the oscillation circuit due to power supply bumps or the like can be suppressed. Since the operating characteristics of the oscillator circuit and the refresh timer counter circuit and the address dependency of the information holding characteristics of the memory cell can be efficiently tested and confirmed, the pseudo static type R
The AM refresh cycle can be set accurately and at a value closer to the information holding capacity of the memory cell.
Further, in the self-refresh mode, for example, a PS (pseudo) refresh mode that is performed in a relatively long cycle at the time of battery backup, and a VS that is performed in a relatively short cycle after the pseudo static RAM is activated. (Virtual) refresh mode is 1
It is possible to provide a pseudo static RAM or the like that can be selectively realized by using one common semiconductor substrate. As a result, the power consumption can be promoted while stabilizing the operation of the pseudo static RAM.

[Brief description of drawings]

FIG. 1 is a pseudo static RA to which the present invention is applied.
It is a block diagram which shows one Example of M.

FIG. 2 is a pseudo static RA to which the present invention is applied.
It is a block diagram which shows one Example of M.

FIG. 3 is a pseudo static RA to which the present invention is applied.
It is a block diagram which shows one Example of M.

FIG. 4 is a layout diagram showing an embodiment of the pseudo static RAM shown in FIGS. 1 to 3;

FIG. 5: Pseudo-static type RA to which the present invention is applied
It is a timing diagram which shows one Example of each operation cycle of M.

FIG. 6 is a pseudo static RA to which the present invention is applied.
It is a timing diagram which shows one Example of each operation cycle of M.

FIG. 7 is a pseudo static RA to which the present invention is applied.
It is a timing diagram which shows one Example of each operation cycle of M.

FIG. 8 is a pseudo static RA to which the present invention is applied.
It is a timing diagram which shows one Example of each operation cycle of M.

FIG. 9 is a pseudo static RA to which the present invention is applied.
It is a timing diagram which shows one Example of each operation cycle of M.

FIG. 10 is a pseudo static type R to which the present invention is applied.
It is a timing diagram which shows one Example of each operation cycle of AM.

FIG. 11 is a pseudo static type R to which the present invention is applied.
It is a timing diagram which shows one Example of each operation cycle of AM.

FIG. 12 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 13 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 14 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 15 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 16 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 17 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 18 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 19 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 20 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 21 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 22 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 23 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 24 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 25 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 26 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 27 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 28 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 29 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 30 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 31 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 32 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 33 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 34 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 35 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 36 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 37 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 38 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows the concrete structure of each part of AM.

FIG. 39 is a pseudo static type R to which the present invention is applied.
It is a signal waveform diagram which shows one Example of AM.

FIG. 40 is a pseudo static type R to which the present invention is applied.
It is a signal waveform diagram which shows one Example of AM.

FIG. 41 is a pseudo static type R to which the present invention is applied.
It is a signal waveform diagram which shows one Example of AM.

FIG. 42 is a pseudo static type R to which the present invention is applied.
It is a conceptual diagram for demonstrating the memory array part of AM.

FIG. 43 is a pseudo static type R to which the present invention is applied.
It is a block diagram for explaining a sense amplifier unit of AM.

FIG. 44 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows one Example of the redundancy enable circuit of AM.

FIG. 45 is a pseudo static type R to which the present invention is applied.
It is a circuit block diagram which shows one Example of the X system redundancy circuit of AM.

FIG. 46 is a pseudo static type R to which the present invention is applied.
FIG. 4 is a partial circuit diagram showing an example of an AM Y decoder.

FIG. 47 is a pseudo static type R to which the present invention is applied.
It is a partial circuit diagram which shows one Example of the main amplifier of AM, and its peripheral circuit.

48 is a signal waveform diagram for explaining an operation of the main amplifier of FIG. 47.

FIG. 49 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows one Example of the data output buffer of AM.

FIG. 50 is a pseudo static type R to which the present invention is applied.
FIG. 3 is a block diagram showing an embodiment of an AM refresh timer circuit and a refresh tamper counter circuit.

51 is a partial circuit diagram showing an embodiment of the refresh timer circuit and the refresh timer counter circuit of FIG. 50.

52 is a waveform diagram for explaining the operation of the refresh timer circuit and the refresh timer counter circuit of FIG. 50.

53 is a configuration diagram showing an embodiment of the refresh timer circuit of FIG. 50.

FIG. 54 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows another Example of the refresh timer circuit of AM.

FIG. 55 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows one Example of the voltage generation circuit HVC of AM.

FIG. 56 is a pseudo static type R to which the present invention is applied.
It is a circuit diagram which shows one Example of the oscillation circuit contained in the voltage generation circuit VBB of AM.

57 is a waveform diagram for explaining the operation of the oscillation circuit of FIG. 56.

FIG. 58 is a pseudo static type R to which the present invention is applied.
It is a block diagram which shows one Example of the signal transmission path regarding the redundant data line selection signal of AM.

FIG. 59 is a pseudo static type R to which the present invention is applied.
FIG. 7 is a partial plan layout view showing an example of an AM common I / O line.

[Explanation of symbols]

TG ... Timing generator, CE ... CE timing generator, WE ... WE timing generator, WC
...... Word line clear circuit, OE ... OE system timing generation circuit, TMR ... Refresh timer circuit, SRC
...... Refresh timer counter circuit, SCNTR ...
... refresh timer counter unit circuit, PC ... precharge control circuit, XAB ... X address buffer,
PXD ... X predecoder, RFC ... Refresh counter, CNTR ... Refresh counter unit circuit,
XR0 to XR3 ... X system redundant circuit, φXG ... Word line drive signal generation circuit, PWD ... Word line selection drive signal generation circuit, PRWD ... Redundant word line selection drive signal generation circuit, SP, SN ... Sense amplifier Drive circuit, YAB ...
Y address buffer, PYD ... Y predecoder, YR
AC0 to YRAC7 ... Y system redundancy circuit, MALL to MA
RR ... Main amplifier, ASL ... Array selection circuit, D
IB ... data input buffer, DILL to DIRR ...
Writing circuit, WS ... Writing selection circuit, DOB ...
Data output buffer, OSL ... Output selection circuit, HV
C, VBB, VL ... Voltage generation circuit, ICT, FCK ...
... Signal generation circuit, EHG ... High voltage detection circuit, SG ...
Signature circuit, XD0L to XD3R ... X decoder, YD0 to YD3 ... Y decoder, MARY0L to M
ARY3R ... Memory array, SA0L to SA3R ...
Sense amplifier, CS0L to CS3R ... Column switch.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technology display location G11C 11/34 371J (72) Inventor Yutaka Shinbo 2326 Imai, Ome-shi, Tokyo Hitachi Device Development Center ( 72) Inventor Katsuyuki Sato 2326 Imai, Ome-shi, Tokyo Inside Hitachi, Ltd. Device Development Center (72) Inventor Masahiro Ogata 5-20-1 Joumizuhoncho, Kodaira-shi, Tokyo Engineering Co., Ltd. (72) Inventor Kanehide Kanezaki 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hirate Super LSI Engineering Co., Ltd. (72) Inventor Masatsugu Kubo, Kodaira, Tokyo 5-20-1 Jitsumizu Honcho, Ichi, Japan, within Hitate Super LSI Engineering Co., Ltd. (72) Inventor Nobuo Kato 5-20-1, Kamimizuhoncho, Kodaira, Tokyo Metropolitan Government I engineering stock In-house (72) Inventor Kiichi Manita 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Within Hitate Cho-LS Engineering Co., Ltd. (72) Inventor Michitaro Kanemitsu 5-chome, Mizumizuhoncho, Kodaira-shi, Tokyo No. 20-1 Hitate Super LSI Engineering Co., Ltd.

Claims (41)

[Claims] 1. An internal terminal, an external output terminal, a first MOSFET for controlling injection of a charge current to the internal terminal and extraction of a discharge current from the internal terminal, and a current mirror configuration for the first MOSFET. And a second MOSFET connected in series with the current path of the second MOSFET, coupled between the first power supply voltage and the second power supply voltage, and substantially setting the value of the charge current or the discharge current. A resistor, a first logic inverter having an input terminal coupled to the internal terminal, a delay circuit and a second logic inverter coupled in series between the external output terminal and the output terminal of the first logic inverter. And a feedback circuit that includes a feedback circuit including: The resistor includes a polysilicon layer formed on an insulating layer formed on the semiconductor substrate, and the insulating layer substantially includes a first well region and a second well region formed in the semiconductor substrate. The first well region and the second well region are formed apart from each other by a predetermined distance, and the polysilicon layer is formed on the first well region and the second well region in plan view. An oscillating circuit characterized by being arranged so as to overlap each other. 2. The first power supply voltage according to claim 1, the absolute value of which is higher than the second power supply voltage, and the first power supply voltage is supplied to the first well region. The second well region is supplied with the second power supply voltage. 3. The oscillator circuit according to claim 2, wherein the semiconductor substrate is of P conductivity type, and the first well region and the second well region are of N conductivity type. 4. The third MOSFET according to claim 1, wherein the first logic inverter has a source-drain path coupled between the first power supply voltage and an output terminal of the first logic inverter. And the first
A fourth MOSF having a source-drain path coupled between the output terminal of the logic inverter and the second power supply voltage.
ET, the second logic inverter includes a fifth MOSFET having a source-drain path coupled between the first power supply voltage and the external output terminal, the external output terminal and the second power supply voltage. An oscillating circuit comprising a sixth MOSFET having a source-drain path coupled between. 5. The device according to claim 4, wherein the third MOSFET and the fifth MOSFET are P
The MOSFET is a channel type MOSFET, and the fourth MOSFET and the sixth MOSFET are N-type.
An oscillation circuit characterized by being a channel type MOSFET. 6. The first MOSFET according to claim 1, wherein the first MOSFET has a source-drain path coupled between the internal terminal and the second power supply voltage, and the oscillation circuit has the first and second drain paths. An oscillator circuit further comprising a third MOSFET having a source / drain path coupled between one power supply voltage and the internal terminal, and a gate coupled to the external output terminal. 7. The oscillation circuit according to claim 6, further comprising a fourth MOSFET having a source-drain path coupled between the source-drain path of the third MOSFET and the internal terminal, The current mirror configuration is a current mirror arrangement having a controlled current path and a non-controlled current path, wherein the controlled current path is the resistor and the second MOSFE.
And the controlled current path includes the first MOSFET and the third M
An oscillator circuit including an OSFET and a fourth MOSFET. 8. The gate according to claim 7, wherein the gate of the second MOSFET is the first MOSFET.
The gate of the second MOSFET is coupled to the gate of the second MOSFET.
An oscillator circuit, characterized in that it is coupled to the drain of T and one end of the resistor, and the source of the second MOSFET is coupled to the second power supply voltage. 9. The fifth MOSF according to claim 8, wherein the oscillation circuit has a source-drain path coupled between the first power supply voltage and the resistor.
ET, the control current path further includes the fifth MOSFET, the first logic inverter is a source-drain path coupled between the first power supply voltage and an output terminal of the first logic inverter. A sixth MOSFET having:
A seventh MOSFET having a source-drain path coupled between the output terminal of the logic inverter and the second power supply voltage, and a gate coupled to the internal terminal, wherein the second logic inverter comprises the first Between an eighth MOSFET having a source-drain path coupled between a power supply voltage and the external output terminal and a gate coupled to the output terminal of the delay circuit, and between the external output terminal and the second power supply voltage Nth M having a source-drain path coupled to the gate and a gate coupled to the output terminal of the delay circuit
OSFET, and the gate of the fifth MOSFET is the sixth MOSFET.
The gate of the fourth MOSFET is coupled to the gate of the T.
An oscillator circuit characterized in that it is coupled to the drain of T. 10. The claim, wherein the first MOSFET, the second MOSFET, the seventh MOSFET, and the ninth MOSFET are first conductivity type MOSFETs, the third MOSFET, the fourth MOSFET, and the third MOSFET. 5 MOSFET, the 6th MOSFET, and the 8Mth
The OSFET is an oscillating circuit characterized by being a MOSFET of the second conductivity type. 11. The MOSFET according to claim 10, wherein the first conductivity type MOSFET is an N-channel MOS.
The second conductivity type MOSFET is a P-channel MOS
An oscillation circuit characterized by being a FET. 12. The first power supply voltage according to claim 11, which is larger in absolute value than the second power supply voltage, and the first power supply voltage is supplied to the first well region. An oscillation circuit, wherein the second power supply voltage is supplied to the second well region. 13. The oscillator circuit according to claim 12, wherein the semiconductor substrate is of P conductivity type, and the first well region and the second well region are of N conductivity type. 14. The oscillator circuit according to claim 13, wherein the resistor is coupled between a source-drain path of the second MOSFET and a source-drain path of the fifth MOSFET. 15. The semiconductor substrate according to claim 14, further comprising: a plurality of dynamic memory cells, and a refresh timer circuit that determines a refresh cycle of a refresh operation of the plurality of dynamic memory cells. An oscillation circuit, wherein the refresh timer circuit is formed, the refresh timer circuit includes the oscillation circuit, and the oscillation circuit is a ring oscillator. 16. The semiconductor substrate according to claim 1, further comprising: a plurality of dynamic memory cells, and a refresh timer circuit that determines a refresh operation cycle of the plurality of dynamic memory cells. The refresh timer circuit includes the oscillator circuit, and the oscillator circuit is a ring oscillator. 17. The oscillator circuit according to claim 16, wherein the first power supply voltage is a predetermined positive potential, and the second power supply voltage is a ground potential. 18. An external output terminal, a first N-channel MOSFET having a source coupled to receive a first power supply voltage, a gate coupled to the gate of the first N-channel MOSFET, and the first power supply voltage. A third N-channel MOSFET having a second N-channel MOSFET having a source coupled to receive, a gate coupled to the gate of the first N-channel MOSFET, and a source coupled to receive the first power supply voltage. A first P-channel MOSFET having a gate coupled to the external output terminal, a drain coupled to the drain of the first N-channel MOSFET, and a source coupled to receive a second power supply voltage; A second having a source coupled to receive a second power supply voltage A third P having a channel MOSFET, a gate coupled to the gate of the second P-channel MOSFET, a source coupled to receive the second power supply voltage, and a drain coupled to the drain of the third N-channel MOSFET. A channel MOSFET, a resistor having a current path having one end coupled to the drain of the second P-channel MOSFET and the other end coupled to the drain of the second N-channel MOSFET, and coupled to the drain of the third N-channel MOSFET. An oscillation circuit comprising: a delay circuit having an input terminal; an inverter circuit having an input terminal coupled to an output terminal of the delay circuit; and an output terminal coupled to the external output terminal, the second N-channel The drain of the MOSFET and the second The gate of the N-channel MOSFET is coupled, the drain of the second P-channel MOSFET and the gate of the second N-channel MOSFET are coupled, the oscillation circuit is formed on a semiconductor substrate, and the resistor is the semiconductor. A polysilicon layer formed on an insulating layer formed on the substrate, wherein the insulating layer is formed substantially on the first well region and the second well region formed in the semiconductor substrate; The first well region and the second well region are formed apart from each other by a predetermined distance, and the polysilicon layer is arranged so as to substantially overlap the first well region and the second well region in plan view. An oscillating circuit characterized in that 19. The value of the first power supply voltage is larger in absolute value than the value of the second power supply voltage according to claim 18, and the first power supply is provided in the first well region. A voltage is supplied to the second well region, and the second power supply voltage is supplied to the second well region. 20. The oscillator circuit according to claim 19, wherein the semiconductor substrate is of P conductivity type, and the first well region and the second well region are of N conductivity type. . 21. The semiconductor substrate according to claim 20, further comprising a plurality of dynamic memory cells, and a refresh timer circuit for determining a refresh cycle of a refresh operation of the plurality of dynamic memory cells. An oscillation circuit, wherein the refresh timer circuit is formed, the refresh timer circuit includes the oscillation circuit, and the oscillation circuit is a ring oscillator. 22. The oscillator circuit according to claim 21, wherein the first power supply voltage is a predetermined positive potential, and the second power supply voltage is a ground potential. 23. The oscillator circuit according to claim 18, wherein the delay circuit includes an even number of inverter circuits coupled in series. 24. The oscillator circuit according to claim 23, wherein the logic inverter included in the delay circuit includes a P-channel MOSFET and an N-channel MOSFET. 25. The oscillation circuit according to claim 18, wherein the source is connected to the drain of the first P-channel MOSFET, and the drain is connected to the drain of the first N-channel MOSFET.
An oscillator circuit further comprising a fourth P-channel MOSFET having a gate, wherein the gate of the fourth P-channel MOSFET is coupled to the drain of the fourth P-channel MOSFET. 26. A semiconductor memory device having a plurality of memory cells and a control circuit, wherein when the device is in a first self-refresh mode, the control circuit performs a first refresh cycle on the plurality of memory cells. A refresh operation is performed every time, and when the device is in the second self-refresh mode, the control circuit causes the plurality of memory cells to perform a second refresh cycle that is longer than the first refresh cycle. A semiconductor memory device characterized by executing a refresh operation. 27. The device according to claim 26, wherein the device further includes a plurality of word lines and a plurality of data lines, each of the plurality of memory cells corresponding to a corresponding word line. And a timing signal forming means for forming at least one of a first timing signal that determines the first refresh cycle and a second timing signal that determines the second refresh cycle. A refresh address signal forming means for forming a refresh address signal for selecting a word line to which a memory cell to be refreshed is connected, the refresh address signal forming means for generating a refresh address signal when the device is in the first self refresh mode. , Above first
The refresh address signal forming means forms the refresh address signal in response to a timing signal, and the refresh address signal forming means generates the refresh address signal when the device is in the second self refresh mode.
A semiconductor memory device, wherein the refresh address signal is formed in response to a timing signal. 28. The timing signal forming means according to claim 27, wherein the timing signal forming means forms a third timing signal having a first frequency, and the second frequency has a second frequency based on the third timing signal. Means for forming a first timing signal and means for forming the second timing signal having a third frequency based on the third timing signal, wherein the third frequency is lower than the second frequency A semiconductor memory device characterized by: 29. The semiconductor memory device according to claim 28, wherein the refresh address signal forming means includes a counter circuit which forms the refresh address signal. 30. The semiconductor memory device according to claim 29, wherein the counter circuit includes a plurality of unit counters connected in series so as to form a binary counter. 31. At least one of the plurality of word lines according to claim 30, wherein when the device is in a normal operation mode, at least one of the plurality of word lines is selected based on an external address signal input from the outside of the device. A semiconductor memory device characterized by the above. 32. The normal operation mode according to claim 31, wherein the normal operation mode includes a read operation mode and a write operation mode, and when the device is in the read operation mode, the data held in the memory cell is A semiconductor memory device is characterized in that data is read based on the external address signal and data is written into a memory cell based on the external address signal when the device is in the write operation mode. 33. The device according to claim 32, wherein when the device is in an auto-refresh mode, once for each of the plurality of memory cells in response to a control signal input from the outside of the device. A semiconductor memory device characterized in that a refresh operation is executed only. 34. The semiconductor memory device according to claim 33, wherein each of the plurality of memory cells is a dynamic memory cell including an information storage capacitor and an address selection MOSFET. 35. The semiconductor memory device according to claim 28, wherein the first frequency is higher than the second frequency and the third frequency. 36. The semiconductor memory device according to claim 35, wherein the third frequency is half the frequency of the second frequency. 37. A plurality of word lines, a plurality of data lines, a plurality of memory cells, a means for forming a first timing signal having a second frequency, and a third frequency having a third frequency different from the second frequency. 2. A semiconductor memory device comprising: means for forming a timing signal; and refresh address signal forming means for forming a refresh address signal for selecting a word line to which a memory cell to be refreshed is connected. Is coupled to a corresponding word line and a corresponding data line, and when the device is in the first self-refresh mode, the refresh address signal forming means outputs the refresh address signal in response to the first timing signal. When the device is in the second self-refresh mode, the refresh address signal is generated. Forming means, a semiconductor memory device characterized by forming the refresh address signal in response to said second timing signal. 38. The apparatus of claim 37, wherein the device further comprises means for forming a third timing signal having a first frequency, the first timing signal and the second timing signal being the first timing signal. A semiconductor memory device, which is formed based on three timing signals, wherein the third frequency is lower than the second frequency. 39. A plurality of word lines including a first word line, a plurality of data lines, a plurality of memory cells, and a refresh address signal for selecting a word line to which a memory cell to be refreshed is coupled is formed. A semiconductor memory device including a refresh address signal forming means, wherein each of the plurality of memory cells is coupled to a corresponding word line and a corresponding data line, and the refresh operation is performed when the device is in a first self-refresh mode. The address signal forming means performs a refresh operation on the memory cells coupled to the first word line every first cycle, and when the device is in the second self-refresh mode, the refresh address signal forming means is The refresh operation is performed on the memory cells coupled to the first word line every second period different from the first period. A semiconductor memory device characterized by executing a read operation. 40. The device according to claim 39, wherein the device provides at least one of a first timing signal that determines the first period and a second timing signal that determines the second period. Timing signal forming means for forming the refresh address signal forming means, wherein the refresh address signal forming means forms the first signal when the device is in the first self-refresh mode.
The refresh address signal forming means forms the refresh address signal in response to a timing signal, and the refresh address signal forming means generates the refresh address signal when the device is in the second self refresh mode.
A semiconductor memory device, wherein the refresh address signal is formed in response to a timing signal. 41. In the claim 40, the timing signal forming means has a means for forming a third timing signal having a first frequency, and a second frequency based on the third timing signal. Including means for forming the first timing signal and means for forming the second timing signal having a third frequency based on the third timing signal, the third frequency being less than the second frequency A semiconductor memory device characterized by the above.