JPH08279462A - Vapor growth method - Google Patents

Abstract

PURPOSE: To secure even thickness in depositing and growing simultaneously a polycrystalline layer and a single-crystal layer by conducting a vapor growth method after device separation. CONSTITUTION: A technique of conducting a vapor growth method after damaging both an insulating material layer 2 and an exposed silicon wafer part 3 is employed for the process of simultaneously growing a polycrystalline silicon 7 on the insulating material layer 2 and a single-crystal silicon 6 on the exposed silicon wafer part 3, thus eliminateting what is called 'waiting time'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and is particularly suitable for using a vapor phase growth layer.

[0002]

2. Description of the Related Art A conventional MOS type semiconductor device has a method of forming an element isolation region on a silicon semiconductor substrate by a selective oxidation method and forming an element region such as a MOS type transistor or a capacitor on the exposed semiconductor substrate. There is. On the other hand, as MOS type semiconductor devices become finer and faster,
There is a limit in such a method, and other structures and methods are considered. As one of the countermeasures, after element isolation by the selective oxidation method, a single crystal silicon film is deposited on the exposed silicon portion and a polycrystalline silicon film is deposited on the insulating film by the vapor phase growth method to form elements such as MOS transistors. A method has been devised.

[0003]

After element isolation by the selective oxidation method, single crystal silicon is grown on the silicon substrate and polycrystalline silicon is grown on the insulating layer by the vapor phase growth method, and the element is placed on the silicon substrate. The growth process becomes important. For example, when a silicon film is deposited and grown on the semiconductor substrate after element isolation by the SiH ₄ / H ₂ system, a difference occurs in the film thickness of the single crystal silicon and the film thickness of the polycrystalline silicon on the insulator layer (SiO ₂ ). It becomes thin on the object layer. The reason for this is, as shown in Fig. 6, the time dependence of the grown film thickness.
This is because there is a time (waiting time) during which growth does not occur immediately after the start of growth in the growth on the insulating layer. This results in a difference in the grown film thickness between the silicon and the insulating layer.
In particular, in order to perform the above-mentioned vapor phase growth for miniaturization and speedup of a semiconductor element, a thin film is required as a growth film thickness, so that the difference in the growth film thickness tends to be remarkable. When the difference in the grown film thickness between the single crystal part and the polycrystal part is caused, a step is generated in this part, which causes a defect when a semiconductor element is formed. Therefore, it is necessary to make the grown film thickness uniform. .

As a particularly remarkable phenomenon in thin film growth,
Since the grain growth is likely to occur in the growth mode of the polycrystalline silicon of the insulating layer, there is a problem that unevenness is formed and a semiconductor element cannot be formed.

The present invention has been made under such circumstances, and an object of the present invention is to make the growth film thickness uniform when growing polycrystalline silicon and single crystal silicon at the same time by a vapor phase growth method.

[0006]

In a method of forming a vapor phase growth thin film on an insulating layer and a semiconductor substrate surface exposed between the insulating layers, a step of forming a damaged layer on at least the insulating layer, and thereafter Polycrystalline film on the insulator,
The vapor phase growth method according to the present invention is characterized by the step of forming a single crystal film on the semiconductor substrate exposed between the insulating layers.

Further, CF ₄ , C ₃ F ₈ , CCl ₄ , SF
₆ and a point of forming the damaged layer by reactive ion etching or dry etching with a plasma containing fluoride such as XeF ₄ or chloride, and also silicon,
It is also characterized in that it is performed by an ion implantation method using one of germanium, argon, nitrogen, oxygen, neon, boron, phosphorus and arsenic.

Furthermore, in a vapor phase growth method in which a vapor phase growth layer is simultaneously formed on at least two surfaces made of different materials, at least one of the materials is damaged or defective on the surface of the vapor phase growth layer. Another feature is that a vapor phase growth layer is formed later.

[0009]

As described above, in order to simultaneously grow polycrystalline silicon on the insulating layer and silicon single crystal on the exposed semiconductor substrate, vapor phase growth is performed after damaging both the insulating layer and the exposed semiconductor substrate. Adopt a method.

The term "damage" means damage to the insulating layer and damage to the single crystal or disorder of the crystal. As a means for giving damage, etching of CF ₄ , C ₃ F ₈ , CCl ₄ , SF ₆ or the like is used. Anisotropic reactive etching, isotropic etching, or Si, Ar, O ₂ ,
There is ion implantation using N ₂ , B, P, As, and Sb.

[0011]

EXAMPLE A first example using a selective oxide film will be described. That is, a (100) Si mirror-finished wafer 1 of 150 mm Φ is coated with 2000 Å of selective oxide film (SiO ₂ ) 2 using silicon nitride as a mask (see FIG. 1), and then silicon nitride is CF ₄ + O 2. Remove by isotropic etching with ₂ . As a result, after exposing the Si wafer portion 3, the Si wafer portion 3 and the selective oxide film 2 are subjected to anisotropic reactive etching (RIE: Reactive) using CF ₄ + H _2.
Damage layer 4 by e Ion Etching)
(X mark) is formed (see FIG. 2). Further, as shown in FIG. 3, S is formed by a photolithography process and isotropic etching.
The damaged layer on the i-wafer portion 3 is removed to 0.2 μm-
A 2 μm opening 5 is provided, and the damage layer 4 is left only in the selective oxide film 2.

Furthermore, 150 mm which has undergone such a process
The (100) Si mirror-finished wafer 1 of Φ was treated with a dilute HF solution of 1: 200 for 30 seconds and then washed with running water, and then placed in a vapor phase growth apparatus and heated to 900 ° C. in an H ₂ atmosphere to obtain SiH. _{4 A} vapor phase growth layer was deposited on the Si wafer opening 5 and the damage layer 4 of the selective oxide film 2 for 10 minutes, 20 minutes, 30 minutes and 40 minutes in 0.5% to obtain a single crystal layer 6 and a polycrystal layer. Layer 7 was formed (see Figure 4) and evaluated.

A second embodiment 10 ^{1 2} cm at an acceleration voltage of 100Kev by ion implantation using a B ⁺ in place of ion etching such as RIE in the first embodiment ^{- 2,} 1
^{0 1 3 cm - 2, 10} 1 4 cm - from the implanted under ^second condition, installed in the vapor phase growth apparatus 10 minutes. And 900 ° C
The temperature was raised to the H ₂ atmosphere and the vapor phase growth layers were deposited in SiH ₄ 0.5% for 10 minutes and evaluated.

The third embodiment is 1:20 in the first embodiment.
The treatment time with the dilute HF solution of 0 was 30 seconds for 1 minute, 2 minutes, and 4 minutes, and after each step of washing with flowing water, the apparatus was installed in the vapor phase growth apparatus and then heated to 900 ° C. in an H ₂ atmosphere to raise SiH ₄ 0.5 %
The vapor phase growth layers were deposited in each for 10 minutes and evaluated.

The fourth embodiment is (100) S of 150 mmΦ.
The i-mirror surface wafer 1 is covered with a selective oxide film (SiO ₂ ) 2 using silicon nitride as a mask for element isolation, and then silicon nitride is removed by isotropic etching with CF ₄ + O ₂ . As a result, after exposing the Si wafer portion 3,
A damage layer 4 (marked with X) is formed on the selective oxide film 2 by anisotropic reactive etching using CF ₄ + H ₂ (see FIG. 2). Further, as shown in FIG. 3, the damaged layer of the Si wafer portion 3 is removed by a photolithography process and isotropic etching to form an opening 5 of 0.2 μm to 2 μm, and the damaged layer 4 is formed only on the selective oxide film 2. leave. In order to remove the damaged layer on the Si wafer portion 3, in this embodiment, the Si wafer portion 3 is etched to 100 angstroms with a solution of choline / H ₂ O ₂ / H ₂ O. Further, after a treatment step with a dilute HF solution of 1: 200 for 30 seconds and a washing step with running water, after installing in a vapor phase growth apparatus, the temperature was raised to an H ₂ atmosphere at 900 ° C. and SiH ₄ 0.5%.
The vapor phase growth layer 6 was deposited and evaluated for 10 minutes.

In Comparative Example 1, the following vapor phase growth layers were used. That is, after forming the damage layer 4 by RIE in Example 4, the Si wafer portion 3 was not etched by the solution of choline / H ₂ O ₂ / H ₂ O, and the Si wafer portion 3 was placed in a vapor phase growth apparatus and the temperature was set to 900 ° C. The temperature was raised to an H ₂ atmosphere and the vapor phase growth layer 6 was deposited for 10 minutes in SiH ₄ 0.5% and evaluated. As Comparative Example 2, the opening 5 is formed without forming the damage layer 4 after the selective oxide film 2 is formed in Example 1.
After the formation, the vapor phase growth layer deposited under the same conditions was evaluated.

Of the above Examples 1 to 4 and Comparative Examples 1 and 2, the time dependence of the thickness of the vapor phase growth layer obtained by Example 1 is shown in FIG. 5, and that of Comparative Example 2 is shown. Revealed in 6. 5 and 6, the vertical axis indicates the growth layer thickness and the horizontal axis indicates time (
Min), the circle in the figure indicates the Si wafer part 3,
The triangular mark indicates that the vapor phase growth layer is deposited on the selective oxide film 2, and the growth layer thickness is the Si wafer portion 3 at 20 minutes.
It is an arbitrary value with the upper slope set to 1. In FIG. 5, S
Single crystal layer 6 and selective oxide film 2 deposited on i-wafer portion 3
The thickness of the growth layer of the upper polycrystalline layer 7 shows almost the same value when the damage layer 4 is formed by anisotropic etching and isotropic etching, whereas in FIG. Although the slopes indicating the speeds are almost equal in the single crystal layer 6 and the polycrystalline layer 7, there is a waiting time during which the growth of the polycrystalline layer 7, that is, the selective oxide film 2 does not grow immediately after the start of growth. This is the basis for the significant difference.

However, by forming the damage layer 4, the surface of the selective oxide film is roughened and becomes a deposition point of silicon during vapor phase growth, and the deposition is accelerated to deposit the polycrystalline layer 7.
Growth begins without waiting.

Next, the dependence of the deposited / grown layer of Example 2 on the amount of ion implantation was clarified in FIG. The vertical axis of the figure shows the thickness of the growth layer, and the horizontal axis shows the amount of ion implantation. The thickness of the growth layer is 1 with the thickness of the single crystal layer 6 deposited on the Si wafer portion 3 being 1. The conditions are 900 ° C: 20 minutes and Si
10 minutes in H ₄ 0.5%.

As is clear from this figure, the thickness of the single crystal layer 6 deposited on the Si wafer portion 3 is such that the ion implantation amount is 1
^{0 1 3 cm - 2, 10} 1 4 cm - 10 1 2 cm with respect to equal ² conditions ^- has become the ² bit thin, the amount of damage is less than in the case more or ion implantation amount is small . Therefore, the point of precipitation is considered to be small, and it can be assumed that the growth is delayed immediately after the start of growth.

The results obtained by Example 3 are shown in FIG. There is no difference in the thickness between the single crystal layer 6 and the polycrystalline layer 7 when the treatment time with the dilute HF solution is 30 seconds, 1 minute and 2 minutes, while 4
The thickness of the deposited / grown layer is the same as that when the damage 4 is not given on the selective oxide film 2. This is because the damage layer 4 formed is removed when the treatment with the diluted HF solution is long.

If the damaged layer 4 is removed before vapor phase growth in this way, the effect of the present invention is lost. Example 4 is an example of a process similar to the actual formation of a semiconductor element. In this example, after the element isolation by the selective oxidation method, the Si wafer portion 3
Then, the damage layer 4 was formed on the selective oxide film 2 by the RIE method.

Moreover, the damage layer 4 formed on the Si wafer portion 3 is thinly etched with an alkaline solution to remove the damage layer 4 only on the Si wafer portion 3. However, with this alkaline solution, damages overlapping the selective oxide film 2 are caused. Layer 4 cannot be removed.

Further, in Comparative Example 1, the alkaline solution treatment was not carried out, and vapor phase growth was performed with the damaged layer 4 formed on the Si wafer portion 3 left, and the single crystal layer 6 which was both vapor phase growth layers.
There is almost no difference between the polycrystalline layer 7 and the polycrystalline layer 7, and the thickness is uniformly deposited and grown.

However, when the crystallinity of the single crystal layer 6 was evaluated by the selective etching method / microscope, the one obtained in Example 4 was
While defects such as stacking faults is observed Comparative Example 1 due to the 10 ⁴ ~10 ⁵ cm ^{- 2} degree of defects is observed defects due damage layer 4 of the single crystal layer 6 the surface occurs.

In this embodiment, the RIE method and the isotropic dry etching using CF ₄ are used.
_The same damage layer 4 can be formed by using an etching gas such as CCl ₄ or SF ₆ other than ₄ .

Further, in the ion implantation method used in the present invention, Si, N ₂ , O ₂ and Ar which do not affect the characteristics of the semiconductor device are used.
Alternatively, the damage layer 4 is formed only on the selective oxide film 2, whereas when the Si wafer portion 3 is simultaneously ion-implanted, the ions that are restricted by the characteristics of the semiconductor element such as the conductivity type are as follows. That is, B, P, Sb, As and the like. Further, although the selective oxide film 2 is exemplified in this embodiment, BPSG, PSG, Si ₃ N ₄ or the like can be applied, and a thin film having a vapor phase growth layer thickness of up to 5000 angstrom is formed. Is effective for. This is because it is considered that when the thickness becomes thicker, the difference between the single crystal layer 6 and the polycrystalline layer 7 becomes smaller in proportion to the thickness of the growth layer, which does not cause a big problem.

[0028]

As described above, when the vapor phase growth layer is simultaneously deposited and grown on the insulating film and the semiconductor substrate, the conventional technique is used.
When there was a large variation in the thickness of the vapor phase growth layer between the two in order to obtain a thin film of 0 angstrom, it was 100%, whereas when the present invention was applied, it was almost 5%. As a result, it becomes possible to vapor-deposit polycrystalline silicon and single crystal silicon at the same time after element isolation, and to easily form a semiconductor element thereon.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing the manufacturing process of the semiconductor element, following FIG. 1;

FIG. 3 is a diagram showing the manufacturing process of the semiconductor element, following FIG. 2;

FIG. 4 is a diagram showing the manufacturing process of the semiconductor element, following FIG. 3;

5 is a diagram showing the time dependence of the thickness of the vapor phase growth layer obtained in Example 1. FIG.

6 is a diagram showing the time dependence of the thickness of the vapor phase growth layer obtained in Comparative Example 2. FIG.

FIG. 7 is a diagram showing the ion implantation dose dependency of a vapor phase growth layer according to Example 2.

FIG. 8 is a diagram showing a treatment time dependency of a vapor phase growth layer with a dilute HF solution.

[Explanation of symbols]

 1: Silicon semiconductor substrate, 2: Selective oxide film, 3: Silicon wafer part, 4: Damage layer, 5: Opening part, 6: Single crystal layer, 7: Polycrystalline layer.

Claims (4)

[Claims] 1. A method of forming a vapor phase thin film on an insulating layer and on a surface of a semiconductor substrate exposed between the insulating layers, comprising the steps of forming a damage layer at least on the insulating layer, and then forming the insulating layer. And a single crystal film on the semiconductor substrate exposed between the insulating layers. 2. The damaged layer is formed by reactive ion etching or dry etching using a plasma containing fluoride or chloride such as CF ₄ , C ₃ F ₈ , CCl ₄ , SF ₆ and XeF _4. The vapor deposition method according to claim 1, characterized in that 3. The vapor phase growth method according to claim 1, which is performed by an ion implantation method using one or more of silicon, germanium, argon, nitrogen, oxygen, neon, boron, phosphorus and arsenic. 4. A vapor phase growth method for simultaneously forming a vapor phase growth layer on a surface made of at least two different materials, wherein the vapor phase growth layer is formed after at least one surface of the material is damaged or defective. 2. The vapor phase growth method according to claim 1, wherein