JPH0827810B2 - Delay simulator - Google Patents

Description

The present invention relates to functional verification of a logic circuit, and more particularly to a delay simulator used for timing verification.

[Conventional technology]

Conventionally, this kind of delay simulator gives a uniform roundness to all the elements that consider that there is no rounding in the rounding of the input waveform to the primitive elements (step function).
Methods such as giving the time constant of CR were adopted. Moreover, in the conventional delay simulator, a logical behavior description is required for the primitive element. Therefore, an element for which a logical behavior description can be defined and delay information can be defined for a pin can be regarded as a primitive element.

Here, the primitive element is an element located in the lowest layer in the unit of the circuit diagram information for performing the delay analysis. For example, in FIG. 5, E, F, G, H are primitive elements. In addition, the delay information refers to a parameter of the delay value calculation formula. For example, when a 2-input NAND gate is used as a primitive element, the delay value calculation formula is T = aX + bY + c
Assuming that X is a load capacitance and Y is a rounding of the input waveform, a, b, and c are parameters of the delay value calculation formula. Depending on the simulator, the delay value itself may be given, but if a = b = 0 and c is considered to be the delay value, it can be regarded as a parameter of the delay value calculation formula. A set of delay information is called a delay library.

FIG. 6 is an example of a logical operation description of a 2-input NAND gate.

[Problems to be Solved by the Invention]

 The conventional delay simulator has the following problems.

When the rounding of the input waveform becomes large, the accuracy of the delay value for the primitive element tends to deteriorate significantly,
It also affects the accuracy of the simulator as a whole.

A logical behavioral description that defines the relationship between the input value and the output value is required, which requires a lot of preparation man-hours, and also makes it difficult to create the logical behavioral description itself in the case of an element having a plurality of functions.

It is necessary to measure the delay information based on the logical behavior description, but it is necessary to measure the delay information at least by the number of items of the logical behavior description, and a lot of man-hours are required to create the delay library.

[Means for solving the problem]

The delay simulator of the present invention executes so-called static delay analysis that does not require test patterns. The delay analysis method uses a conventional technique such as a critical path analysis method or setup / hold timing verification.

In the present invention, when the delay value of a certain primitive element is calculated, the information about the rounding of the waveform output from the preceding primitive element is stored, so that the rounding of the input waveform can be considered.

Further, in the present invention, regarding the primitive element, even if the number of output pins is 1 or the total number of output pins and bidirectional pins is 2 or more, all output pins and bidirectional pins can be regarded as having equivalent delay information. The logical behavior description was made unnecessary by providing a restriction that the delay information can be defined regardless of the logical value. However, in order to improve the accuracy of the delay simulation, it is defined whether the output value is in-phase or inverted with respect to the input value.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The delay value calculation method of the primitive element 2 is given by Trise = Ar * X + Br * Y + Cr (rising delay) Tfall = Af * X + Br * Y + Cf (falling delay), and Ar, Br, Cr, Af, Bf, Cf are It is assumed that it is given as delay information. Ar, Br, Cr, Af, Bf, Cf
Can be calculated from the delay value measured by changing the load capacitance and the rounding of the input waveform using a circuit simulator such as SPICE. Here, X is the load capacitance value and Y is the rounding of the input waveform. Y is represented by, for example, the time required to reach a constant voltage.

The waveform 3 output by the primitive element 1 is shown in FIG. At this time, the output voltage is VDD on the primitive element 1 side.
Memorize the time Tr10 that reaches 10% and the time Tr50 that reaches 50%. When calculating the delay value of the primitive element 2, the rounding Y of the input waveform is given by Y = (Tr50−Tr10) / (0.4 × VDD). In the present embodiment, the case where the input waveform of the primitive element 2 rises is shown, but in the case of the falling edge, the time Tf90 when the output voltage reaches 90% of VDD and the time Tf50 when it reaches 50% on the primitive element 1 side. By storing it, it is possible to similarly obtain the rounding of the input waveform by Y = (Tf90−Tf50) / (0.4 × VDD).

FIG. 3 is an example of a primitive element set according to the present invention. The primitive element consists of:

Inverter (element 6) NAND gate (element 7,8,9) NOR gate (element 10,11,12) Composite gate (element 13,14) Clocked inverter (element 15) Unidirectional transfer gate (element 16) Bidirectional Transfer Gate (Element 17) Generally, in a logic circuit having a CMOS structure, all functional elements can be described by a combination of the above seven primitive elements.

In this example, ~ has one output pin,
Has two bidirectional pins. However, it can be used as a primitive element, considering that the two bidirectional pins have equal delay information.

Each primitive element is given a parameter of the delay value calculation formula measured in advance according to the transistor size, and also information about whether the output value is inverted with respect to the input value. In this example, ~ is inversion, and is in phase.

FIG. 4 shows another example of the primitive element set in the present invention. The feature of this example is that functions such as FF are also included as primitives. The elements of the primitive element set are shown below.

Inverter (element 18) NAND gate (element 19,20,21) NOR gate (element 22,23,24) Composite gate (element 25,26) Clocked inverter (element 27) Unidirectional transfer gate (element 28) Bidirectional Transfer gate (element 29) Buffer (element 30) AND gate (element 31) OR gate (element 32) Tri-state buffer (element 33) Flip-flop (element 34) Multiplexer (element 35) Register (element 36) ROM / RAM (Element 37) In the primitive element, the flip-flop is considered to have the same delay information Q. Similarly, since it is considered that all output pins and bidirectional pins have the same delay information, the logical operation description becomes unnecessary.

〔The invention's effect〕

As described above, according to the present invention, since the roundness of the waveform output by the preceding stage primitive element can be used as the rounding of the input waveform in the delay value calculation of the primitive element, the accuracy of the delay value in the delay simulation is improved. Since there is no need for a logical behavior description, it has the effect of reducing the man-hours required to create a delay library.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of a method for calculating a rounding of an input waveform, FIG. 3 is a diagram showing an example of a primitive element set of the present invention, and FIG. FIG. 5 is a diagram showing another example of the primitive element set of the present invention, FIG. 5 is an explanatory diagram of the primitive elements in the circuit hierarchy, and FIG. 6 is a diagram showing an example of the logical operation description of the 2-input NAND gate. 1 ... Pre-stage primitive element, 2 ... Primitive element whose delay value is to be calculated, 3 ... Waveform output by primitive element 1, 4 ... Waveform output by primitive element 2, 5 ... Load capacity of primitive element A virtual capacity symbol showing the total of 6 ... Inverter, 7 ...
2-input NAND gate, 8 ... 3-input NAND gate, 9 ... 4
Input NAND gate, 10 …… 2-input NOR gate, 11 …… 3-input NOR gate, 12 …… 4-input NOR gate, 13 …… Composite gate, 14 …… Composite gate, 15 …… Clocked inverter,
16 …… unidirectional transfer gate, 17 …… bidirectional transfer gate, 18 …… inverter, 19 …… 2-input NAND gate, 20 …… 3-input NAND gate, 21 …… 4-input NAND gate, 22 …… 2-input NOR gate, 23 …… 3-input NOR gate,
24 …… 4-input NOR gate, 25 …… compound gate, 26 …… compound gate, 27 …… clocked inverter, 28 …… unidirectional transfer gate, 29 …… bidirectional transfer gate, 30 …… buffer, 31… … 2-input AND gate, 32 ……
2-input OR gate, 33 ... Tri-state buffer, 34 ...
… Flip-flops, 35 …… Multiplexers, 36 …… Registers, 37 …… RAM, 38 …… 2-input NAND gates, 39 ……
Logical operation description of 2-input NAND gate.

Claims (2)

[Claims] 1. When a calculation formula for calculating a delay value of a primitive element has a period depending on a rounding of an input waveform,
A delay simulator having a function of preliminarily storing information on the rounding of the waveform output from the preceding primitive element and using it as information on the rounding of the input waveform when calculating the delay value of the primitive element. 2. The delay simulator according to claim 1, wherein a logical behavior description is not required by providing the primitive element with a definition of whether the output value is in-phase or inverted with respect to the input value.