JPH08275210A - Composite signal check device - Google Patents

Abstract

PURPOSE: To attain a function check of a composite signal inexpensively with high accuracy by separating the composite signal into a horizontal synchronizing signal, a vertical synchronizing signal and an analog RGB signal and conducting a synchronizing signal output timing check, a dot check of the analog RGB signal and gradation check. CONSTITUTION: An output timing of a horizontal synchronizing signal and a vertical synchronizing signal among signals separated by a decoder 37 is measured by a synchronizing signal check circuit 10. An analog RGB signal 23 is subjected to dot measurement by an analog comparator 13 with a write clock 34 and its gradation is measured by an A/D converter 17 with a 2nd asynchronous sampling clock 33. A central processing unit section 1 compares the measured value with the expected value to discriminate the acceptance of the measured value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite signal inspection apparatus, and more particularly _, to a composite signal output from a video signal generator, after separating and extracting an analog RGB signal from the composite signal.
The present invention relates to a composite signal inspection device for making a pass / fail judgment for each dot by its own dot clock.

[0002]

Conventional composite signal inspection apparatus inputs the pattern designating signal to the video signal generator to be _inspected, a composite signal corresponding to the pattern designation signal is output from the video signal generator, on a cathode ray tube The operator visually judges whether or not the image displayed on the CRT and the image to be formed by the composite signal generated by the video signal generator according to the pattern designation signal match with each other. The two-dimensional camera captures an image, performs image processing, and determines whether or not the video signal generator is operating normally depending on whether or not it matches the expected value.

FIG. ₆ shows
_Is a block diagram showing _{a conventional} color television signal inspecting apparatus _{shown in JP-A-62-239785.} This conventional _example, when the composite signal as typified by NTSC signals _are entered, and a matrix 210 for converting an analog RGB signal. Matrix 2
The analog _RGB signal output from 10 is supplied to two sets of comparators 212 1 _and 214 2. The comparator 212 receives _the minimum voltage as a reference signal, when _the voltage _of the analog _{RGB signal} is lower than the minimum value voltage, outputs a logical 1. Comparator 2
14 receives _the maximum value voltage as a reference signal, the analog
_{If the} voltage of the _RGB signal is higher than the minimum value voltage, logic 1 is output. The output of the comparator 212, 214 _is supplied to the OR gate 216, a range error device signals _{is output. Modulator} 218 modulates the composite signal in response to the range error signal, to visually prominently, displayed on the monitor 220. Alternatively, the monitor 220 is provided with a color shutter that responds to the range error signal and modulates the composite signal by a predetermined method, and the range error signal is directly supplied to the monitor 220 and displayed. The operator looks at the image displayed on the monitor 220 and determines _the quality of the composite signal.

[0004]

In this conventional example, it is only checked whether or not the input composite signal can be reproduced as a video signal, and if the composite signal has a defect, the cause thereof is specified. Is difficult to do. Further, when inspecting the intermediate gradation color, the maximum value and the minimum value of the comparator must be reset for each gradation color, which is not suitable for the intermediate gradation color inspection.

In the conventional composite signal inspection apparatus, the composite signal inspection of the video signal generator employs a method of displaying an image on a cathode ray tube and visually checking the quality of the operator, and the inspection quality varies depending on the operator. There was a drawback. In particular, minute image defects and gradation defects in multicolor, high-resolution video signals cannot be discerned by human eyes, and even defects that can be discriminated can be overlooked in the inspection environment where several hundred units per day. There is a possibility of

Further, in a method of capturing an image with a two-dimensional camera, performing image processing, comparing with an expected value, and judging pass / fail,
When inspecting multi-color, high-resolution images, a high-resolution two-dimensional camera, a high sampling rate, a high-resolution A / D converter and a high-speed data processing circuit around it are required. The converter has the drawback that it cannot be inspected due to lack of high-speed performance, or that even if the inspection can be realized, the inspection device becomes very expensive.

Further, when a defect is detected, it is difficult to distinguish whether the defect is caused by the video signal generator or the cathode ray tube.

[0008]

SUMMARY OF THE INVENTION The composite signal of the present invention.
No. inspection device is the output of the video signal generator to be inspected
The brightness signal that indicates the brightness, the color signal that expresses the color, and the
position_andA composite containing a sync signal to indicate timing.
Analog RGB signal_,Horizontal sync signal_AndVertical
Decoder that separates and converts into sync signal, Input from outside
One screen according to the pattern designation signal, which is the digital amount
1st pattern where the entire surface is a white pattern with the highest brightness
Composite signal_,Alternate maximum and minimum for each dot
The second pattern of composite signals,_and,
One horizontal line has the same gradation, and each horizontal line has a floor
Outputs the composite signal of the third pattern with changed key
An identification signal that specifies the video signal generator,
_AndPrescribes the pattern designation signal corresponding to this
Pattern designation values to be stored in association with each other in advance.
A turn storage means and the pattern designation value are temporarily stored
Register and above_decoderOf the horizontal sync signal output by
Ruth width P_WThe standard value of P_W± H_D%, And the measurement accuracy is T
_M1%, (P_W× (H_D/ 100) x (T_M1/
100))^-1H_zGenerates the first sampling clock of
And a first sampling clock generation circuit for
The horizontal synchronization signal and vertical with the sampling clock of
The first service that samples the sync signal into a digital value.
The sampling means and the first sampling means
Input the sampling result and input the horizontal sync signal and vertical sync signal.
Pulse width, period,_{The above}Horizontal, vertical
_{The analog RGB signal is output after the sync signal is output.
It is time to go}Back porch time
_{, And before the end of output of analog RGB signals
It is the time until the synchronization signal is output.}Front porch
Sync signal that extracts time and counts the number of digital pulses
Measured by the check circuit and the sync signal check circuit
A standard value storage means for storing the standard value of an item and a write / read control
Measurement of the sync signal check circuit controlled by a control signal
The value is written and stored at the first sampling clock.
A first storage means,_MinuteIt is controlled by the frequency designation signal
The horizontal sync signal output from the decoder is used as input
A times the frequency of the period signal_{(A is a natural number)}Has the frequency of
The dot clock with the phase synchronized with the horizontal sync signal._KuOccurs
Dot clock generator circuit that outputs the
Tsu_KuVariable delay means for delaying
_{Output the threshold for maximum and the threshold for minimum
A threshold voltage source, The above}With a threshold for maximum_{The above}minimum value
Set a threshold for_AThe analog comparator and the
A, N depending on the frequency designation signal
_{(N is a natural number not larger than a)}Enter the value of
The output of the analog comparator is added a / N at a time to obtain a /
An averaging circuit for averaging with N and receiving the dot clock
And input the values of a and N by the frequency division designation signal.
Output the write clock with the frequency divided by N / a.
And the frequency divider that is controlled by the write / read control signal.
Receives the output of the averaging circuit and writes at the write clock
A second storage means of 2 bits × N layers for performing only storage;
The third pattern output from the video signal generator
Water of analog RGB signal which decoded composite signal
When displaying analog RGB signal data during flat 1-line scanning
T between_DAnd the measurement accuracy is T_M2%, (T_D×
(T_M2/ 100)^-1H_zSecond sampling clock of
A second sampling clock generation circuit for generating
The clock of the second sampling clock generation circuit is received.
And the third pattern output from the video signal generator.
Analog RGB decoded from composite signal
Convert signal to at least 12-bit digital output signal
Controlled by the A / D converter and the write / read control signal
The digital output signal of the A / D converter is captured
3 by the storage means and the switching control signal
Select one of the RGB signals to select the analog comparator
Data output to either the data converter or the A / D converter
And a test command including the identification signal is input,
The reset signal is output to the sync signal check circuit,
The corresponding first pattern specified value from the pattern storage means
Read and store in the register and the video
Outputting the pattern designation signal to a signal generator,
Analog that decodes the composite signal of the pattern
Output RGB signals and measure with the sync signal check circuit.
The counted value is read from the first storage means, and the standard
If the value read from the value storage means is “good”,
The horizontal sync signal and the vertical sync signal cycle.
The frequency division designation signal to the dot clock generation circuit.
Force to generate the dot clock, and the switch
What_,Select one of the analog RGB signals_ShiThe analog
Select the comparator side_{The above}Issue a switching control signal
And again from the pattern storage means.
When the specified turn value is read and stored in the register,
Outputs the pattern designation signal to the video signal generator.
The second pattern composite for each dot.
Output the analog RGB signal that is the decoded signal and
One screen image
_{The measurement result was written in the second storage means.}After the above
The read-in pattern is read out from the storage means of 2.
Ana that has decoded the composite signal of the second pattern.
When it matches the log RGB signal, it is judged as “good”, and in that case
Before selecting the A / D converter side as the switching device
Switch_controlOutputs a signal, and the pattern storage means
The corresponding third pattern designation value is read from the register
And remember it_{The above}Putter on video signal generator
Output a command signal to output the composite of the third pattern
Output the signal, and only the test time corresponding to one image screen
After that, the gradation value for each horizontal line is read from the third storage means.
When it is read and within the specified value, it is judged as “good”,
The first storage means, the second storage means, and the third storage
Judgment in the middle of making a pass / fail judgment of the value stored in the method
While controlling so that the test is stopped when the status becomes "bad"
And a central processing unit.

[0009]

The present invention will be described in detail with reference to the drawings.

FIG. 1 shows _{an NTSC composite signal inspection apparatus} as an embodiment of the composite signal inspection apparatus of the present invention.
FIG.

[0011] Composite signal inspection apparatus of this _embodiment,
An NTSC decoder 37 for separating an NTSC composite signal 38 output from the video signal generator 6 into an analog RGB signal 23 _{, a} horizontal synchronizing signal 20 and a vertical synchronizing signal 22.
When a pattern designating signal 19 which is a digital amount inputted from the outside is inputted, the NTSC composite signal of the first pattern in which all dots on one screen have the highest white brightness according to the pattern designating signal 19 and each dot The second pattern of NTS, in which the maximum white brightness and the minimum brightness alternate with each other
C composite signal and N of the third pattern in which one horizontal line has the same gradation and the gradation is changed for each horizontal line
And it outputs the TSC composite _signal, a video signal generator 6 identification signal and said corresponding pattern designation signal 19 pattern memory means 2 stored in advance in association with the pattern designation value that defines _the to be examined, the pattern a register 4 for storing a specified value temporarily when the video signal generator 6 is P _W ± H _D% the standard value of the pulse width P _W of the horizontal synchronizing signal 20 to be output, and the measurement accuracy and _M1% T,
_{Asynchronous (PW x (HD / 100) x (TM1 / 10)
0)) A} first sampling clock generation circuit 8 for generating a first sampling clock 21 of ^-1 _Hz, and a horizontal synchronization signal 20 and a vertical synchronization signal 22 are sampled by the first sampling clock 21 and converted into digital values. First sampling means 9 for inputting the sampling result, and the vertical synchronizing signal 22 and the horizontal synchronizing signal 20 by inputting the sampling results, the respective periods 100, 104 _{(FIG. 2)} , the pulse width 101,
105 _{(FIG. 2)} , a sync signal check for extracting back porch times 102 and 106 _{(FIG. 2)} and front porch times 103 and 107 _{(FIG. 2)} , which are time differences from the analog RGB signal 23, and counting the number of pulses of a digital value. Circuit 10
If, _vertical synchronizing signal 22 and horizontal synchronizing signal 20, each period, a pulse width, a standard value storing means 3 for storing a standard value of the back porch time and front porch time is the time difference between the analog RGB signal 23, write first frequency dividing designation signal storage means 11, is output from _Chuo processor 1 is controlled by a write read control signal 24 for the write stores the measurement value of the synchronous signal check circuit 10 in the first sampling clock 21 25 dot clock 26A a multiple of the frequency of the _horizontal synchronization signal 20 as an input horizontal synchronizing signal 20 outputted from the controlled _N TSC decoder 37 _{(a is a natural number)} combined phase with the horizontal synchronization signal 20 has a frequency of the
A dot clock generating circuit 7 for generating and outputting a dot clock 26B arbitrarily delaying the _de Ttokurokku 26 _A
A variable delay unit 15 for outputting a _Anal log comparator 13 which sets the threshold 29 of the threshold 28 and a minimum value for the maximum value inputs an output of the _switching Rikae 12, division designation signal 25 By a _, N _{(N is a natural number not larger than a)}
Enter the value of
_{By doing this, one dot of analog RGB signal 23
Determine the number of samples for each sample, and hit one sampled dot}
A an averaging circuit 35 receives the dot clock 26 _B, by further dividing designation signal 25 _{to average the data of Ri,}
A frequency divider 36 which inputs a value of N and outputs a write clock 34 whose frequency is divided by N / a times;
A threshold voltage source 5 that outputs a threshold 28 for the maximum value and a threshold 29 for the minimum value _{set by the threshold voltage setting signal 30,} and an averaging controlled by the write / read control signal 24. the _comparator output 31 and 32 at a speed converting circuit and a write clock 34 configured with a shift register of m stages receiving the output of the circuit 35 serial - parallel conversion, a write memory at a writing speed of 1 / m of the write clock frequency a second storage unit 14 of the 2-bit × N layer for outputs from the _video signal generator _6, and decodes the NTSC composite signal with different tone for each horizontal line one line horizontal as same gradation It is asynchronous _when the data display time T _D of the analog RGB signal during one horizontal line scanning of the analog RGB signal and the measurement accuracy is T _M2 % (T
A second sampling clock generation circuit 16 for generating a _{D × (T M2 / 100)} -1 second sampling clock ₃₃ H _z, output from the _pattern memory means _2, one line horizontal as same gradation _the analog RGB _signals with different tone for each horizontal line the second sampling clock
_{2 bits or more than the resolution that can be inspected by}
An A / D converter 17 for converting the _high digital signal, a third storage means 18 for capturing digital _signals of the write and read control signal is controlled by the 24 _A / D converter 17, the switching control signal _27, NTSC Input the analog RGB signal 23 output from the decoder 37 and select one of them.
A switching unit 12 to be output to either the _comparator 13 and the _{A /} D converter 17, the test command including an identification signal for specifying the video signal generator 6 is inputted, the reset signal to the _synchronous signal check circuit 10 outputs, then reads the first pattern designation value corresponding the _pattern memory means 2
Outputting a pattern designation signal 19 to the video signal generator 6 with is stored in _register 4, one screen full dot to output the NTSC composite signal of the first pattern as a white maximum brightness, counted by the synchronization signal check circuit 10 and value read out from the first storage means 11, _Tadashi if Kakuchi is compared to the value read from the memory means 3 "good", the horizontal synchronizing signal and a vertical synchronizing signal _dividing designation signal period based on the Two
5 generates a dot clock 26 _A and outputs the _de Ttokurokku generating circuit 7, analog RGB to the _switching Rikae 12
Select one of the signals, and outputs a switching control signal 27 for selecting _Anal log comparator 13 side, reads the second pattern specified values corresponding the _pattern memory means 2 again
Outputting a pattern designation signal 19 to the video signal generator 6 with is stored in _{register 4,} the analog RGB signals 2
3 After outputting the NTSC composite signal of the second pattern such that each of the dots becomes the maximum value and the minimum value alternately for each dot, and after the corresponding test time for one screen of the image has passed,
When the pattern read from the second storage means 14 is read out and coincides with the second pattern designation value, it is determined as “good”,
_Les outputs a switching control signal 27 for selecting the _{A /} D converter 17 side to the _switching Rikae 12 if "good", reads a third pattern specifying values corresponding the _pattern memory means 2
Outputting a pattern designation signal 19 to the video signal generator 6 with is stored in the register _4, the third pattern _with different tone for each horizontal line in the horizontal one line _{of analog RGB signal} as the same tone NTSC Composite to output a signal, after passing through only the test time corresponding to the image one frame, reads out the tone value for each horizontal line from the third storage unit _18, determines that "good" _when they are within a predetermined value Shi
_The central processing unit 1 stops the test when a "defective" is made in the middle of these judgments.

FIG. 2 is a timing chart showing the input / output relationship of the NTSC decoder ₃₇ for separating the NTSC composite signal into a horizontal synchronizing signal, a vertical synchronizing signal, and an analog RGB signal, and the test items measured by the synchronizing signal check circuit 10. Is.

FIG. 3 shows an analog RGB signal and actually a second one.
3 shows the relationship with the data written in the storage means 14.

FIG. 4 shows the relationship between the analog RGB signal obtained by decoding the third pattern NTSC composite signal and the second sampling clock.

The NTS of the present invention shown below in FIG.
The operation of the embodiment of the C composite signal inspection apparatus will be described.

When a test command including an identification signal designating the video signal generator 6 to be inspected is input from the outside,
The central processing unit 1 outputs a reset signal to the sync signal check circuit ₁₀ .

The composite video signal 38 output from the video signal generator ₆ is separated by the NTSC decoder 37 into an analog RGB signal 23, a horizontal synchronizing signal 20 and a vertical synchronizing signal 22.

The first sampling means 9 has a frequency {P _W obtained from the first sampling clock generating circuit 8.
× (H _D / 100) × (T _M1 / 100)} ⁻¹ H _z first
The horizontal synchronizing signal 20 and the vertical synchronizing signal 22 obtained from _the NTSC decoder 37 are sampled using the sampling clock 21 of FIG.

The synchronization signal check circuit 10 initialized by the reset signal inputs the sampling result.
_2, the periods 100 and 104, the pulse widths 101 and 105 of the horizontal synchronizing signal and the vertical synchronizing signal, the back porch 102 and 106, and the front porch 10 _{as shown in FIG.}
3, 107 are extracted and the number of pulses of the digital value is counted.

[0020] The counting results _are written and stored in the first sampling clock 21 in the first storage means 11 controlled by the write and read control signals 24.

Thereafter, the central processing unit 1 reads out the result counted by the synchronization signal check circuit 10 from the first storage means 11, and further refers to the standard value storage means 3 to refer to the standard value corresponding to the inputted identification signal. Is read out, both are compared and judged, and only when all are “good”, the frequency division designating signal 25 corresponding to the identification signal is outputted to the dot clock generating circuit 7, and the second pattern designating means 2 is designated from the pattern storing means 2. The value is read and stored in the register 4. Then, the pattern designating signal 19 corresponding to the second pattern designating value is output to the video signal generator 6, and the analog RGB signals 23 each have the second pattern NT in which the maximum value and the minimum value are alternately set for each dot.
Output SC composite signal. Switcher 1
The switching control signal 27 for selecting one of the analog RGB signals for 2 and inputting the analog RGB signal to the analog comparator 13 is output, and the threshold voltage source 5 outputs the maximum value threshold value and the minimum value threshold value. A threshold voltage setting signal 30 that specifies is output.

The threshold voltage source 5 outputs the maximum value threshold value 28 and the minimum value threshold value 29 to the analog comparator 13 in accordance with the threshold voltage setting signal 30.

The analog comparator 13 is composed of a maximum value comparator output 31 and a minimum value comparator output 32 for the analog RGB signal obtained from the switch 12 with reference to the maximum value threshold value 28 and the minimum value threshold value 29. The converted digital value is converted into a 2-bit digital value _{(FIG. 3)} .

The dot clock generation circuit 7 is controlled by the frequency division designation signal 25, receives the horizontal synchronizing signal ₂₀ output from the video signal generator 6, and has a frequency a times the frequency of the horizontal synchronizing signal _{20. Dots} phase-locked to ₂₀
A clock _26A is generated, and through the variable delay means 15,
A dot clock 26 _B in phase with the analog RGB signal obtained by decoding the NTSC composite signal of the second pattern is generated.

The frequency divider 36 receives the dot clock 26 _B , inputs the values of a and N by the frequency division designating signal 25, and outputs the write clock 34 whose frequency is divided by N / a.

The second storage means 14 controlled by the write / read control signal 24 has a storage capacity of 2 bits × N layers,
The 2-bit digital output data obtained as _{described later} from the averaging circuit 35 is received, and the analog comparator output is serial-parallel converted by a speed conversion circuit composed of m stages of shift registers and a write clock 34,
Data is written and stored at a writing speed of 1 / m of _the frequency of the writing clock ₃₄ .

N is a number such that a dot clock having a frequency N times the frequency of the horizontal synchronizing signal 20 can sample once for each dot. Therefore, for example, a = 1
000, N = 1000, the second pattern NT
The maximum value _{and the} minimum value of the analog RGB signal obtained by decoding the SC composite signal are sampled once, and the averaging circuit 35 does not perform averaging.
Write in the storage means 14 of. a = 2000, N = 1000
In the case of, the maximum value _{and the} minimum value of the analog RGB signal obtained by decoding the NTSC composite signal of the second pattern are sampled twice, and the averaging circuit 35 decodes the NTSC composite signal of the second pattern. The maximum value _{and the} minimum value of the analog RGB signal thus obtained are averaged so that there is one data each, and then written _in the second storage means 14.

When A / D converting an NTSC composite signal, a color subcarrier frequency of 3.579545 MHz is used.
It is necessary to sample with a dot clock that is more than double. Therefore, the dot clock frequency capable of A / D converting the NTSC composite signal is about 15 MHz or more, and the horizontal synchronizing signal frequency is 15.734264 KHz, so that the value of N is 910 or more.

After the output data for one screen of the image is stored in the second storage means 14, the central processing unit 1 reads this content, compares it with the second pattern _{designating value,} and if it matches, it is judged as "good". To do. The switching control signal 27 for selecting the A / D converter 17 is output to the switch 12 only when it is determined that the analog RBG signal for each color is “good”, and the pattern storage means 2 outputs the third pattern designation value. together it is stored in the read register _4, and outputs the pattern designation signal 19 corresponding to the third pattern specified value to the video signal generator 6 changes the gradation for each horizontal line one line horizontal as same gradation The third pattern NTSC composite signal is output.

The A / D converter 17 has a resolution of 12 bits or more, a second sampling clock of the second sampling clock frequency obtained from the generator _{16 (T D × (T M2} / 100) -1 H z With 33
_{Decoder separates the third pattern composite signal
The} analog RGB signal is A / D converted _{(FIG. 4)} .

The third storage means 18 controlled by the write / read control signal 24 receives the digital output of the A / D converter 17 and writes / stores it by the second sampling clock 33.

After storing the output data for one screen of the image in the third storage means 18, the central processing unit 1 reads the gradation value for each horizontal line, and when it is within the predetermined value, it is "good".
To determine.

In the pass / fail judgment performed by the central processing unit 1, if the test result is "defective", the test is stopped at that point.

FIG. ₅ shows another embodiment of the composite signal inspection apparatus of the present invention.

Personal computer 6 to be inspected
When a test command including an identification signal designating A is input from the outside, the central processing unit 1 outputs to the selector 12A a selection signal 41 for selecting the analog RGB signal 40 output from the personal computer. Figure 1 otherwise
The operation is exactly the same as the embodiment shown in FIG. With such a configuration, the inspection of not only the video signal generator that outputs the composite signal but also the equipment that outputs the analog RGB signal represented by a personal computer is 1
It is possible with a stand.

[0036]

As described above, the present invention separates _and converts a composite signal output from a video signal generator to be inspected into a horizontal synchronizing signal, a vertical synchronizing signal and an analog RGB signal, and measures output timing. occurrence of the analog RGB signal for each dot, by performing a series of steps carved and gradation test analog RGB signals, compared to the conventional inspection apparatus, _an effect of enabling more inexpensive and accurate inspection _Play .

Further, a dot clock generating circuit for independently generating a dot clock having a frequency a times the clock extracted from the horizontal synchronizing signal and phase-synchronized with the horizontal synchronizing signal is provided, and the value of a is arbitrarily set. Thus, the analog RGB signal inspection can be electrically performed with the number of dots which is equal to or higher than the resolution of the composite signal, and the composite signal can be inspected in detail.

Further, since the function inspection of the composite signal can be performed directly by the electric inspection without passing through the cathode ray tube, there is an effect that the function inspection of the video signal itself can be performed and the inspection quality can be kept constant.

In order to inspect an analog RGB signal obtained by separating _and converting an NTSC composite signal for high resolution television with a conventional NTSC composite signal inspection device,
A high-resolution two-dimensional camera and a high sampling speed / multi-resolution A / D converter were required, but the composite signal inspection apparatus of the present invention uses an analog RGB converter that uses a low-cost analog comparator that can operate at high speed. Since the signal is converted into a 2-bit digital signal, and the required storage capacity is 2 bits × the number of pixels of one screen, which is smaller than the conventional one, the inspection apparatus can be realized at a low price. In order to use an A / D converter that has a high resolution but a relatively low sampling speed in the gradation test, the inspection pattern of the composite signal adopts a pattern in which one scanning line has the same gradation and the gradation is changed for each scanning line. By doing so, the inspection device can be realized at a low price.

[0040] _Composite signal detection unit of the invention, _co
The composite signal is separated into a horizontal synchronizing signal, a vertical synchronizing signal, and an analog RGB signal, and the output function of each signal is inspected. Therefore, by inserting the Switching _Operation place device at the subsequent stage of _{the decoder,} and the composite signal used in the television or the like by simply switching the video signal format to be output of the test products, as used in a personal computer or the like Originally, the CR and the video signals are separated
T Ru _can perform function tests (Cathode Ray Tube) interface signal in one.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing the input / output relationship of the NTSC decoder and the test items for which the synchronization signal check circuit 10 measures time.

FIG. 3 is a timing chart showing a relationship between analog RGB signals and data actually written in the second storage means.

FIG. 4 is a diagram showing a relationship between an analog RGB signal obtained by decoding a third pattern composite signal and a second sampling clock.

FIG. ₅ is a block diagram showing another embodiment of the present invention.

FIG. ₆ is a block diagram showing a conventional example.

[Explanation of symbols]  1 Central Processing Unit 2 Pattern Storage Means 3 Standard Value Storage Means 4 Registers 5 Threshold Voltage Source 6 Video Signal Generator 7 Dot Clock Generation Circuit 8 First Sampling Clock Generation Circuit 9 First Sampling Means 10 Sync signal check circuit 11 First storage means 12 Switcher 13 Analog comparator 14 Second storage means 15 Variable delay means 16 Second sampling clock generation circuit 17 A / D converter 18 Third storage means 35 Averaging circuit 36 frequency divider 37 NTSC decoder

Claims (3)

[Claims] 1. Output of a video signal generator to be inspected
The brightness signal that indicates the brightness, the color signal that expresses the color, and the
position_andA composite containing a sync signal to indicate timing.
Analog RGB signal_,Horizontal sync signal_AndVertical
Decoder that separates and converts into sync signal,  Pattern designation signal, which is a digital amount input from the outside
Depending on, the entire screen becomes a white pattern with the highest brightness
First pattern composite signal_,Alternate for each dot
Second pattern composite with maximum and minimum values in
signal,_and,Horizontal 1 line is the same gradation and each horizontal
The third pattern composite with different gradation for each line
Identification for specifying the video signal generator that outputs a video signal
signal,_AndThe pattern designating signal corresponding to this
The pattern specified value that defines
A pattern storage unit, a register for temporarily storing the pattern designation value, and_decoderPulse width P of horizontal sync signal output by_Wof
Standard value is P_W± H_D%, And the measurement accuracy is T_M1% And
(P_W× (H_D/ 100) x (T_M1/ 100))^-1
H_zTo generate a first sampling clock of
A sampling clock generation circuit, and the horizontal synchronization signal and the horizontal synchronization signal with the first sampling clock.
And the vertical sync signal are sampled into digital values
The first sampling means and the sampling result by the first sampling means
Input the horizontal sync signal, vertical sync signal pulse width, frequency
Period,_{The above}Horizontal, vertical
_{The analog RGB signal is output after the sync signal is output.
It is time to go}Back porch time
_{, And before the end of output of analog RGB signals
It is the time until the synchronization signal is output.}Front porch
Sync signal that extracts time and counts the number of digital pulses
Enter the standard values of the check circuit and the items measured by the sync signal check circuit.
Memorized standard value storage means and the synchronization signal check controlled by a write / read control signal
Write the measured value of the circuit with the first sampling clock
First storage means for storing inclusively,_Minute Water output from the decoder controlled by the cycle designation signal
Input the flat sync signal and multiply the frequency of the horizontal sync signal by a
_{(A is a natural number)}Has a frequency of and is in phase with the horizontal sync signal
Dot clock_KuTo generate and output
Clock generation circuit and the dot clock_KuVariable delay means for delaying_{Output the threshold for maximum and the threshold for minimum
A threshold voltage source, The above} With a threshold for maximum_{The above}Set threshold for minimum value
Fixed_ABy the analog comparator and the frequency division designation signal, a, N
_{(N is a natural number not larger than a)}Enter the value of
The output of the analog comparator is added a / N at a time to obtain a /
An averaging circuit for averaging by N, receiving the dot clock,
Input the values of a and N, and divide the frequency by N / a.
A frequency divider for outputting a write clock; and an averaging circuit controlled by the write / read control signal.
Receives output and writes and stores at the write clock 2
Bit × N layer of second storage means, and the third pattern output from the video signal generator
Analog RGB signal decoded from the composite signal of
Data table of analog RGB signals during horizontal 1-line scanning
Show time T_DAnd the measurement accuracy is T_M2%, (T
_D× (T_M2/ 100)^-1H_zSecond sampling of
Second sampling clock generating circuit for generating clock
And a clock of the second sampling clock generation circuit
And the third signal output from the video signal generator.
Analog RG that decodes the composite signal of the turn
Convert the B signal to a digital output signal of at least 12 bits
An A / D converter for converting, and the A / D converter controlled by the write / read control signal
Third storage means for fetching the digital output signal of, and which of the analog RGB signals is selected by the switching control signal
Select one of them to select the analog comparator and the A / D
A switch that outputs to either of the converters, and when a test command including the identification signal is input, the synchronization
The reset signal is output to the signal check circuit, and the pattern
Read the corresponding first pattern designation value from the memory means
Then, it is stored in the register and the video signal is generated.
The pattern designating signal is output to the living body, and the first pattern is output.
Analog RGB decoded from composite signal
A signal was output and counted by the sync signal check circuit.
A value is read from the first storage means, and the standard value is stored.
If it is “good” compared to the value read from the means,
Based on the cycle of the horizontal sync signal and the vertical sync signal,
Output the frequency division designation signal to the dot clock generation circuit
Generate the dot clock and send it to the switch_,Before
Select one of the analog RGB signals_ShiThe analog computer
Select the pallet side_{The above}Outputs a switching control signal,
Again the corresponding second pattern from the pattern storage means
Read the specified value and store it in the register
Output the pattern designation signal to the video signal generator,
The composite signal of the second pattern for each dot
Outputs the decoded analog RGB signal and outputs one image
Area_{The measurement result was written in the second storage means.}rear,
The captured pattern is read from the second storage means.
Then, the composite signal of the second pattern is decoded
When it matches the analog RGB signal, it is judged as “good”,
In that case, select the A / D converter side for the switch
Switch to_controlOutputs a signal and stores the pattern
Reading the corresponding third pattern designation value from the means;
And store it in a register_{The above}To video signal generator
A pattern designating signal is output to output the component of the third pattern.
At the time of the test corresponding to one screen of the image by outputting the git signal
After a lapse of time, from the third storage means, the floor for each horizontal line
Read the adjustment value and judge it as “good” when it is within the specified value.
The first storage means, the second storage means and the third storage means.
While making a pass / fail judgment of the value stored in the storage means
Control to stop the test when the judgment is "bad"
And a central processing unit that
Signal inspection equipment. Wherein the output horizontal synchronizing signal of the personal computer to be inspected, in a CRT (Cathode Ray Tube) interface signals including a vertical synchronizing signal _and an analog RGB signal, an analog RGB signal ₍₄₀₎ Decoder (37 ) Output analog RGB signal (42), and the central processing unit (1) outputs a selection signal (4
In response to 1), one of the analog RGB signals (40 _, 41) is selected and the analog RGB signal (23) is turned off.
By a selector (12A) for outputting the modified unit (12) _Ri, equipment for outputting a composite signal as representative of the inspected object on a television, the synchronous signal and the video signal as represented by a personal computer composite signal inspection apparatus according to claim 1, _feature to switch the device to output the separated analog RGB signals. 3. The composite signal is NTSC (Na
(Comparative National Television System Committee) composite signal inspection apparatus according to claim 1 or 2, which is a composite signal.