JPH08275060A - Light receiving element circuit, light receiving element circuit array and method for configuring the light receiving element circuit - Google Patents

Abstract

PURPOSE: To obtain the light receiving element circuit having a sensitivity variable function able to vary the light receiving sensitivity and to control the polarity of an output from each light receiving element in which values of bipolar outputs of the light receiving element circuit are made in matching with each other. CONSTITUTION: A potential of a light receiving element 3 is led to a MOS transistor(TR) 15 in a noninverting output circuit and a MOS TR 17 in an inverting output circuit to control each conductance of each circuit. When a selector switch 16 is closed, a current flows from a power supply voltage terminal 6 to an output terminal 5 (noninverting output), and when a selector switch 18 is closed, a current flows from the output terminal 5 to a ground terminal 4 (inverting output). The potential of the output terminal 5 is a difference of a threshold voltage between the MOS TRs 15, 17 and the design of the noninverting output circuit and the inverting output circuit is easily designed to make values of output currents from both the circuits equal to each other by specifying a potential of the output terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light receiving element circuit having a plurality of light receiving element circuits, in particular, a circuit configuration of a light receiving element circuit which allows a control circuit to change the light receiving sensitivity of the light receiving element and to increase the sensitivity. The present invention relates to a method of configuring a circuit array and a light receiving element circuit.

[0002]

2. Description of the Related Art In a conventional image processing device, a signal obtained from a light receiving element is processed by a computer in the processing device,
The desired image processing was performed with a huge amount of calculation time.
Therefore, reduction in image processing time has been expected. On the other hand, some image processing requires a negative polarity as a signal, and using a negative power source as a control power source of a light receiving element to obtain a signal of a negative polarity is costly and accurate. was difficult. Against this background, a light receiving element circuit that has a sensitivity variable function that can control the sensitivity of the light receiving element by providing a control circuit in the light receiving element and further control the polarity is a light receiving element that solves the above problems. It is expected as an element circuit.

A conventional light receiving element circuit having a variable sensitivity function will be described below. FIG. 14 shows Japanese Patent Application No. 6-125.
It is a block diagram of the light receiving element circuit described in No. 132. In the figure, the output potential from the light receiving element 103 is, through a tri-state switch 104, a pMOS transistor 105 having one end connected to a terminal of a power supply voltage 109, or one end grounded.
Is connected to the gate terminal of the nMOS transistor 106 connected to the terminal.

The operation of the conventional light receiving element circuit configured as described above will be described. First, one end is grounded 108
The received light receiving element 103 is biased by the bias terminal 101 through the reset switch MOS transistor 102. Next, after turning off the reset switch 102, the charges accumulated in the light receiving element 103 due to the incidence of light are input to the gate terminal of the pMOS transistor 105 or the nMOS transistor 106 through the tristate switch 104. Each gate is biased according to this charge amount (potential) and outputs a current to the output terminal 107. At this time, if the tri-state switch 104 is turned on to the pMOS transistor 105 side, the current flows in the direction in which the nMOS transistor 10 is turned on.
If it is turned on to the 6 side, it can be controlled in the flowing direction. As described above, the potential of the light receiving element is converted into a current,
It has become possible to control the size and polarity of the light receiving element circuit, which can control the sensitivity to positive and negative without using a negative power source. Also, in the non-inverting output circuit, a low gate
In order to make it easy to take out the current value even at the gate voltage, and in the inverting output circuit, to make it easy to take out the current value even at the high gate voltage, pMOS and nMOS transistors are provided respectively.

[0005]

In the light receiving element circuit, since the image processing is performed in the subsequent stage by using the output signal information obtained from the circuit, the same light intensity, that is, the same light receiving element potential is inverted. It is necessary to equalize the absolute values of the non-inverted outputs so that the output of one light receiving element circuit can be calculated or the output of a plurality of light receiving elements can be calculated (calculation between pixels). That is, the inverted and non-inverted outputs must be offset. Because, in a certain light receiving element circuit, when an inverted output signal is selected and when a non-inverted output signal is selected,
This is because calculation between pixels cannot be performed if the signal magnitudes are different.

On the other hand, FIG. 15 shows the light receiving element circuit of FIG.
It is an example in which the magnitudes of the inverted output and the non-inverted output are plotted as a function of the light receiving element potential. Ideally, the two curves should perfectly match as a light-receiving element circuit, but the sizes of both should be very different, and both outputs should match as long as the pMOS and nMOS are used for changes in the light-receiving element potential. I can't let you. Therefore, it can be seen that the cancellation is not successful in this state as it is, that is, the calculation between pixels cannot be performed, and the light receiving element circuit does not have sufficient performance.

As described above, in the conventional light receiving element circuit, the output of the light receiving element can be amplified and the output can be taken out in two ways: inverted and non-inverted. However, since it has the above-mentioned structure, for example, The output current value of the pMOS transistor increases as the gate potential decreases, but the output current value of the nMOS transistor increases as the gate potential increases. Due to the circuit asymmetry and the characteristics of the transistor used, the inverted output Also, there is a problem that the magnitude of the non-inverted output is different. Further, there is no circuit configuration method for making the magnitudes of the inverted and non-inverted outputs equal. Therefore, the accuracy of the calculation between pixels is low, and the light receiving element circuit cannot sufficiently function.

Furthermore, in circuit selection switching using the tri-state switch 104, the potential remains at the gates of the transistors 105 and 106 simply by turning off the switches, so that the tri-state switch 104, the transistor 105 and the tri-state switch. Due to the capacitance between the switch 104 and the transistor 106, the accuracy of the potential given to the gate as the potential of the light receiving element becomes low. Therefore, the tristate switch 104 turns on the transistor 105,
The transistor 105 is set to H and reset, then the transistor 106 is turned on by the tri-state switch 104, the transistor 106 is set to L, and finally reset.
There has been a problem that a complicated reset operation of resetting 03 has to be performed every time charge is accumulated.

The present invention has been made in order to solve the above-mentioned problems, and by specifying the gain coefficient and the threshold voltage of the transistors forming the light receiving element circuit, the same light receiving element potential is obtained. To provide a high-performance light-receiving element circuit in which absolute values of inverted and non-inverted outputs are the same and calculation between pixels such as output cancellation can be performed, and a high-performance light-receiving element having a plurality of the light-receiving element circuits arranged therein. It is an object of the present invention to provide a circuit array and a method for configuring the light receiving element circuit.

It is another object of the present invention to provide a high-performance light receiving element circuit having a large light storage capacity without noise and malfunction in the light receiving element circuit having the same absolute value of inverted and non-inverted outputs.

Another object of the present invention is to provide a selection switch which is simple in operation when selecting an inverting / non-inverting output circuit.

[0012]

According to a first aspect of the present invention, there is provided a light receiving element circuit, wherein a light receiving element and a signal obtained by converting a potential of the light receiving element into a current are controlled and output to the outside. In the light-receiving element circuit having a control circuit for controlling the voltage on the substrate, the control circuit includes a MOS transistor that controls a current value flowing from the power supply voltage terminal to the output terminal according to the potential of the light-receiving element (non-inverting output circuit). And a circuit configured by a MOS transistor (inversion output circuit) configured to control a current value flowing from the output terminal to the ground terminal according to the potential of the light receiving element, the MOS forming the light receiving element circuit. At least one of the gain coefficient and the threshold voltage of the transistor, the potential of the output terminal, and the potential of the power supply voltage has a large output signal from the non-inverting output circuit and the inverting output circuit. It is has specified value to be equal to the same light receiving element potential.

The light receiving element circuit according to the invention of claim 2 is
According to the first aspect of the present invention, it is defined that the MOS transistor has a specified gain coefficient controlled by the ratio of the gate width and the gate length of the transistor.

The light receiving element circuit according to the invention of claim 3 is
3. The circuit according to claim 1, wherein the circuit including a MOS transistor that controls a current value according to the potential of the light receiving element is nM.
It defines that an OS or pMOS transistor is provided.

The light receiving element circuit according to the invention of claim 4 is
According to any one of claims 1 to 3, the non-inverting output circuit and the inverting output circuit are provided with a switching transistor for selecting each circuit.

A light receiving element circuit according to the invention of claim 5 is
The non-inverting output circuit and the inverting output circuit according to claim 4, wherein the MOS transistor that controls the current value according to the potential of the light receiving element and the switching transistor that selects each circuit are connected in series. It specifies that.

The light receiving element circuit according to the invention of claim 6 is
In any one of Claim 1 thru | or 5, it prescribed | regulated that the difference of the MOS transistor threshold voltage which controls a current value by the electric potential of the non-inverting output circuit and the light receiving element with which the inverting output circuit was provided was made into the electric potential of an output terminal. To do.

The light receiving element circuit according to the invention of claim 7 is
In any one of claims 1 to 6, it is specified that the potential of the power supply voltage terminal is twice the potential of the output terminal.

A light receiving element circuit according to the invention of claim 8 is
8. The non-inverting output circuit and the inverting output circuit according to claim 7, wherein the current value is controlled by the potential of the light receiving element.
The S transistor and the switching transistor for selecting each circuit are arranged to be relatively equal in potential.

A light receiving element circuit according to the invention of claim 9 is
9. The non-inverting output circuit and the inverting output circuit according to claim 8, wherein a switching transistor for selecting each circuit is on a lower potential side than a MOS transistor for controlling a current value by a potential of a light receiving element provided in both circuits. It is defined as being placed in.

According to a tenth aspect of the invention, there is provided a light receiving element circuit according to any one of the seventh to ninth aspects, wherein the non-inverting output circuit and the inverting output circuit are provided with a MOS for controlling a current value according to the potential of the light receiving element. It defines that the transistors and the switching transistors for selecting the respective circuits have the same gain coefficient between the non-inverting output circuit and the inverting output circuit, respectively.

According to an eleventh aspect of the present invention, there is provided a light receiving element circuit according to any one of the first to fifth aspects, wherein in the non-inverting output circuit, a MOS transistor for controlling a current value according to a power supply voltage terminal and a potential of the light receiving element. It defines that a diode-connected transistor is arranged in series between the two.

According to a twelfth aspect of the present invention, in the light receiving element circuit according to the eleventh aspect, in the inverting circuit, the switching transistor for selecting the inverting circuit has a higher potential than the MOS transistor for controlling the current value by the potential of the light receiving element. It defines that it is placed on the side.

According to a thirteenth aspect of the present invention, there is provided a light receiving element circuit according to the eleventh or twelfth aspect, wherein the threshold voltage of the diode-connected transistor is a threshold value of a MOS transistor whose current value is controlled by the potential of the light receiving element provided in the inverting circuit. It specifies that the voltage or the threshold voltage of the MOS transistor that controls the current value is matched with the potential of the light receiving element included in the non-inverting circuit.

According to a fourteenth aspect of the present invention, in the light receiving element circuit according to any one of the eleventh to thirteenth aspects, the gain coefficient of the diode-connected transistor and the non-inverting circuit selecting switching transistor constitutes a light receiving element circuit. Is larger than the gain coefficient of any of the transistors.

A light receiving element circuit according to a fifteenth aspect of the present invention is the light receiving element circuit according to any one of the thirteenth to fifteenth aspects, wherein the transistors forming the light receiving element circuit have a gain coefficient ratio with respect to a ratio of current driving capability between the respective transistors. The value defines a transistor having a relation of a ratio of a gate width and a gate length between the transistors.

According to a sixteenth aspect of the invention, there is provided a light receiving element circuit according to any one of the first to fifteenth aspects, wherein the light receiving element is a pn photodiode.

According to a seventeenth aspect of the present invention, in a light receiving element circuit according to the sixteenth aspect, the pn photodiode is provided with an n-type layer formed on a p-type substrate or a p-type layer formed on an n-type substrate. It stipulates the provision.

According to the eighteenth aspect of the invention, in the light receiving element circuit according to the seventeenth aspect, the n-type layer or the p-type layer of the pn photodiode is connected with a switching transistor for resetting the pn photodiode. is there.

A light receiving element circuit according to a nineteenth aspect of the present invention is the light receiving element circuit according to any one of the sixteenth to eighteenth aspects, wherein the doping concentration of the substrate forming the light receiving element and the control circuit is 1 or less.
It is specified to be higher than × 10 ¹³ cm ^{-3 and} lower than 1 × 10 ¹⁶ cm ^-3 .

According to a twentieth aspect of the invention, in the light receiving element circuit according to the nineteenth aspect, the substrate forming the light receiving element and the control circuit is a p-type substrate, and the light receiving element forming portion in the p-type substrate is doped. A light-receiving element comprising a p-type layer having a concentration of 1 × 10 ¹⁵ cm ⁻³ or more and an n-type layer doped therein at a concentration higher than the doping concentration of the p-type layer, or a light-receiving element The substrate forming the control circuit is an n-type substrate, and the light-receiving element forming portion in the n-type substrate is
What defines a light-receiving element comprising an n-type layer having a doping concentration of 1 × 10 ¹⁵ cm ^-3 or more and a p-type layer doped therein at a concentration higher than that of the n-type layer Is.

According to a twenty-first aspect of the present invention, in the light-receiving element circuit according to any one of the first to twentieth aspects, a capacitor for accumulating an output from the light-receiving element is connected in parallel between the light-receiving element and the control circuit. It is a thing.

A light receiving element circuit according to a twenty-second aspect of the present invention is the light receiving element circuit according to any one of the first to twenty-first aspects, wherein a metal film is provided in a portion forming the transistor circuit.

According to a twenty-third aspect of the present invention, there is provided a light-receiving element circuit array in which the light-receiving element circuits according to any one of the first to twenty-second aspects are arranged in a one-dimensional or two-dimensional array.

According to a twenty-fourth aspect of the invention, in the light-receiving element circuit array according to the twenty-third aspect, the switch terminals of the light-receiving element circuits arranged on one horizontal line of the plurality of light-receiving element circuits arranged in an array are common. It is defined that the output terminals of the light receiving element circuits arranged on one line in the vertical direction are common.

A light receiving element circuit array according to a twenty-fifth aspect of the present invention is the light receiving element circuit according to the twenty-third or twenty-fourth aspect, wherein a substrate contact for grounding a substrate forming the light receiving element circuit is connected to a ground line in the light receiving element circuit. It defines that it is provided for each.

According to a twenty-sixth aspect of the present invention, there is provided a method of configuring a light-receiving element circuit, which includes a light-receiving element and a control circuit for controlling the magnitude and polarity of a signal obtained by converting the potential of the light-receiving element into a current and outputting the signal to the outside. A light-receiving element circuit including and on a substrate,
The control circuit controls the current value flowing from the power supply voltage terminal to the output terminal by the potential of the light receiving element (non-inverting output circuit), and the potential from the light receiving element causes the current to flow from the output terminal to the ground terminal. In a method of forming a light receiving element circuit including a circuit (inversion output circuit) including a MOS transistor for controlling a current value, a signal to be output by selecting the non-inversion output circuit, that is, a current flowing into an output terminal And a second step of measuring or calculating the magnitude of a current output from a signal to be output to the outside by selecting the inverting output circuit, that is, the magnitude of a current flowing from the output terminal.
A third step of comparing the results of the first and second steps, and control so that the magnitudes of the output signals from the non-inverting output circuit and the inverting output circuit are the same for the same light-receiving element potential. A fourth step of controlling at least one of a gain coefficient and a threshold voltage of a MOS transistor forming a circuit, a potential of an output terminal, and a potential of a power supply voltage.

According to a twenty-seventh aspect of the present invention, there is provided a method of forming a light-receiving element circuit according to the twenty-sixth aspect, wherein the gain coefficient of the MOS transistor constituting the control circuit is selected and set in the fourth step. After the fourth step, there is provided a fifth step of controlling the gain coefficient of the set MOS transistor by the ratio of the gate width and the gate length of each MOS transistor.

According to a twenty-eighth aspect of the present invention, there is provided a method of forming a light-receiving element circuit according to the twenty-seventh aspect, wherein in the fifth step, the ratio of the ratio of the gate width and the gate length between the transistors to be set is set to It defines that the gain coefficient of the MOS transistor is controlled so that the ratio of the gain coefficient to the ratio of the drivability is set.

[0040]

Since the light-receiving element circuit according to claim 1 of the present invention includes the MOS transistor having a specific gain coefficient or threshold voltage, the output terminal whose potential is specified, and the power supply voltage whose potential is specified, the non-inverting The absolute value of the output of the inverting output circuit can be controlled by the gain coefficient. Further, by providing the non-inverting / inverting output circuit, the polarity of the signal can be controlled without the negative power supply.

According to the second aspect of the present invention, in the light receiving element circuit of the first aspect, the gain coefficient of the MOS transistor is controlled by the ratio of the gate width and the gate length of the transistor.
The gain coefficient of the MOS transistor can be easily controlled.

According to a third aspect of the present invention, there is provided a light receiving element circuit according to the first or second aspect, in which an n-type circuit is provided with a MOS transistor for controlling a current value according to the potential of the light receiving element.
Since a MOS or pMOS transistor is used, if the same type of transistor as other transistors is used, the circuit can be simplified by the same process and simple steps. Further, since it is not necessary to form two p and n wells in one pixel (one light receiving element circuit), the size of the pixel can be reduced. Further, in the case of an nMOS, when an element whose potential increases as the light is irradiated is used as the light receiving element,
If the output current is 0 when light is not emitted, the output current increases as the incident light becomes stronger.
In the case of an OS, when an element whose potential decreases as light is irradiated is used as the light receiving element, the output current is 0 if the light is not irradiated, and the output current increases as the incident light becomes stronger. can do.

According to a fourth aspect of the present invention, in the light receiving element circuit according to any one of the first to third aspects, the non-inverting output circuit and the inverting output circuit are provided with switching transistors for selecting respective circuits. The direction of can be easily selected from the outside. Further, since each circuit can be selected by the conduction of each circuit by opening / closing the switching transistor, the potential of the light receiving element is not affected, and a complicated reset operation is unnecessary. Further, by controlling the gate voltage of the switching transistor in an analog manner, the output current value for a constant light receiving element potential can be changed in an analog manner.

According to a fifth aspect of the present invention, in the light receiving element circuit according to the fourth aspect, in the non-inverting output circuit and the inverting output circuit, a transistor for controlling a current value by a potential of the light receiving element in each circuit and a switching transistor. By connecting the two in series, the circuit becomes simple and the light receiving element circuit can be made small.

A light receiving element circuit according to a sixth aspect of the present invention is the MOS transistor according to any one of the first to fifth aspects, wherein the current value is controlled by the potentials of the light receiving elements provided in the non-inverting output circuit and the inverting output circuit. Since the difference between the threshold voltages is taken as the potential of the output terminal, the transistor that constitutes the circuit that controls the current value that flows from the power supply voltage terminal to the output terminal by the light receiving element potential and the current that flows from the output terminal to the ground terminal by the light receiving element potential Since the transistors forming the circuit for controlling the value can be arranged so as to be electrically equivalent to each other, it becomes easy to design the outputs of both circuits to have the same magnitude.

According to a seventh aspect of the present invention, in the light receiving element circuit according to any one of the first to sixth aspects, the potential of the power supply voltage terminal is twice the potential of the output terminal. The potential difference from the voltage terminal to the output terminal is equal to the potential difference from the output terminal to the ground terminal of the inverting output circuit, so that both circuits are electrically equivalent and the magnitude of the output from both circuits is the same. It becomes easy to design such that

According to an eighth aspect of the present invention, there is provided a light receiving element circuit according to the seventh aspect, wherein the transistor for controlling the current value by the potential of the light receiving element and the switching transistor have the same positional relationship on the high potential side and the low potential side. Since they are arranged in such a manner, both circuits can have an electrically symmetrical structure, and it becomes easy to design so that the magnitudes of the outputs from both circuits are the same.

According to a ninth aspect of the present invention, in the light receiving element circuit according to the eighth aspect, in the non-inverting circuit and the inverting circuit, the switching transistor is set to a lower potential side than the transistor whose current value is controlled by the potential of the light receiving element. By arranging them, the linearity is improved because the fluctuation of the drain voltage is smaller than that when the switching transistor is placed on the high potential side.

According to a tenth aspect of the present invention, the light receiving element circuit is
10. The non-inverting circuit and the inverting circuit according to claim 7, wherein the MOS transistors controlling the current value according to the light receiving element potential have the same gain coefficient, and the switching transistors selecting the respective circuits have the same gain coefficient. Therefore, both circuits are electrically equivalent, and the magnitudes of the outputs from both circuits can be matched and controlled.

According to the eleventh aspect of the present invention, the light receiving element circuit is
The transistor connected in diode is arranged between the power supply voltage terminal of the non-inverting output circuit and the MOS transistor whose current value is controlled by the light receiving element potential according to any one of claims 1 to 5. Even if the potential of the power supply voltage terminal is substantially lowered and the potential of the power supply voltage terminal is sufficiently higher than that of the output terminal, it is easy to control so that the output from the non-inverting / inverting output circuit is the same. become.

According to a twelfth aspect of the present invention, the light receiving element circuit is
12. The non-inverting circuit according to claim 11, wherein the switching transistor is placed on the higher potential side than the transistor whose current value is controlled by the potential of the light receiving element included in the inverting circuit. The linear characteristics can be made the same, and the outputs of both circuits can be designed to have the same magnitude.

According to a thirteenth aspect of the present invention, the light receiving element circuit is
13. The MOS according to claim 11 or 12, wherein the threshold voltage of the diode-connected transistor is controlled by a light receiving element potential provided in an inverting circuit or a non-inverting circuit.
Since it matches with one of the threshold voltage of the transistor,
The transistor has two threshold voltages, and the number of steps in the manufacturing process can be reduced.

According to a fourteenth aspect of the present invention, the light receiving element circuit is
14. The gain coefficient of a diode-connected transistor and a switching transistor for selecting a non-inverting circuit according to claim 11, wherein the non-inverting circuit has more transistors than the inverting circuit because the output is reduced. Is set to be larger than the gain coefficient of any other transistor forming the light receiving element circuit, which facilitates the design so that the magnitude of the output from the non-inverting / inverting output circuit can be made the same.

According to a fifteenth aspect of the present invention, the light receiving element circuit is
16. The transistor constituting the light receiving element circuit according to claim 13, wherein a value of a gain coefficient ratio with respect to a ratio of current driving capability between the transistors is equal to a ratio of a gate width / gate length ratio between the transistors. Since the transistors have the following relationship, it is possible to compensate for the difference in current driving capability between the MOS transistors due to different threshold voltages or fluctuations in threshold voltage due to the substrate bias effect.

According to a sixteenth aspect of the present invention, there is provided a light receiving element circuit comprising:
In any one of Claims 1 to 15, since the light receiving element is a pn photodiode, photocharges are easily generated, and a simple light receiving element can be used to form a circuit configuration.

According to a seventeenth aspect of the present invention, the light receiving element circuit is
The nMOS of the control circuit unit according to claim 16, wherein the pn photodiode has an n-type layer formed on a p-type substrate or has a p-type layer formed on an n-type substrate.
Alternatively, it can be formed in the same process as the pMOS transistor.

The light receiving element circuit according to claim 18 of the present invention is
In the seventeenth aspect, since the switching transistor for resetting the pn photodiode is connected to the n-type layer or the p-type layer of the pn photodiode, the light storage time of the pn photodiode can be controlled.

The light receiving element circuit according to claim 19 of the present invention is
The doping concentration of the substrate forming the light receiving element and the control circuit according to any one of claims 16 to 18 is set to 1x10.
^{Since it} is higher than ¹³ cm ^{-3 and} lower than 1 × 10 ¹⁶ cm ^-3 , the doping concentration of the substrate is sufficiently low and the substrate bias effect can be ignored. Therefore, the electrical equivalence of the non-inverting and inverting output circuits of the control circuit Can be maintained.

The light receiving element circuit according to claim 20 of the present invention is
20. The substrate for forming the light receiving element and the control circuit according to claim 19, wherein the light receiving element forming portion in the p type substrate is a p type layer having a doping concentration of 1 × 10 ¹⁵ cm ⁻³ or more. It is a light-receiving element provided with an n-type layer doped at a concentration higher than the doping concentration of the p-type layer therein, or the substrate forming the light-receiving element and the control circuit is n-type.
The n-type substrate having a doping concentration of 1 × 10 ¹⁵ cm ⁻³ or more and a higher concentration than that of the n-type layer. Since the light receiving element includes the p-type layer, the concentration of the portion where the depletion layer spreads in the pn junction is sufficiently high even when the substrate concentration is low, so that the pn junction capacitance can be increased.

According to a twenty-first aspect of the present invention, the light receiving element circuit is
The capacitor for accumulating the output from the light-receiving element is connected in parallel between the light-receiving element and the control circuit according to any one of claims 1 to 20, so that photo-charges can be accumulated in the capacitor as well, so that the substrate concentration is reduced. Even when the capacitance is low and the pn junction capacitance is small, the storage capacitance in the light receiving element portion including the capacitor can be increased.

The light receiving element circuit according to claim 22 of the present invention is
In any one of Claims 1 to 21, since a metal film is provided in a portion forming the transistor circuit, light and electromagnetic waves are prevented from entering the transistor circuit by the metal film, so that noise and malfunction of the circuit are prevented. Can be avoided.

According to a twenty-third aspect of the invention, a light-receiving element circuit array is formed by arranging the light-receiving element circuits according to any one of the first to twenty-second aspects in a one-dimensional or two-dimensional array. One-dimensional or two-dimensional light patterns are simultaneously received in parallel, and desired image processing becomes possible.

According to a twenty-fourth aspect of the present invention, in the light-receiving element circuit array according to the twenty-third aspect, the switch terminals of the light-receiving element circuits arranged on one horizontal line of the plurality of light-receiving element circuits arranged in an array are commonly used. Since the output terminals of the light receiving element circuits arranged on one line in the vertical direction are made common, it is possible to take out one-dimensional or two-dimensional light patterns at the same time in parallel and while performing pixel-to-pixel calculation.

According to a twenty-fifth aspect of the present invention, in the light-receiving element circuit array according to the twenty-third or twenty-fourth aspect, a substrate contact is provided for each light-receiving element circuit on a ground line in the plurality of light-receiving element circuits. Even when a large amount of photocharge is generated, the charge escapes from the contact portion to the ground line, and thus it is possible to prevent the noise from flowing into surrounding pixels and causing noise or the like. Further, when the photocharge from the light receiving element overflows, it is prevented from flowing into the surrounding pixels and causing noise or the like.

According to a twenty-sixth aspect of the present invention, there is provided a method of configuring a light receiving element circuit, comprising: a light receiving element; and a control circuit for controlling the magnitude and polarity of a signal obtained by converting the potential of the light receiving element into a current and outputting the signal to the outside. A non-inverting output circuit, wherein the control circuit includes a MOS transistor for controlling the current value flowing from the power supply voltage terminal to the output terminal according to the potential of the light receiving element. And a circuit (inversion output circuit) including a MOS transistor for controlling a current value flowing from an output terminal to a ground terminal according to a potential from the light reception element, the non-inversion output circuit comprising: A first step of measuring or calculating the signal to be selected and output to the outside, that is, the magnitude of the current flowing into the output terminal, and the inverting output circuit being selected and output to the outside A second step of measuring or calculating the magnitude of the current flowing out from the output terminal, that is, the magnitude of the current flowing out of the output terminal, a third step of comparing the results of the first and second steps, and At least one of the gain coefficient and threshold voltage of the MOS transistor forming the control circuit, the potential of the output terminal, and the potential of the power supply voltage so that the magnitudes of the output signals from the inverting output circuit and the inverting output circuit are the same. And a fourth step of controlling the output voltage of the non-inverting / inverting output circuit, the output of the non-inverting / inverting output circuit is the gain coefficient and threshold voltage of the MOS transistor constituting the control circuit, the potential of the output terminal, and the potential of the power supply voltage. Since it can be described by a function of the gain coefficient of the MOS transistor, the output of the non-inverting / inverting output circuit can be controlled by controlling at least one of them. Designed so as to equal the absolute value is facilitated.

According to a twenty-seventh aspect of the present invention, in the method for constructing a light-receiving element circuit according to the twenty-sixth aspect, it is selected and set in the fourth step that the gain coefficient of the MOS transistor constituting the control circuit is selected. After the fourth step, there is provided a fifth step of controlling the set gain coefficient of the MOS transistor by the gate width / gate length ratio of each MOS transistor, and the gain coefficient of the MOS transistor is set to the gate width / gate of the transistor. Since it is controlled by the length ratio, the gain coefficient of the MOS transistor can be easily controlled.

According to a twenty-eighth aspect of the present invention, in the method for constructing a light-receiving element circuit according to the twenty-seventh aspect, in the fifth step, the ratio of the gate width / gate length ratio between the transistors to be set is determined by the current driving capability between the transistors. Since the gain coefficient of the MOS transistor is set so as to be the ratio of the gain coefficient to the ratio of the
The difference in current driving capability between the transistors can be compensated.

[0068]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a circuit configuration for explaining the principle of the present invention. In the figure, the light receiving element 3
The electric potential of M controls the current value flowing from the power supply voltage terminal 6 to the output terminal 5 by the electric potential of the light receiving element (non-inverted output) M
It is guided to the OS transistor circuit 7 and the MOS transistor circuit 8 that controls the current value flowing from the output terminal 5 to the ground terminal 4 (inversion output) by the light receiving element potential.

Next, the operation will be described. First, the light receiving element 3 whose one end is grounded 4 via a substrate contact (not shown) is biased by the bias terminal 1 through the reset switch MOS transistor 2. When electric charges are accumulated in the light receiving element 3 due to the incidence of light, the potential corresponding to the electric charge is inverted and input to the non-inversion output circuits 7 and 8. When the non-inverting output circuit 7 is selected and is output through the circuit, the current flows from the power supply voltage terminal 6 toward the output terminal 5, while the inverting output circuit 8 is selected and passes through the circuit. The current in the case of being output flows out from the output terminal 5 to the ground terminal 4, so that the polarity control is realized. If the bias terminal 1 and the power supply voltage terminal 6 are shared, the area of the light receiving element circuit (pixel) can be reduced.

Here, since the current value from each circuit is controlled by the light receiving element potential, the light receiving element output is amplified and the S / N ratio can be improved.

Since the output circuits 7 and 8 are composed of MOS transistors, the gain coefficient β and the threshold voltage Vth of the MOS transistors forming these circuits are adjusted, and the output terminal potential and the power supply voltage terminal potential are adjusted. By adjusting, the magnitudes of the outputs from the output circuits 7 and 8 can be made the same for the same light receiving element potential. That is, since it is possible to obtain outputs having the same size but opposite directions, it is possible to accurately perform calculation between pixels such as output cancellation.

On the other hand, the output current value I of the MOS transistor
It is represented by (Under certain conditions) I = β / 2 · ( V G -Vth-V S) 2 ··· (1). Here, β is a gain coefficient, V _G is a gate potential of the MOS transistor, Vth is a threshold voltage of the MOS transistor, and V _S is a source potential of the MOS transistor. The gain coefficient β is β = με (ox) / t (ox) · (W / L) (2)
Is represented by Here, μ is the effective surface mobility, ε (ox) is the dielectric constant of the oxide film, and t (ox) is the thickness of the oxide film. That is,
The gain coefficient β of a MOS transistor is determined by the effective surface mobility μ of electrons in the channel, the capacitance ε (ox) / t (ox) of the gate insulator per unit area, and the gate width W / gate length L of the MOS transistor. Since it is a product of the ratio (hereinafter abbreviated as (W / L)), the gain coefficient β can be controlled by manipulating these values. Further, the operation of W / L can be easily controlled by simply determining the sizes of W and L of the transistor at the time of circuit design.

FIG. 2 is a block diagram of a concrete light receiving element circuit showing an embodiment of the present invention. In the figure, a transistor 9 (9a, which controls the current value by the light receiving element potential,
9b), the circuit selection transistor 10 (10a, 10
b) is arranged in the non-inverting and inverting output circuits, respectively. Here, the switching transistor 10 is shown only in somewhere in each circuit, and the arrangement is arbitrary. As described in FIG. 1, the bias terminal 1
If the power supply voltage terminal 6 is shared, the area of the pixel can be reduced.

Next, the operation will be described. First, the light receiving element 3 whose one end is grounded 4 through the substrate contact is biased by the bias terminal 1 through the reset switch MOS transistor 2. Light receiving element 3 by light incidence
When the electric charge is accumulated in, the potential corresponding to the electric charge is input to the transistors 9a and 9b. When the upper switch 10a is turned on, a current controlled by the light receiving element potential flows from the power supply voltage terminal 6 toward the output terminal 5, and when the lower switch 10b is turned on, a current controlled by the light receiving element potential is output terminal. 5 flows to the ground terminal 4. Thereby, control of the polarity is realized from the outside.

Further, since both the inversion circuit and the non-inversion circuit are composed of two transistors 9 and 10, the circuit becomes simple and the pixel can be made small. Further, if the gate voltage of the switching transistor is changed in an analog manner, it becomes possible to change the output current value for a constant light receiving element potential in an analog manner. Further, since the circuit selection switching transistor is arranged in each circuit, it does not affect the potential of the light receiving element and a complicated reset operation is not necessary.

Further, in the equation (1), it can be seen that the output current value I of the MOS transistor is described by V _G , Vth and V _S. As can be seen from FIG. 2, V _G or V _S of the MOS transistor 9 is the potential of the output terminal 5, and if the switching transistor 10 of the non-inverting circuit is arranged at a lower potential position than the MOS transistor 9, the MOS transistor 9 is V _S is the potential of the power supply voltage 6. That is, in the light receiving element circuit, not only the gain coefficient of the MOS transistor that constitutes the circuit but also the threshold voltage and the potential of the output terminal,
By specifying the potential of the power supply voltage, it becomes possible to control the output magnitudes of the non-inverting / inverting circuits to be equal. This enables highly accurate calculation between pixels.

Next, a procedure for matching or controlling the outputs of the non-inverting output circuit and the inverting output circuit will be described. First, an output current when a non-inverted output is selected is measured in a light receiving element circuit including a MOS transistor having a certain β and Vth and a circuit set to an arbitrary power supply voltage VDD and an output terminal potential Vout. Next, the output current when inverting output is selected is measured. From the result of both output current values and the configuration of the control circuit, β of the optimum MOS transistor,
Vth, arbitrary power supply voltage VDD, output terminal potential Vout
To calculate. At this time, it does not matter which of the outputs of the non-inverted / inverted output circuit is matched or set to another value. If the W / L is adjusted when controlling the β of the MOS transistor, the W / L of each transistor can be calculated from β set as a result of the comparison of the output current values and the equation (2).
It suffices to determine L. Then, in the light receiving element circuit forming process, the circuit is designed with the determined W / L size to form the light receiving element circuit.

As in the above-described embodiment, the MOS transistors for controlling the current value according to the potential of the light receiving element provided in the non-inverting output circuit and the inverting output circuit are composed of nMOS and pMOS. Not only the manufacturing process is simplified, but also the threshold voltage of the MOS transistor, the gain coefficient, the potential of the power supply voltage, and the potential of the output terminal are adjusted and controlled so that the outputs from both the non-inverting output and the inverting output circuits match. It is possible to easily do this.

In the above embodiments, the light receiving element is not particularly described, but any light receiving element capable of converting and accumulating photocharges with high sensitivity, such as a pn photodiode, may be used.
If a pn photodiode is used, a light receiving element circuit can be realized by forming an n layer on a p type semiconductor substrate or a p layer on an n type semiconductor substrate to form a light receiving element. Furthermore, other transistors can be formed on the same substrate by a simple process.
The type of substrate can be selected according to the type of transistor, either nMOS or pMOS. Further, if silicon is used as the semiconductor substrate, the light receiving element circuit can be formed by an advanced silicon process.

Example 2. Hereinafter, another embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a partially expanded view of a circuit for explaining an embodiment of the present invention, and is a partially expanded view of FIG. 2, for example. In the figure, (a) shows a part of the non-inverting output circuit expanded, and (b) shows a part of the inverting output circuit expanded. In (a) in the figure, the non-inverting output circuit is
It is composed of a MOS transistor 11 on the high potential side and a MOS transistor 12 on the low potential side.
The inverting output circuit is composed of the MOS transistor 13 on the high potential side and the MOS transistor 14 on the low potential side. Either of the MOS transistors 11 and 12 may be a circuit selection switch transistor or a transistor whose current value is controlled by the potential of the light receiving element. Similarly, the MOS transistors 13 and 14
May be either a circuit selection switch transistor or a transistor whose current value is controlled by the potential of the light receiving element. Bias terminal 1 and power supply voltage terminal 6
Can be made common, the area of the pixel can be reduced.

The symbols in the figure represent the following. Vth (n) ... Threshold voltage of the transistors 11 and 12 forming the non-inverting output circuit. Vth (r) ... Threshold voltage of the transistors 13 and 14 forming the inverting output circuit. Vout ... Potential of the output terminal 5. VDD: The potential of the power supply voltage terminal 6. Vgn1 ... Gate potential of the transistor 11. Vgn2 ... Gate potential of the transistor 12. Vgr1 ... Gate potential of the transistor 13. Vgr2 ... Gate potential of the transistor 14. Vmn: potential between the transistors 11 and 12. Vmr: potential between the transistors 13 and 14. That is, the transistor 11 forming the non-inverting output circuit
And 12 have the same threshold voltage, and the transistors 13 and 14 forming the inverting output circuit have the same threshold voltage.

What is important in the operation of the MOS transistor is the relationship among the gate potential Vgate, the source potential Vsource, and the drain potential Vdrain in each transistor. Vgate-Vth-Vsource (3) Vdrain-Vsource (4) Comparing the magnitude relations of equations (3) and (4) between the transistors, the operating characteristics of those transistors are compared. . Here, in FIG. 3, potentials such that VDD = 2Vout ... (5) Vmr = Vmn−Vout ... (6) Vth (r) = Vth (n) + Vout ... (7) Or consider the structure of the transistor. Under the conditions of formulas (5) to (7), for the transistors 11 and 13, if Vgn1 = Vgr1 (8), then VDD-Vmn = Vout-Vmr (9) Vgn1-Vth ( n) -Vmn = Vgr1-Vth (r) -Vmr (10). That is, the transistor 11,
13 has the same relationship in both expressions (3) and (4). on the other hand,
For the transistors 12 and 14, if Vgn2 = Vgr2 (11), then Vmn-Vout = Vmr-0 (12) Vgn2-Vth (n) -Vout = Vgr2-Vth (r)- 0 (13) holds. That is, the transistors 12 and 14 are also
Both (3) and (4) have the same relation. From the above, the transistors 11 and 13 and 12 and 14 are at the equivalent positions in their respective circuits. Expression (8) (1
0) is the gate of the transistors 11 and 13 or 12 and 14.
It means that the transistors have the same potential, that is, the transistors have the same function. Therefore, if the high-potential side and low-potential side of the switching transistor and the transistor that controls the current value based on the light-receiving element potential that make up the inverting and non-inverting output circuits have the same positional relationship, both circuits will become equivalent. be able to. If both circuits are equivalent, it will be easy to design so that the outputs from both circuits have the same magnitude.

Next, the procedure for matching or controlling the outputs of the non-inverting output circuit and the inverting output circuit in this circuit configuration will be described. Output current when non-inverted output is selected in the light receiving element circuit configured by the MOS transistor having the conditions of FIG. 3 and the above equations (5) to (13) and the circuit set to the power supply voltage and the output terminal potential. To measure.
Next, the output current when inverting output is selected is measured. The results of both output current values are compared. The output value can be controlled by optimizing the gain coefficient β of the MOS transistors forming each circuit, and the threshold voltage of the transistor, the power supply voltage, which are other parameters that influence the output value,
The output terminal potential has already been set.

When controlling the gain coefficient β of the MOS transistor, β set as in the first embodiment and equation (2)
From the above, W / L of each transistor may be determined.

Example 3. Hereinafter, another embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a circuit configuration diagram showing an embodiment of the present invention, which is an example of a concrete circuit configuration of the invention described in the second embodiment. In the figure, a MOS transistor 1 whose current value is controlled by the light receiving element potential
Reference numerals 5 and 17 denote switching MOS transistors 16 and 18 in the non-inverting output circuit and the inverting output circuit, respectively.
The structure is arranged on the higher potential side. Here, if the bias terminal 1 and the power supply voltage terminal 6 are commonly used, the area of the pixel can be reduced.

Similar to the second embodiment, VDD = 2Vout (5) Vth (r) = Vth (n) + Vout (7). Further, other symbols attached in the drawings are as follows. βVI-N: Non-inverted output circuit, β βSN of the MOS transistor 15 controlling the current value by the light receiving element potential β βSN: Non-inverted output selection MOS transistor 1
6 β βVI-R: Inversion output circuit, β βSR of MOS transistor 17 controlling current value by light receiving element potential: Inversion output selection MOS transistor 18
Β Vreset ... Gate potential for controlling the reset switch 2. Vnormal: Gate potential for controlling the non-inverting output selection switch 16. Vreverse ... Gate potential for controlling the inverting output selection switch 18.

The characteristics of the light receiving element circuit when the switches 16 and 18 are placed on the higher potential side than the MOS transistors 15 and 17 which control the current value by the light receiving element potential will be examined. FIG. 5 shows output characteristic curves with respect to changes in the light receiving element potential when the switch is arranged on the high potential side and the switch is arranged on the low potential side in the circuit of FIG. As can be seen from the figure, the linearity is better when the switch is on the low potential side. The reason for this is as follows. When the switch is on the low potential side, the current flowing from the power supply potential VDD to the output terminal is controlled by the light receiving element potential in the non-inverting output circuit, and the current flowing from the output terminal to the ground (GND) is controlled by the light receiving element potential in the inverting output circuit. On the other hand, when the switch is on the high potential side, the drain voltage of the MOS transistor that controls the current value becomes almost VDD when the light receiving element potential is low in the non-inverting circuit, but when the light receiving element potential becomes high, the current value changes. The conductance of the MOS transistor to be controlled increases, and the drain voltage of the MOS transistor decreases due to the relationship with the conductance with the switching transistor. Therefore, the curve saturates at a high light-receiving element potential, resulting in poor linearity. . Similarly, in the inverting circuit, the curve is saturated at a high light-receiving element potential due to a decrease in drain voltage, resulting in poor linearity.

Further, regarding the gain coefficient of each transistor, if βVI-N = βVI-R (14) βSN = βSR (15), the inverting and non-inverting output circuits are completely equivalent. Therefore, the magnitude of the output from both circuits can be made the same. It is sufficient to maintain this relationship when increasing or decreasing the output while maintaining the canceling relationship between both output circuits.

For example, FIG. 6 shows the magnitude obtained by subtracting the inverted output from the non-inverted output in the case of βVI-N = βVI-R = βSN = βSR (16)
It is an example of what was plotted as a function of a light receiving element electric potential. The graph obtained by subtracting the inverted output from the non-inverted output ideally agrees with the horizontal axis, and it can be seen that the output is certainly the same in size but opposite in direction. As a result, when the output of the variable sensitivity light receiving element circuits according to the present invention is taken out, the same light receiving element potential can be canceled and the accuracy of the image processing in the subsequent stage can be improved.

Next, the procedure for matching or controlling the outputs of the non-inverting output circuit and the inverting output circuit in this circuit configuration will be described. Measure the output current when non-inverted output is selected in the light receiving element circuit composed of the MOS transistor having the conditions of FIG. 4 and the equations (14) and (15) and the circuit set to the power supply voltage and the output terminal potential To do. Next, the output current when inverting output is selected is measured. The results of both output current values are compared. If the output current value from the non-inverting output circuit is smaller than the output current value from the inverting output circuit, adjust the output size, or change the output current value from the non-inverting output circuit from the output current value from the inverting output circuit. In order to increase, the gain coefficient of either of the transistors forming the non-inverting output circuit may be made larger than the gain coefficient of the transistor forming the inverting output circuit. That is, βVI-N> βVI-R or βSN> βSR may be satisfied.

On the other hand, when the output current value from the non-inverting output circuit is larger than the output current value from the inverting output circuit, the output magnitude is adjusted, or the output current value from the non-inverting output circuit is changed from the inverting output circuit. In order to make the output current value smaller than that, the gain coefficient of one of the transistors forming the non-inverting output circuit may be set smaller than the gain coefficient of the transistor forming the inverting output circuit. That is, βVI
-N <βVI-R or βSN <βSR. The gain coefficient β of the MOS transistor forming the light receiving element circuit may be controlled in this way, and the light receiving element circuit can be easily realized by designing W / L based on β determined here.

Example 4. Hereinafter, another embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a circuit configuration diagram showing an embodiment of the present invention. In the figure, the difference from FIG. 4 is that the bias terminal 1 and the power supply voltage terminal 6 are common.
The diode-connected MOS transistor 19 is arranged between the non-inverting output circuit and the power supply voltage terminal 6, and the switching MOS transistor 18 of the inverting output circuit is more than the MOS transistor 17 whose current value is controlled by the light receiving element potential. That is, it is arranged on the high potential side. The gain coefficient of the diode-connected MOS transistor 19 is βdiode,
The threshold voltage is Vth (diode). Here, if the bias terminal is also used as the power supply voltage terminal 6, the area of the pixel can be reduced.

Similar to the third embodiment, Vth (r) = Vth (n) + Vout (7).

At this time, the higher the bias terminal potential of the light receiving element is, the wider the dynamic range is. However, since the bias terminal is commonly used as the power supply voltage terminal 6, the bias terminal is VDD, while the equation (5) From (7), since VDD = 2Vout = 2 [Vth (r) -Vth (n)] (17), it is impossible to increase VDD in order to enlarge the bias terminal. Therefore, the formula
In some cases, the bias terminal potential cannot be increased while satisfying (17). Here, if the diode-connected transistor 19 is inserted between the transistor 15 and the power supply voltage terminal 6, the drain potential of the transistor 15 is substantially higher than VDD by Vt.
Only h (diode) lower potential. As a result, the bias terminal potential of the light receiving element can be increased while keeping the magnitudes of the outputs from the inverting and non-inverting output circuits the same. That is, VDD to 2Vout + Vth (diode) (18), and it becomes possible to increase VDD and improve the dynamic range of the light receiving element.

In the non-inverting output circuit, if the diode-connected transistor 19 is inserted between the transistor 15 and the power supply voltage terminal 6, the MOS transistor is changed by the change in the potential of the light receiving element as in the case where the switching transistor is placed on the high potential side.
The drain voltage of the transistor 15 will change, and the linearity will deteriorate. So even in the inverting output circuit,
If the switching MOS transistor 18 is placed on the higher potential side than the MOS transistor 17 that controls the current value by the light receiving element potential, the linearity is inferior to the outputs from both circuits, but the shape of the output characteristic curve is the same. Therefore, it becomes easy to design so that the magnitude of the output current from each circuit becomes equal.

Further, with such a circuit configuration, the number of transistors on the non-inverting output circuit side is 3, and the number of transistors on the inverting output circuit side is 2, which makes the circuit asymmetrical, and therefore transistors having the same gain coefficient are used. Then, the output of the non-inverting output circuit becomes smaller. Therefore, if the gain coefficients of the diode-connected transistor 19 and the MOS transistor 16 are made larger than the gain coefficients of the other transistors, that is, the gain coefficients of the transistors forming the non-inverting output circuit are made larger, the magnitude of the output from both circuits is increased. It can be designed to be the same.

A procedure for matching or controlling the non-inverting output circuit and the inverting output circuit in this circuit configuration will be described. In the light receiving element circuit composed of the MOS transistor shown in FIG. 7, the circuit set to the power supply voltage, and the output terminal potential, the output current when non-inverting output is selected is measured. Next, the output current when inverting output is selected is measured. Here, the outputs from both circuits are compared, and the gain coefficients of the MOS transistors forming both circuits are controlled so that the outputs from both circuits match. At this time, the number of transistors on the non-inverting output circuit side is 3, and the number of transistors on the inverting output circuit side is 2, which is asymmetrical in the circuit. Therefore, the gain coefficient of the transistor configuring the non-inverting output circuit is configured as the inverting output circuit. It may be larger than the gain coefficient of the transistor.

Even if the circuit shown in FIG. 4 is used instead of the circuit shown in FIG. 7, if it is determined that the dynamic range of the light receiving element needs to be improved when the output is measured, the circuit is diode-connected. The gain coefficient of each transistor forming each circuit may be determined according to the above procedure by disposing the transistor 19 and considering the disposition with the switching transistor.

Example 5. Another embodiment of the present invention will be described below. The gain coefficient β of the MOS transistor is
As expressed by the equation (2), it is described by β = με (ox) / t (ox) · (W / L) (2). In the equation (2), generally, when the threshold voltage changes, the value of μ also changes. Here, μ is the effective surface mobility in the channel, which substantially represents the current driving capability of the transistor. That is, the output current value for the same (W / L) changes. Therefore, as in Examples 5 to 8, the threshold voltage is specified to optimize the combination of the gain coefficients β, and (W /
To control L), precise β cannot be optimized without considering the difference in μ. Therefore, in Examples 1 to 4, the output magnitudes of the inverting output circuit and the non-inverting output circuit are compared, and when the β and (W / L) are determined, the ratio of β between transistors having different threshold voltages is compared. The value obtained by dividing by the ratio of μ may be used as the ratio of (W / L). When the same β value is used for a transistor with a high threshold voltage and a transistor with a low threshold voltage, if μ of a transistor with a high threshold voltage becomes half of μ of a transistor with a low threshold voltage, (W / L) may be doubled (W / L) of a transistor having a low threshold voltage.

For example, it is assumed that two MOS transistors for which β should be determined have threshold voltages V1 and V2. The gain coefficient of each transistor is β1, β2, the current drive capacity is μ1, μ2, and the gate width / gate length ratio is W /
If L1 and W / L2, then (β1 / β2) / (μ1 / μ2) = (W / L1) / (W / L2) ・ ・ ・ The gate width / gate length ratio W so as to satisfy the equation (19). / L should be determined.

Further, when the potential on the source side is different, the threshold voltage is influenced by the substrate bias effect.
As can be seen from (1), the output current value I of the MOS transistor also changes. In particular, in the structures of Examples 1 to 4, since the source potential of the inverting output circuit is 0 and the source potential of the non-inverting output circuit is Vout, only the non-inverting output circuit is greatly affected by the substrate bias effect. Therefore, in order to properly realize the operations as in Examples 1 to 4 as designed, the substrate bias effect is taken into consideration, and the W / L of the transistor that causes a decrease in the current value is increased accordingly.
The W / L of the transistor whose current value does not decrease may be reduced accordingly.

In order to match or control the outputs from the non-inverting output circuit and the inverting output circuit in the first to fifth embodiments,
By forming a temporary light receiving element and measuring the output from the circuit, β and Vth of the transistor forming the circuit are measured.
The power supply voltage and the potential of the output terminal have been determined by calculation. However, in each embodiment, a simulated circuit is assumed, and the output from the circuit is calculated to calculate the β of the transistor forming the circuit,
It may be determined by a model calculation of calculating Vth, the power supply voltage, and the potential of the output terminal.

Example 6. Hereinafter, another embodiment of the present invention will be described with reference to the drawings. In the present embodiment, the first to the first embodiments
A detailed example of the structure of a light receiving element circuit using a pn photodiode as the light receiving element of No. 5 will be described.

FIG. 8 is a partial cross sectional view showing the cross sectional structure of the light receiving element circuit according to the embodiment of the present invention. In the figure, p
On the substrate 20, a light receiving element 3 composed of an n + layer, one end of which is connected to the bias terminal 1 via the reset switch 2, a transistor 9 for converting the potential from the light receiving element 3 into a current, and the circuit itself. A terminal 4 for grounding is formed or connected. The reset switch 2 and the transistor 9 are provided with a metal film 22 for shielding via an insulating layer (not shown, but arranged directly below the metal film 22).
Is arranged. A p + layer 21 for making a substrate contact is formed on the p − substrate 20 and is grounded 4. It should be noted that this figure is one cross section, and a plurality of transistors that normally constitute the light receiving element circuit are arranged in other cross section portions. As the substrate, p is obtained by doping with a semiconductor substrate.
-A substrate can be realized, but silicon makes the process easier. Hereinafter, the substrate is assumed to be silicon.

Since the light-receiving element 3 is formed by forming the n + layer on the p − substrate 20, it can be manufactured in the same process as a normal MOS transistor. Further, since the reset transistor 2 is connected to the bias terminal 1 through the reset switching transistor 2, the reset transistor 2 can determine the accumulation time to accumulate the photocharges, and thus the sensitivity can be improved. Further, by providing the substrate contact 21 in the light receiving element circuit and guiding it to the ground 4,
Even when the light incident is strong and the charges are excessively generated in the light receiving element, the charges are released through the substrate contact 21, so that, for example, when a plurality of light receiving element circuits are arranged, the light leaks into the surrounding light receiving elements and causes noise such as noise. It is possible to prevent the occurrence. Further, since the metal film 22 shields, it is possible to prevent light and electromagnetic waves from entering the transistor circuit and reduce noise and malfunctions.

Next, the doping concentration of the substrate used in this embodiment will be described. In this embodiment, the p − substrate 20 has a doping concentration lower than 1 × 10 ¹⁶ cm ⁻³ . When the doping concentration is lower than 1 × 10 ¹⁶ cm ^-3 , the substrate bias effect is suppressed and thus the fluctuation of the threshold voltage is suppressed. Term ΔV of change in threshold voltage due to substrate bias effect
th is represented by the following equation. ΔVth = γ [(Vsb + 2VBF) ^1/2 − (2VBF) ^1/2 )] (20) where Vsb is the potential difference between the source and the substrate, and VBF is the built-in barrier of the pn junction. Further, γ is expressed by the following equation (21). γ = t (ox) / ε (ox) · (2qε (Si) Na) ^1/2 (21) where t (ox) is the thickness of the oxide film and ε (ox) is the oxide film ( Here, the dielectric constant of the silicon oxide film), q is the electron charge, and ε (S
i) is the dielectric constant of silicon, and Na is the doping concentration of the substrate.

In the above equation (20), [(Vsb + 2VBF)
^1/2 - term (2VBF) ^1/2)] can not be adjusted in the process of forming the light receiving element, the operating potential with transistor is treated as a constant. Therefore, in order to reduce the influence of the variation of the threshold voltage due to the substrate bias effect, that is, ΔVth, γ must be reduced.

In the above equations (20) and (21), t (ox) = 20 (nm) ε (ox) = 4 × 8.85 × 10 ^-14 (F / cm) q = 1.6 × 10 ^-19 (c) ε (Si) = 12 × 8.85 × 10 ^-14 (F / cm), and from the film thickness range used in the actual process,
When here, the thickness of the oxide film t (ox) = 20 (nm ), and when ^{Na = 1 × 10 16 (cm} -3) following gamma = 0.33 in the following, the value of ΔVth becomes smaller. Therefore p-substrate 20
As a result, when the doping concentration is lower than 1 × 10 ¹⁶ cm ^-3 , the substrate bias effect is suppressed, so that the inverting and non-inverting output circuits can be designed without considering the influence of the fluctuation of the threshold voltage. .

Furthermore, since the width d of the depletion layer has a relationship of d∝ (Na) ^−1/2 ... (22), if the doping concentration of the p − substrate 20 is low, that is, Na is small, the depletion layer is Is easily spread, and the sensitivity as a light receiving element is improved. Needless to say, the doping concentration cannot be 1 × 10 ¹³ cm ⁻³ or less.

In FIG. 8, a p-type substrate on which an n-type layer is formed is used as a light receiving element, but an n-type layer formed on a p-well or an n-type substrate or an n-well is formed on a p-type substrate. It goes without saying that the same effect can be obtained by using the formed one.

Embodiment 7. An embodiment of the present invention will be described below with reference to the drawings. FIG. 9 is a partial cross-sectional view showing the structure of a light receiving element circuit showing one embodiment of the present invention. In the figure, the light receiving element 3 is a capacitor 2 connected in parallel.
3 and 3 are connected to a transistor 9 which converts a potential into a current. As shown in FIG. 8, when a light-receiving element is formed by forming an n + layer on the p- substrate (or by forming a p + layer on the n- substrate), the pn junction capacitance is insufficient and the output potential of the light-receiving element is low. Is easily saturated. Therefore, as shown in FIG. 9, if a capacitor 23 of MOS capacitance is connected in parallel to the light receiving element 3, the charge storage capacity of the light receiving element can be increased.

By providing each transistor circuit with the shielding metal film 22 as in the sixth embodiment,
It goes without saying that noise and malfunctions can be suppressed.
Further, the substrate contact 21 can be provided.

Embodiment 8 Another embodiment of the present invention will be described below with reference to the drawings. FIG. 10 is a partial cross-sectional view showing the structure of a light receiving element circuit showing one embodiment of the present invention. In the figure, the capacitance C of the pn junction is described by the following equation (23) when the n-side doping concentration is sufficiently higher than the p-side doping concentration. C = (qε (Si) Na / 2VBF) ^1/2 (23) That is, it is proportional to the 1/2 power of the p-side doping concentration. To increase the accumulated charge capacity and widen the range of the amount of received light as a light receiving element, the doping concentration on the p side may be increased. Therefore, for example, as the p − substrate 20, the doping concentration is 1 × 10 ¹⁴
When using cm ^-3 , the doping concentration is 1 × 10
By forming the p-type layer 24 of ¹⁵ cm ⁻³ or more and further forming the n-type layer therein, the charge storage capacity can be tripled or more. This makes it possible to simultaneously obtain the effect of expanding the range of the amount of received light while suppressing the substrate bias effect.

Further, in the above-mentioned embodiment, an example in which a high concentration p-type layer and an n-type layer are formed on the p-substrate is shown. However, an n-type substrate having a doping concentration of 1 × 10 ¹⁵ cm ^-3 or more is used. It goes without saying that the same effect can be obtained even with a structure in which the mold layer is formed and the p-type layer is formed therein.

Further, in FIG. 10, the n-type layer was formed so as to be included in the p-type layer 24. However, as shown in FIG. Layer 2
4 may be formed outside. As shown in FIG. 11, p
With the structure in which the n-type layer formed in the mold layer 24 protrudes, the storage capacitance of the light receiving element can be freely designed.

Embodiment 9 An embodiment of the present invention will be described below with reference to the drawings. FIG. 12 is a diagram showing a configuration of a light receiving element circuit array in which a plurality of light receiving element circuits of Examples 1 to 8 are arranged in a two-dimensional array. In the figure, one light receiving element circuit 25 forming one pixel is arranged in the horizontal direction by four pieces and in the vertical direction by four pieces. One line in the horizontal direction of each light receiving element circuit 25, for example, 25a, 25b, 25c, 25d
The light receiving element circuit of is a switch terminal Vr28, Vn29, V
It is connected to the control circuit 26 with p30 in common. On the other hand, one line in the vertical direction of each light receiving element circuit 25, for example, the light receiving element circuits of 25d, 25e, 25f, and 25g are connected to the output circuit 27 with the output terminal OUT31 in common.

FIG. 13 illustrates an example of the light receiving element circuit 25, and it is shown that (a) in FIG. 13 used in FIG. 12 is equivalent to (b). In the figure, the circuit uses the circuit of FIG. Gate voltage of reset transistor 2, switching transistor 1 for selecting non-inverting output circuit
6 and the inverting output circuit selecting switching transistor 18 have gate voltages Vr28 and Vn2, respectively.
At 9, Vp30, the output from the output terminal 5 is OUT31. The ground (GND) 4 in the control circuit in the drawing forms a substrate contact, and as shown in the sixth embodiment,
The influence of excess charges from the peripheral light receiving element 3 is avoided.

Next, the operation will be described. Control circuit 26
The light receiving element of each light receiving element circuit to which the reset signal Vr28 is simultaneously sent from the light receiving element receives light for a predetermined time, and the signal is sent to the non-inverting / inverting output circuit via the potential / current converting transistors 15 and 17. The light receiving element circuit arranged on one horizontal line is Vn29 from the control circuit 26 through a common wiring.
Alternatively, a control signal is sent to Vp30. The output signal 31 from each light receiving element circuit is sent to the output circuit 27. In this way, the switch terminal is shared for each horizontal run to obtain the output signal, and the output terminal is shared for each vertical line. Therefore, the output signal obtained for each horizontal run is sequentially transferred in the vertical direction. can do. With such an array structure, it becomes possible to take out a one-dimensional or two-dimensional light pattern simultaneously, in parallel, and while performing a calculation between pixels.

Although FIG. 12 of the ninth embodiment shows an example of two-dimensional arrangement, the same effect can be obtained for a one-dimensional optical pattern even if it is arranged one-dimensionally. Needless to say.

Since the substrate contacts are formed in the respective light receiving element circuits of the light receiving element circuit array of the ninth embodiment, as described in the sixth embodiment, the light incidence is strong and the light receiving elements are excessively charged. Even if it occurs, it is possible to prevent the electric charge from escaping into the surrounding light receiving element by causing the electric charge to escape through the substrate contact, which may cause noise and the like.

In the first to ninth embodiments, the pn photodiode formed by using the silicon substrate as the light receiving element has been described, but a material other than silicon, for example,
It goes without saying that the same effect can be obtained by using a III-V group compound semiconductor, a II-VI group compound semiconductor, germanium, and a combination thereof with silicon.

In the first to ninth embodiments, a combination of AMI (Amplified MOS Image) is used as the pn photodiode light receiving element and an amplifier circuit for converting the potential of the light receiving element into a current. , And other types of amplification type photo detectors such as CMD (Charge Modulation
vice), SIT (Static Induced Transistor), AP
D (Avalanche Photodiode), FGA (Floating Gate)
It is needless to say that the same effect is exhibited even with an Array), a BASIS (Base Stored Image Sensor), or the like.

In Examples 1 to 9, the pn photodiode light receiving element was used as the light receiving element.
It is needless to say that the same effect can be obtained by using a material having sensitivity in the infrared region, such as i, HgCdTe, SiGe, InSb, or a combination thereof.

Since the sensitivity varying function can be realized on the silicon (Si) substrate, the control circuit can be easily built on the same chip.

In the first to ninth embodiments, the light receiving element section and the control circuit section are made of the same material on the same silicon substrate, but any of the substrate, the light receiving element section material, and the control circuit material may be used. The materials may be different from each other.

[0126]

The light receiving element circuit according to claim 1 of the present invention is
Since the MOS transistor having a specific gain coefficient or threshold voltage, the output terminal whose potential is specified, and the power supply voltage whose potential is specified are provided, the absolute value of the output of the non-inverting / inverting output circuit can be controlled by the gain coefficient, It is possible to provide a light-receiving element circuit having high performance capable of processing a desired signal necessary for image processing in the subsequent stage. Further, by providing the non-inverting / inverting output circuit, the polarity of the signal can be controlled without the negative power supply.

According to a second aspect of the present invention, in the light receiving element circuit of the first aspect, the gain coefficient of the MOS transistor is controlled by the ratio of the gate width and the gate length of the transistor.
It is possible to provide a light-receiving element circuit having a high performance capable of easily controlling the gain coefficient of the MOS transistor and processing a desired signal required for image processing in the subsequent stage.

A light receiving element circuit according to a third aspect of the present invention is the same as the light receiving element circuit according to the first or second aspect, in which the n-type circuit is provided with a MOS transistor for controlling a current value by the potential of the light receiving element.
Since the MOS or pMOS transistor is used, the potential of the light receiving element can be amplified and the sensitivity can be controlled with a simple circuit configuration, and a high performance light receiving element circuit can be provided. In addition, if the transistor is formed using the same type of transistor as another transistor, the circuit can be simplified by the same process and simple steps. Further, since it is not necessary to form two p and n wells in one pixel (one light receiving element circuit), the size of the pixel can be reduced. Further, in the case of an nMOS, when an element whose potential increases as the light is irradiated is used as the light receiving element, the output current is 0 if the light is not irradiated,
The output current can be increased as the intensity of the incident light is stronger. In the case of a pMOS, if a light receiving element whose potential lowers as the light is irradiated is used, the output is output if the light is not irradiated. It is possible to adopt a configuration in which the output current increases as the current is 0 and the incident light is stronger.

The light receiving element circuit according to a fourth aspect of the present invention is the light receiving element circuit according to any one of the first to third aspects, in which the non-inverting output circuit and the inverting output circuit are provided with switching transistors for selecting respective circuits. Can be easily selected from the outside. Further, since each circuit can be selected by the conduction of each circuit by opening / closing the switching transistor, the potential of the light receiving element is not affected, and a complicated reset operation is unnecessary. Further, by controlling the gate voltage of the switching transistor in an analog manner, it is possible to provide a high-performance light receiving element circuit in which the output current value for a constant light receiving element potential can be changed in an analog manner.

According to a fifth aspect of the present invention, in the light receiving element circuit according to the fourth aspect, the non-inverting output circuit and the inverting output circuit are both a transistor for controlling a current value by the potential of the light receiving element and a switching transistor. The circuit can be simplified and the size of the pixel can be reduced by adopting a configuration in which is connected in series. Further, since it is a simple circuit, it is easy to arbitrarily control the outputs from both the non-inverting and inverting output circuits, and it is possible to provide a light receiving element circuit with high performance.

A light receiving element circuit according to a sixth aspect of the present invention is the MOS transistor threshold voltage according to any one of the first to fifth aspects, wherein the current value is controlled by the potentials of the light receiving elements provided in the non-inverting output circuit and the inverting output circuit. Since the difference between the two is taken as the potential of the output terminal, the transistors that make up the non-inverting output circuit and the transistors that make up the inverting output circuit can be arranged so as to be electrically equivalent. It is easy to design so that they have the same value. That is, the outputs from both the non-inverting and inverting output circuits can be easily controlled arbitrarily, and a high-performance light receiving element circuit can be provided.

According to a seventh aspect of the present invention, in the light receiving element circuit according to any one of the first to sixth aspects, the potential of the power supply voltage terminal is twice the potential of the output terminal. Since the potential difference from the output terminal to the output terminal is the same as the potential difference from the output terminal of the inverting output circuit to the ground terminal,
It is easy to design the two circuits to be electrically equivalent so that the magnitudes of the outputs from the two circuits are the same, and it is possible to provide a light receiving element circuit with high performance.

According to an eighth aspect of the present invention, in the light receiving element circuit according to the seventh aspect, the positional relationship between the high potential side and the low potential side of the transistor for controlling the current value by the potential of the light receiving element and the switching transistor is the same. Since it is arranged so that both circuits can have an electrically symmetrical structure, it becomes easy to design so that the magnitudes of the outputs from both circuits are the same, and a high-performance light receiving element A circuit can be provided.

According to a ninth aspect of the present invention, in the light receiving element circuit according to the eighth aspect, in the non-inverting circuit and the inverting circuit, the switching transistor is set to a lower potential side than the transistor whose current value is controlled by the potential of the light receiving element. By arranging them, the change of the drain voltage is smaller than that in the case where the switching transistor is placed on the high potential side, so that the linearity is improved and a high performance light receiving element circuit can be provided.

The light receiving element circuit according to claim 10 of the present invention is
In any one of claims 7 to 9, in the non-inverting circuit and the inverting circuit, since the gain coefficients of the MOS transistors that control the current value by the light receiving element potential are the same and the gain coefficients of the switching transistors that select the respective circuits are the same, Both circuits are electrically equivalent, the magnitudes of outputs from both circuits can be matched and controlled, and a high-performance light receiving element circuit can be provided.

The light receiving element circuit according to claim 11 of the present invention is
In any one of claims 1 to 5, a diode-connected transistor is arranged between the power supply voltage terminal of the non-inverting output circuit and the MOS transistor whose current value is controlled by the light-receiving element potential, so that it is transmitted to the MOS transistor. Even if the potential of the power supply voltage terminal drops substantially and the potential of the power supply voltage terminal is sufficiently higher than that of the output terminal, it is easy to control the output from the non-inverting / inverting output circuit to be the same. It is possible to provide a high-performance light receiving element circuit.

According to the twelfth aspect of the present invention, the light receiving element circuit is
12. The non-inverting circuit according to claim 11, wherein the switching transistor is placed on the higher potential side than the transistor whose current value is controlled by the potential of the light receiving element included in the inverting circuit. The linear characteristics can be the same, and the output of both circuits can be designed to be the same,
A light-receiving element circuit with high performance can be provided.

According to the thirteenth aspect of the present invention, the light receiving element circuit is
13. The MOS according to claim 11 or 12, wherein the threshold voltage of the diode-connected transistor is controlled by a light receiving element potential provided in an inverting circuit or a non-inverting circuit.
Since it matches with one of the threshold voltage of the transistor,
Since there are two types of threshold voltage of the transistor and it is easy to control the output from the non-inverting / inverting output circuit to be the same, the number of steps in the manufacturing process is reduced,
Productivity is improved.

The light receiving element circuit according to claim 14 of the present invention is
14. The non-inverting circuit according to claim 11, wherein the output of the non-inverting circuit is reduced by the number of transistors constituting the non-inverting circuit, and the gain coefficient of the diode-connected transistor and the non-inverting circuit selecting switching transistor is received. By making it larger than the gain coefficient of any of the other transistors that make up the element circuit, it becomes easier to control so that the output from the non-inverting / inverting output circuit is the same, and a high-performance photodetector circuit. Can be provided.

The light receiving element circuit according to claim 15 of the present invention is
16. The relation between the transistors constituting the light receiving element circuit according to claim 13, wherein the value of the gain coefficient ratio to the ratio of the current driving capability between the transistors is the ratio of the gate width / gate length ratio between the transistors. Since it is a transistor having a
The difference in current driving capability between the transistors can be compensated, and a desired light receiving element circuit as designed can be provided. Further, the image processing accuracy in the latter stage is improved.

According to the sixteenth aspect of the present invention, the light receiving element circuit is
16. The light receiving element according to claim 1, wherein the light receiving element is pn.
Since it is a photodiode, it is easy to generate photocharges, and a circuit can be configured using a simple light receiving element.

The light receiving element circuit according to claim 17 of the present invention is
The nMOS of the control circuit unit according to claim 16, wherein the pn photodiode has an n-type layer formed on a p-type substrate or has a p-type layer formed on an n-type substrate.
Or it can be created in the same process as pMOS transistor,
The manufacturing process can be simplified.

The light receiving element circuit according to claim 18 of the present invention is
In claim 17, since the switching transistor for resetting the pn photodiode is connected to the n-type layer or the p-type layer of the pn photodiode, the light storage time of the pn photodiode can be controlled, and the performance of the light receiving element circuit can be improved. improves.

The light receiving element circuit according to claim 19 of the present invention is
The doping concentration of the substrate forming the light receiving element and the control circuit is set to 1 × 10 ¹³ cm according to any one of claims 16 to 18.
^Since it is higher than ^-3 and lower than 1 × 10 ¹⁶ cm ^-3 , the doping concentration of the substrate is sufficiently low and the substrate bias effect can be ignored, so the electrical equivalence of the non-inverting and inverting output circuits of the control circuit is maintained. can do. Further, since the doping concentration of the substrate is low, the sensitivity is improved and the performance as a light receiving element circuit is also improved.

The light receiving element circuit according to claim 20 of the present invention is
20. The substrate for forming the light receiving element and the control circuit according to claim 19, wherein the light receiving element forming portion in the p type substrate is a p type layer having a doping concentration of 1 × 10 ¹⁵ cm ⁻³ or more. It is a light-receiving element provided with an n-type layer doped at a concentration higher than the doping concentration of the p-type layer therein, or the substrate forming the light-receiving element and the control circuit is n-type.
The n-type substrate having a doping concentration of 1 × 10 ¹⁵ cm ⁻³ or more and a higher concentration than that of the n-type layer. Since the light receiving element includes the p-type layer, the concentration of the portion where the depletion layer spreads in the pn junction is sufficiently high even when the substrate concentration is low, so that the pn junction capacitance can be increased. The performance as an element circuit is improved.

The light receiving element circuit according to claim 21 of the present invention is
The capacitor for accumulating the output from the light receiving element is connected in parallel between the light receiving element and the control circuit according to any one of claims 1 to 20, so that the photoelectric charge can also be stored in the capacitor, so that the substrate concentration is low. Even if the pn junction capacitance is small, the storage capacitance in the light receiving element portion including the capacitor can be increased, and the performance of the light receiving element circuit is improved.

The light receiving element circuit according to claim 22 of the present invention is
In any one of Claims 1 to 21, since a metal film is provided in a portion forming the transistor circuit, light and electromagnetic waves are prevented from entering the transistor circuit by the metal film, so that noise and malfunction of the circuit are avoided. Therefore, the reliability of the light receiving element circuit is improved.

A light receiving element circuit array according to a twenty-third aspect of the present invention is one-dimensional because the light receiving element circuits according to any one of the first to twenty-second aspects are arranged in a one-dimensional or two-dimensional array. Alternatively, two-dimensional light patterns can be simultaneously received in parallel, desired image processing can be performed, and a highly functional light receiving element circuit array can be provided.

According to a twenty-fourth aspect of the present invention, in the light-receiving element circuit array according to the twenty-third aspect, the switch terminals of the light-receiving element circuits arranged on one horizontal line of the plurality of light-receiving element circuits arranged in an array are common. Since the output terminals of the light receiving element circuits arranged on one line in the vertical direction are made common, one-dimensional or two-dimensional light patterns can be simultaneously extracted in parallel and while performing pixel-to-pixel calculation.
A highly functional light receiving element circuit array can be provided.

According to the twenty-fifth aspect of the present invention, in the light-receiving element circuit array according to the twenty-third or twenty-fourth aspect, since the substrate contact is provided for each light-receiving element circuit on the ground line in the light-receiving element circuit, excess light is received by the light-receiving element. Even if electric charge is generated, the electric charge escapes from the contact portion to the ground line, so that it is possible to prevent the electric current from flowing into surrounding pixels and causing noise or the like. Furthermore, when the photocharge from the light receiving element overflows, it will prevent it from flowing into surrounding pixels and causing noise etc.
A highly functional light receiving element circuit array can be provided.

According to a twenty-sixth aspect of the present invention, there is provided a method of configuring a light-receiving element circuit, comprising: a light-receiving element; and a control circuit for controlling the magnitude and polarity of a signal obtained by converting the potential of the light-receiving element into a current and outputting the signal to the outside. A non-inverting output circuit, wherein the control circuit includes a MOS transistor for controlling the current value flowing from the power supply voltage terminal to the output terminal according to the potential of the light receiving element. And a circuit (inversion output circuit) including a MOS transistor for controlling a current value flowing from an output terminal to a ground terminal according to a potential from the light reception element, the non-inversion output circuit comprising: A first step of measuring or calculating the signal to be selected and output to the outside, that is, the magnitude of the current flowing into the output terminal, and the inverting output circuit being selected and output to the outside A second step of measuring or calculating the magnitude of the current flowing out from the output terminal, that is, the magnitude of the current flowing out of the output terminal, a third step of comparing the results of the first and second steps, and At least one of the gain coefficient and threshold voltage of the MOS transistor forming the control circuit, the potential of the output terminal, and the potential of the power supply voltage so that the magnitudes of the output signals from the inverting output circuit and the inverting output circuit are the same. And a fourth step of controlling the output voltage of the non-inverting / inverting output circuit, the output of the non-inverting / inverting output circuit is the gain coefficient and threshold voltage of the MOS transistor constituting the control circuit, the potential of the output terminal, and the potential of the power supply voltage. Since it can be described by a function of the gain coefficient of the MOS transistor, the output of the non-inverting / inverting output circuit can be controlled by controlling at least one of them. Designed so as to equal the absolute value is facilitated, it can be provided a light receiving element circuit having a desired output, such as to improve the image processing accuracy at the subsequent stage.

According to a twenty-seventh aspect of the present invention, in the twenty-sixth aspect of the present invention, in the twenty-sixth aspect, when it is selected and set that the gain coefficient of the MOS transistor constituting the control circuit is controlled in the fourth step. After the fourth step, a fifth step of controlling the set gain coefficient of the MOS transistor by the gate width / gate length ratio of each MOS transistor is provided, so that the gain coefficient of the MOS transistor is changed to the gate width of the transistor. Since it is controlled by the / gate length ratio, the gain coefficient of the MOS transistor can be easily controlled, and a light receiving element circuit having a desired output can be provided.

According to a twenty-eighth aspect of the present invention, in the method of constructing a light-receiving element circuit according to the twenty-seventh aspect, in the fifth step, the ratio of the gate width / gate length ratio between the transistors to be set is set to the current driving capability between the transistors. Since the gain coefficient of the MOS transistor is set so as to be the ratio of the gain coefficient to the ratio of the
A difference in current driving capability between transistors can be compensated for, and a light receiving element circuit having a desired output as designed can be provided. Therefore, the image processing accuracy in the subsequent stage is improved.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration of a light receiving element circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a light receiving element circuit according to the first embodiment of the present invention.

FIG. 3 is a partial development view of a circuit for explaining a method of configuring a light receiving element circuit according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a light receiving element circuit according to a third embodiment of the present invention.

FIG. 5 is a graph showing an example of output characteristics of signals from the light receiving element circuit according to the third embodiment of the present invention.

FIG. 6 is a graph showing an example of signal output characteristics from a light receiving element circuit according to a third embodiment of the present invention.

FIG. 7 is a configuration diagram of a light receiving element circuit according to a fourth embodiment of the present invention.

FIG. 8 is a partial cross-sectional view showing the structure of a light receiving element circuit according to Example 6 of the invention.

FIG. 9 is a partial cross-sectional view showing the structure of a light receiving element circuit according to Example 7 of the invention.

FIG. 10 is a partial cross-sectional view showing the structure of a light receiving element circuit according to Example 8 of the invention.

FIG. 11 is a partial cross-sectional view showing the structure of another light receiving element circuit according to embodiment 8 of the present invention.

FIG. 12 is a circuit configuration diagram showing a light receiving element circuit array according to a ninth embodiment of the present invention.

FIG. 13 is a circuit configuration diagram showing a detailed example of a circuit forming each light receiving element circuit (pixel) in FIG. 9.

FIG. 14 is a circuit configuration diagram showing a conventional light receiving element circuit.

FIG. 15 is a graph showing an output characteristic from a MOS transistor for explaining an output characteristic of a signal from a conventional light receiving element circuit.

[Explanation of symbols]

1 bias terminal, 2 reset switch, 3
Light receiving element, 4 ground, 5 output terminals, 6 power supply voltage, 7 MOS transistor circuit that controls the current value flowing from the power supply voltage terminal to the output terminal (non-inverting output circuit) 8 Controls the current value flowing from the output terminal to the ground terminal MOS transistor circuit (inverting output circuit) 9, 9a, 9b MOS transistor 10, 10a, 10b for controlling current value by light receiving element potential Circuit switching transistor 11 Non-inverting output circuit high-side MOS transistor 12 Non MOS transistor 13 on the low potential side of the inverting output circuit 13 MOS transistor on the high potential side of the inverting output circuit 14 MOS transistor on the low potential side of the inverting output circuit 15 MOS transistor whose current value is controlled by the light receiving element potential 16 Non-inverting output circuit selection switch MOS transistor 17 Photodetector MOS transistor for controlling current value by potential 18 MOS transistor for selection switch of inverting output circuit 19 MOS transistor with diode connection 20 p- substrate, 21 p + for making substrate contact
Layer, 22 shield metal film, 23 capacitor with MOS capacitance, 24 p-p-type layer with doping concentration of 1 × 10 ¹⁵ cm ^-3 or more built in the substrate, 25, 25
a, 25b, 25c, 25d, 25e, 25f, 25g 1 light receiving element circuit (1 pixel), 26 control circuit, 27 output circuit, 28 gate voltage Vr of transistor 2, 29 gate voltage Vn of transistor 18, 30 transistor 16 Gate voltage Vp,
31 Output from output terminal 5 OUT 101 Bias terminal, 102 Reset switch,
103 photo detector, 104 tri-state switch,
105 pMOS transistor for non-inverting output, 106 nMOS transistor for inverting output, 107 output terminal, 10
8 ground, 109 power supply voltage

Claims (28)

[Claims] 1. A light-receiving element circuit comprising: a light-receiving element; and a control circuit for converting the potential of the light-receiving element into a current and controlling the magnitude and polarity of a signal obtained and outputting the signal to the outside. The circuit consists of a MOS transistor (non-inverting output circuit) that controls the current value that flows from the power supply voltage terminal to the output terminal according to the potential of the light receiving element, and the current value that flows from the output terminal to the ground terminal depending on the potential of the light receiving element. And a threshold voltage, a potential of an output terminal, and a power supply voltage of a MOS transistor forming the light receiving element circuit. At least one of the potentials is specified so that the magnitudes of the output signals from the non-inverting output circuit and the inverting output circuit are equal to the same light receiving element potential. A light-receiving element circuit having different values. 2. The light-receiving element circuit according to claim 1, wherein the MOS transistor has a gain coefficient specified and controlled by a ratio of a gate width and a gate length of the transistor. 3. The light receiving element circuit according to claim 1, wherein the circuit including the MOS transistor for controlling the current value according to the potential of the light receiving element includes an nMOS or pMOS transistor. 4. The light-receiving element circuit according to claim 1, wherein the non-inverting output circuit and the inverting output circuit each include a switching transistor for selecting each circuit. 5. The non-inverting output circuit and the inverting output circuit are composed of a circuit in which a MOS transistor for controlling a current value according to the potential of a light receiving element and a switching transistor for selecting each circuit are connected in series. The light-receiving element circuit according to claim 4, wherein. 6. The potential of the output terminal is defined by the difference between the threshold voltages of the MOS transistors for controlling the current value by the potentials of the light receiving elements provided in the non-inverting output circuit and the inverting output circuit. The light-receiving element circuit described in any one of 1. 7. The light receiving element circuit according to claim 1, wherein the potential of the power supply voltage terminal is twice the potential of the output terminal. 8. In a non-inverting output circuit and an inverting output circuit, a MOS transistor that controls a current value according to the potential of a light receiving element and a switching transistor for selecting each circuit are arranged relatively equipotentially. The light receiving element circuit according to claim 7, wherein 9. In the non-inverting output circuit and the inverting output circuit, a switching transistor for selecting each circuit is on a lower potential side than a MOS transistor for controlling a current value by a potential of a light receiving element provided in both circuits. 9. The light-receiving element circuit according to claim 8, wherein the light-receiving element circuit is arranged in. 10. A MOS for controlling a current value according to the potential of a light receiving element, which is provided in a non-inverting output circuit and an inverting output circuit.
10. The transistor and the switching transistor for selecting the respective circuits have equal gain coefficients between the non-inverting output circuit and the inverting output circuit, respectively. Light receiving element circuit. 11. The non-inverting output circuit according to claim 1, wherein a diode-connected transistor is arranged in series between the power supply voltage terminal and a MOS transistor whose current value is controlled by the potential of the light receiving element. The light-receiving element circuit described in any one of 1. 12. The inverting circuit according to claim 11, wherein a switching transistor for selecting the inverting circuit is arranged on a higher potential side than a MOS transistor which controls a current value by a potential of a light receiving element. Light receiving element circuit. 13. A threshold voltage of a diode-connected transistor is a threshold voltage of a MOS transistor that controls a current value by a potential of a light receiving element included in an inverting circuit, or a current value is determined by a potential of a light receiving element included in a non-inverting circuit. 13. The light-receiving element circuit according to claim 11, wherein the light-receiving element circuit is matched with any one of threshold voltages of MOS transistors to be controlled. 14. The diode-connected transistor and the non-inverting circuit selecting switching transistor have a gain coefficient larger than that of any other transistor forming the light-receiving element circuit. 2. The light-receiving element circuit according to item 1. 15. A transistor constituting a light receiving element circuit, wherein a value of a gain coefficient ratio with respect to a ratio of current driving capability between the respective transistors has a relation of a ratio of a gate width and a gate length between the respective transistors. 15. The light-receiving element circuit according to claim 13, wherein 16. The light-receiving element circuit according to claim 1, wherein the light-receiving element is a pn photodiode. 17. The pn photodiode has an n-type layer formed on a p-type substrate or has a p-type layer formed on an n-type substrate. Light-receiving element circuit. 18. A switching transistor for resetting the pn photodiode is connected to the n-type layer or the p-type layer of the pn photodiode.
7. The light receiving element circuit described in 7. 19. The doping concentration of the substrate forming the light receiving element and the control circuit is higher than 1 × 10 ¹³ cm ^-3 and 1 × 10 ¹⁶ cm ^-3.
19. The light-receiving element circuit according to claim 16, which is lower. 20. A substrate for forming a light receiving element and a control circuit is a p-type substrate, and the light receiving element forming portion in the p-type substrate has a p-type layer having a doping concentration of 1 × 10 ¹⁵ cm ⁻³ or more and the p-type layer. A light-receiving element having an n-type layer doped at a concentration higher than the doping concentration of the p-type layer, or a substrate forming the light-receiving element and the control circuit is an n-type substrate; The light-receiving element forming portion in the mold substrate is an n-type layer having a doping concentration of 1 × 10 ¹⁵ cm ⁻³ or more and a p-type doped therein with a concentration higher than that of the n-type layer.
20. The light-receiving element circuit according to claim 19, which is a light-receiving element including a mold layer. 21. The light-receiving element circuit according to claim 1, further comprising a capacitor connected in parallel between the light-receiving element and the control circuit, the capacitor storing an output from the light-receiving element. 22. A portion forming a transistor circuit,
22. The light-receiving element circuit according to claim 1, further comprising a metal film. 23. A light-receiving element circuit array, wherein the light-receiving element circuits according to claim 1 are arranged in a one-dimensional or two-dimensional array form. 24. An output of a light-receiving element circuit arranged on one line in the vertical direction with a common switch terminal of the light-receiving element circuits arranged on one horizontal line of a plurality of light-receiving element circuits arranged in an array. 24. The light receiving element circuit array according to claim 23, wherein the terminals are common. 25. A substrate contact for grounding a substrate forming a light receiving element circuit is provided on a ground line in the light receiving element circuit for each light receiving element circuit.
The light receiving element circuit array as described in 3 or 24. 26. A light receiving element circuit comprising a light receiving element and a control circuit for controlling the magnitude and polarity of a signal obtained by converting a potential of the light receiving element into a current and outputting the signal to the outside on a substrate. A circuit (non-inverted output circuit) in which the control circuit controls a current value flowing from the power supply voltage terminal to the output terminal according to the potential of the light receiving element, and an output terminal to the ground terminal depending on the potential from the light receiving element In a method of forming a light receiving element circuit including a circuit (inversion output circuit) formed of a MOS transistor for controlling a flowing out current value, a signal to be output to an outside, that is, an output terminal is selected by selecting the non-inversion output circuit. The first step of measuring or calculating the magnitude of the current and the signal output to the outside by selecting the inverting output circuit, that is, the magnitude of the current flowing from the output terminal are The second step of measuring or calculating, the third step of comparing the results of the first and second steps, and the output signals from the non-inverting output circuit and the inverting output circuit for the same light receiving element potential. A fourth step of controlling at least one of a gain coefficient and a threshold voltage of a MOS transistor constituting the control circuit, an output terminal potential, and a power supply voltage potential so as to have the same size. A method of configuring a light-receiving element circuit, comprising: 27. When the gain coefficient of the MOS transistor constituting the control circuit is selected and set in the fourth step, the gain coefficient of the set MOS transistor is respectively set after the fourth step. M
27. The fifth step of controlling by the ratio of the gate width and the gate length of the OS transistor.
A method of configuring the light receiving element circuit according to. 28. In the fifth step, the gain coefficient of the MOS transistor is set such that the ratio of the ratio of the gate width and the gate length between the transistors to be set is the ratio of the gain coefficient to the ratio of the current driving capability between the transistors. 28. The method for configuring a light-receiving element circuit according to claim 27, further comprising: