JPH08274326A - Semiconductor device - Google Patents

Abstract

PURPOSE: To provide a semiconductor device whose speed is high and which is minute by a method wherein conduction carriers are confined in a one- dimensional slender line. CONSTITUTION: The surface of a silicon substrate 11 has a bend structure in which every bend angle θ12 and every cycle Wp 13 are set, and the width Wc of every channel 16 formed on every protrusion 14 on the surface of the substrate 11 is set at Wp/100<=Wc<=Wp with reference to every bend cycle Wp 13. Since the scattering of conduction carriers is suppressed, it is possible to realize a high-speed and high-gain transistor. In addition, since a drop in a threshold voltage due to a short channel effect is suppressed, the transistor can be subjected to micromachining and integrated highly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device utilizing one-dimensional conduction of carriers.

[0002]

2. Description of the Related Art Advances in hyperfine processing technology have made it possible to realize various artificially controlled structures in a system (mesoscopic system) that is larger than the atomic scale but smaller than the macroscopic scale. It was In such a fine region, the device size approaches the wavelength of the electron, and quantum mechanical properties may start to appear. Therefore, it is expected that a new device will be realized that makes use of this quantum mechanical effect and is ultra-high speed and power saving. A typical structure is a quantum wire that confines electrons in a one-dimensional system. It has been theoretically deduced that in a quantum wire, the degree of freedom in the lateral direction of electron motion disappears, so that elastic scattering such as impurity scattering is suppressed and electron mobility increases. Regarding the increase of electron mobility in this quantum wire, Japanese Journal of Applied Physics, Volume 19 No. 12
(1980) L735 to L738 (Japan
ese Journal of Applied Physics, Vol. 19, No. 12 (1
980) PP. L735-L738).

As a method for realizing such a quantum wire, a conventional device is to form a convex portion having a triangular cross section on the surface of a semiconductor substrate and to form the convex portion as described in Japanese Patent Application Laid-Open No. 2-174268. A device has been known in which a one-dimensional electron is generated at the top of the convex portion while being covered with an inactive film such as a silicon dioxide film. The structure is shown in FIG. Thus, by forming the gate electrode 18 on the top of the triangular convex section 14 on the surface of the semiconductor substrate 11 via the insulating film 17, an extremely narrow channel is formed at the interface of the top of the convex section 14. Therefore, the electrons generated here become one-dimensional electrons and can move at high speed along the top of the convex portion 14.

Further, as described in Japanese Patent Application Laid-Open No. 5-29613, by controlling the amount of resist etch back, a finer gate width can be obtained as compared with a device manufactured by using the above-mentioned photolithography technique. A method for manufacturing a quantum wire device has been known in which the gate electrode is formed on the ridge portion.

[0005]

In the semiconductor device of the above-mentioned prior art, since the electrons are confined in a width similar to that of the gate electrode, there is a problem that the channel width to be formed is restricted by the gate processing technique.

Further, although an extremely high electron mobility can be obtained due to the one-dimensional effect of electrons, the total amount of carriers contributing to the current is reduced, so that the current is higher than that of the conventional planar structure MOS transistor as shown in FIG. There was a fear that the amount would decrease.

Further, it was not clear what kind of drain current characteristic the MOS transistor having the quantum wire structure according to the above-mentioned prior art shows as compared with the conventional planar structure MOS transistor. Furthermore, the short channel characteristics have not been clarified.

An object of the present invention is to realize a high-speed semiconductor device by the one-dimensional effect of conduction carriers and to provide a semiconductor device excellent in current driving force.

It also includes enabling a fine element in which a decrease in threshold voltage due to the short channel effect is suppressed.

[0010]

In order to achieve the above object, in a semiconductor device of the present invention, a semiconductor substrate surface has a structure in which it is periodically bent, and is formed on a convex portion of the substrate surface. The channel width Wc is Wp / 100 ≦ Wc ≦ Wp with respect to the bending period Wp of the substrate surface.

Alternatively, the semiconductor substrate surface has a structure in which the surface is periodically bent, and the width Wc of the channel formed in the convex portion of the substrate surface is the gate electrode width per bending cycle.
It is characterized in that Wg / 100 ≦ Wc ≦ Wg with respect to Wg.

Alternatively, the surface of the semiconductor substrate is periodically bent, and the thickness of the insulating film formed on the upper surface of the convex portion of the substrate surface is equal to the thickness of the insulating film on the upper surface of the concave portion. It is characterized by being thinner than Sa.

Alternatively, the semiconductor substrate has a structure in which the surface thereof is periodically bent, and a high-concentration impurity region of the same type as the substrate impurities is formed in the concave portion of the substrate surface. .

Alternatively, a semiconductor layer is formed on the upper surface of the insulating substrate, and the semiconductor layer has a convex portion with a period Wp, and the width Wc of the channel formed in the convex portion is
The feature is that Wp / 100 ≦ Wc ≦ Wp.

[0015]

According to the present invention, the conductive carrier is confined in the convex portion of the interface of the semiconductor substrate in a one-dimensional thin line shape by the bent structure of the interface between the semiconductor and the insulating film. As a result, carrier scattering is suppressed and the mobility of conductive carriers is improved.
It is possible to realize a transistor that has high speed and excellent current driving force.

Further, due to the bent structure of the semiconductor / insulating film interface, the influence of the drain potential is less likely to reach the source in the short channel, so that the reduction of the threshold voltage due to the short channel effect can be suppressed. Therefore, miniaturization and high integration of transistors can be achieved.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention and a diagram showing its potential distribution. The surface of the p-type silicon substrate 11 has a bending angle θ12 and a period W.
It has a bent structure of p13. Further, the potential is locally high at the interface convex portion 14 of the silicon substrate 11 in a triangular cross section, and is low at the concave portion 15. The channel 16 through which the current flows is formed in the convex portion 14 having a locally high potential. Reference numeral 17 is a gate oxide film, 18 is a gate electrode, and 19 is a channel width Wc. The feature of this embodiment is that the induction of conduction carriers is concentrated on the interface convex portion 14 of the silicon substrate 11, and the width Wc19 of the channel 16 formed in the convex portion 14 on the substrate surface is different from the bending period Wp13. Wp / 100 ≦ Wc ≦ Wp. In this way, by confining the conductive carriers in the convex portions 14 on the surface of the substrate in a one-dimensional thin line, carrier scattering is suppressed, so that a transistor having high speed and excellent current driving capability can be realized. Further, since the threshold voltage is prevented from lowering due to the short channel effect, a fine transistor can be realized.

FIG. 2 shows an external view of a semiconductor device according to an embodiment of the present invention. The surface of the silicon substrate 11 has a bending structure with an angle θ12 and a period Wp13 with respect to the device dimension width 21 direction. Due to this bent structure on the substrate surface, the effective width Weff22 along the substrate surface is 2
When 1 is W, it is expressed by W / (sin (θ / 2)), and 1 /
(sin (θ / 2)) times wider. 17 is a gate oxide film, 1
8 is a gate electrode, 23 is an effective channel length, 24 is a source diffusion layer, and 25 is a drain diffusion layer.

Here, in order to explain this embodiment in detail, FIGS. 8 to 13 show characteristic diagrams of the semiconductor device having the structure of FIG. FIG. 8 is a diagram showing a one-dimensional potential distribution in the depth direction at the center of the gate. Bending angle θ1
2 was 90 °, the bending period Wp13 was 0.1 μm, the thickness of the gate oxide film 17 was 4 nm, the effective channel length 23 was 0.3 μm, the p-type substrate concentration was 3.0 × 10 17 cm −3, and the temperature was 300K. For comparison, the one-dimensional potential distribution of the planar structure MOS transistor shown in FIG. 15 is also shown. When the gate voltage is 0.1 V, the potential of the bent structure is 0.47 V at the point A on the substrate surface of the convex portion 14 and 0.13 V at the point B of the concave portion 15.
1 Due to the bending effect of the surface, the point A of the convex portion 14 is 0.34
V becomes higher. This value is 0.20 V higher in the convex portion 14 than the surface potential of the planar structure MOS transistor,
In addition, the concave portion 15 is lowered by 0.15 V. The increase in the potential at the convex portion 14 due to this bending effect is also reflected in the electron density. The electron density is 6.2 × 1017 cm-3 at the point A on the convex portion 14 and 1.3 × 1012 cm-3 at the point B on the concave portion 15.
The density of the convex portions 14 is 5.0 × 10 5 times higher. The electron density at the convex portion 14 is 1.5 × 10 3 times higher than the electron density of the planar structure MOS transistor of 4.2 × 10 14 cm −3. FIG. 9 shows the electron density distribution in the width direction along the silicon / oxide film interface at the center of the gate. Electron density is 1.
If we consider the part of 0 × 1017 cm-3 or more as the channel inversion layer,
It can be seen that the channel inversion layer is formed in the convex portion 14 with a thickness of 13 nm per cycle (Wp = 100 nm). As described above, in the bent structure, the potential is locally increased in the convex portion 14, and as a result, electrons are confined in a region extremely narrower than the processing size, and a minute fine line channel can be realized. . Therefore, the scattering of electrons is suppressed,
The transistor speed can be increased.

As the substrate concentration increases, the convex portion 1
Since the potential difference between 4 and the recess 15 becomes large, the effect of confining electrons is enhanced. For example, the substrate concentration is 7.0 × 101
The surface potential at 7 cm-3 is at point A on the convex portion 14.
0.53V, 0.09V at the point B of the concave portion 15, and the potential difference between the convex portion 14 and the concave portion 15 is 0.44V. This convex portion 14
And the potential difference between the concave portion 15 and the substrate concentration is 3.0 × 1017c
0.10V larger than when m-3. The electron density is 3.5 × 10 18 cm −3 at point A on the convex portion 14 and 1.6 × 10 at point B on the concave portion 15.
It becomes 11 cm-3, and the convex portion 14 is 2.2 × 10 6 more than the concave portion 15.
Double the density.

FIG. 10 is a diagram showing the gate voltage dependence of the surface potential distribution in the width direction along the silicon / oxide film interface in the gate central part of the semiconductor device having the structure of FIG. For comparison, the surface potential of the planar structure MOS transistor shown in FIG. 15 is shown by a wavy line. When the gate voltage Vg is 0.0V or less, as the gate voltage increases,
The potential difference between the convex portion 14 and the concave portion 15 of the bent structure becomes large, but when the gate voltage becomes 0.0 V or more, the local potential increase at the convex portion 14 becomes gentle as the gate voltage increases. . Thus, the electron confinement effect due to the bent structure is remarkable when the gate voltage is low, and the effect decreases as the gate voltage rises.
Here, it can be seen that the effect is highest near the gate voltage of 0.0V.

FIG. 11 is a characteristic diagram showing the drain current ratio of the transistor having the bent structure of FIG. 2 and the transistor having the conventional planar structure of FIG. Here, the source voltage was 0V and the drain voltage was 1.5V. The drain current of the folded structure with respect to the planar structure is 2 when the gate voltage is 0.05V.
70 times the largest. In other words, the one-dimensional effect of the bent structure is most prominent when the gate voltage is 0.05V. As the gate voltage is increased, the width of the channel inversion layer widens and the conduction of electrons becomes two-dimensional, so the drain current ratio decreases, but even when the gate voltage is 0.8V, which is the saturation region, The drain current of the bent structure is 1.5 times larger than that of the planar structure (W = 10 mm). The current value of the bent structure when the gate voltage is 0.8 V is the effective width Weff22.
Even if it is standardized by, it is about 1.2 times larger than the planar structure. As described above, in the folded structure, not only the current value increases due to the increase in the effective width 22, but also the very high density electrons induced in the convex portion 14 are effective for increasing the current value. To work. Therefore, it is possible to realize a transistor having a better current driving force than ever before. When the gate voltage is further increased, the drain current ratio approaches Yo2, which is a geometrical shape effect caused by bending the substrate surface.

FIG. 12 shows the subthreshold characteristic.
In the bent structure, as shown in FIG. 8, even if the gate voltage is the same, the increase in the potential at the convex portion 14 is larger than that in the conventional planar structure, so that the current starts to flow earlier with respect to the change in the gate voltage. As a result, the threshold voltage of the folded structure is about 0.2V lower than that of the planar structure MOSFET. Also,
The subthreshold swing, which represents the rising characteristics of the current, is 64 mV / decade in the bent structure and 74 mV / decade in the conventional planar structure, and the bent structure has better rising characteristics. This is because when the gate voltage is 0.05 V or less, the potential increase in the convex portion 14 when the gate voltage is changed is larger than the potential increase in the planar structure. (For example, as shown in Figure 10,
When the gate voltage Vg is increased from -0.3V to 0.0V, the potential increase in the convex portion 14 is 0.29V, and the planar structure is 0.24V.
Therefore, the convex portion 14 is larger by 0.05V. )in this way,
In the folded structure, the current rising characteristics are improved, so a high-speed transistor with a high switching speed can be realized.

FIG. 13 shows the relationship between the effective channel length Leff23 and the threshold voltage. Here, the threshold voltage is the gate voltage when the drain current flows 10 nA, and the shift amount of the threshold voltage of the bent structure and the planar structure is the effective channel length L
Each threshold voltage when eff23 was 0.5 μm was used as a reference. The amount of shift of the threshold voltage when the effective channel length 23 is 0.1 μm is −0.11 V in the bent structure compared to −0.22 V in the planar structure, and the threshold voltage of the bent structure is The decrease is suppressed. In the long channel, the potential difference between the convex portion 14 and the planar structure is larger than the potential difference between the concave portion 15 and the planar structure in the long channel, as shown in FIG. This is because the potential difference between the concave portion 15 and the planar structure is larger than the potential difference of 1), and as a result, the influence of the drain potential is less likely to reach the source in the short channel than the planar structure in the entire bent structure. As described above, the transistor of the present invention having the bent structure has
Since it is possible to suppress the decrease in the threshold voltage due to the short channel effect, it is possible to realize a finer and faster transistor than the conventional one.

The embodiments of FIGS. 1 and 2 have been described above with reference to FIGS. 8 to 13. In FIGS. 8 to 13, the bending angle θ12 on the surface of the silicon substrate 11 is 90 °, but as the bending angle θ12 becomes smaller, the electric field is more likely to concentrate on the convex portions 14 and the effect of confining the conduction carriers is enhanced. The most effective confinement effect is the bending angle θ1
It is obtained when 2 is 0 ° <θ <180 °. The bending period Wp13 of the substrate surface 11 is set to 0.1 μm, but 0.01
If .mu.m.ltoreq.Wp.ltoreq.1.0 .mu.m, the potential difference between the convex portion 14 and the concave portion 15 becomes large, and the transistor can be speeded up due to the effect of confining conduction carriers.

Although the n-channel type has been described above as an example, the same can be said for the p-channel type.

Next, an example of a method of manufacturing a semiconductor device according to the embodiment shown in FIGS. The p-type silicon substrate 11 is patterned with a resist and anisotropically etched to form a bent structure having a triangular cross section, and the resist is removed. Here, if the surface orientation of the surface of the silicon substrate 11 is (100), the surface orientation of the ridgeline of the bending structure is (111), and at this time, the bending angle θ12 is about 70.
It becomes °. Next, the surface of the silicon substrate 11 having this bent structure is thermally oxidized to form a gate oxide film 17 on the surface of the substrate 11.
Is grown, and polycrystalline silicon containing impurities, for example, which becomes the gate electrode 18, is deposited as a conductive layer thereon. Then, the gate polycrystalline silicon is removed by etching, and the gate oxide film 17 is removed by etching. Next, the impurity layers to be the diffusion layers 24 and 25 of the semiconductor device are implanted by ion implantation. As a result, the diffusion layers 24 and 25 are joined along the bending of the substrate surface. As described above, the semiconductor device of the present invention is completed.

Here, the source / drain diffusion layers 24,
25 may be formed only on the convex portion 14 on the surface of the silicon substrate 11. If the diffusion layers 24 and 25 are formed only in the convex portion 14, the electrons induced by the rise of the gate voltage become one-dimensional electrons having an extremely narrow width 19 in the convex portion 14, so that a high speed transistor can be realized. .

The transistor of the present invention is a DRA.
It can be incorporated into memory cells such as M and SRAM. When the transistor of the present invention is applied to a memory cell, high speed operation and high integration can be achieved.

FIG. 3 is a diagram showing a cross section of a semiconductor device according to another embodiment of the present invention. A width Wg3 per bending cycle is provided on the convex portion 14 of the silicon substrate 11 having a bending structure with a bending angle θ12 and a cycle Wp13 via an oxide film 17.
The gate electrode 18 having 1 is formed. The channel 16 through which the current flows has a width Wc1 on the convex portion 14 on the surface of the substrate 11.
It is formed with a thickness of 9. The feature of the present embodiment is that the induction of conduction carriers is concentrated on the interface protrusion 14 of the silicon substrate 11, and the width Wc19 of the channel 16 formed in the protrusion 14 on the substrate surface is different from the gate electrode width Wg31. Wg /
It lies where 100 ≦ Wc ≦ Wg. By thus confining the conductive carriers in the convex portions 14 on the surface of the substrate in a one-dimensional thin line, carrier scattering is suppressed, so that a high-speed transistor can be realized and the current driving force is improved. Further, similarly to the embodiments of FIGS. 1 and 2, the reduction of the threshold voltage due to the short channel effect can be suppressed, so that a fine and highly integrated device can be realized.

4 and 5 are sectional views showing a semiconductor device according to another embodiment of the present invention. Bending angle θ
12, an oxide film 14 having a non-uniform thickness is deposited on the surface of a silicon substrate 11 having a bent structure with a period Wp13. Here, the oxide film 14 is thin in the convex portion 14 and thick in the concave portion 15. The feature of this embodiment lies in that the thickness of the oxide film 16 formed on the upper surface of the convex portion 14 of the silicon substrate 11 having the bent structure is thinner than the thickness of the oxide film 16 on the upper surface of the concave portion 15. . As a result, the silicon substrate 1
Since the electric field is easily concentrated in the convex portion 14 of No. 1, conduction carriers are confined in the convex portion 14 in a one-dimensional manner, a high-speed transistor can be realized, and the current driving force is improved. Further, similarly to the embodiments of FIGS. 1 and 2, the reduction of the threshold voltage due to the short channel effect can be suppressed, so that a fine and highly integrated device can be realized.

FIG. 6 is a diagram showing a cross section of a semiconductor device according to another embodiment of the present invention. The surface of the silicon substrate 11 has a bending structure with a bending angle θ12 and a period Wp13, and a high-concentration impurity 61 of the same type as the substrate impurities is implanted into the surface recess 15 of the substrate 11. The feature of this embodiment is that the high-concentration impurity 61 is locally implanted in the recess 15 on the silicon substrate 11. As a result, the electric field is easily concentrated on the convex portions 14 of the silicon substrate 11, so that the conductive carriers are easily induced in the convex portions 14 in a one-dimensional manner, and a high-speed transistor can be realized and the current driving force can be increased. improves. Further, similarly to the embodiments of FIGS. 1 and 2, the reduction of the threshold voltage due to the short channel effect can be suppressed, so that a fine and highly integrated device can be realized.

FIG. 7 is a diagram showing a cross section of a semiconductor device according to another embodiment of the present invention. A semiconductor layer 72 is formed on the upper surface of the insulating substrate 71, and the semiconductor layer 72 has an angle θ1.
2, it has a convex shape with a period Wp13. The feature of this embodiment is that the induction of conduction carriers is concentrated in the convex portion 14 of the semiconductor layer 72 and the width Wc of the channel 16 formed in the convex portion 14 is increased.
Is Wp / 100 ≦ Wc ≦ Wp for the convex period Wp13. By thus confining the conductive carriers in the convex portions 14 on the surface of the substrate in a one-dimensional thin line, carrier scattering is suppressed, so that a high-speed transistor can be realized and the current driving force is improved. Further, similarly to the embodiments of FIGS. 1 and 2, the reduction of the threshold voltage due to the short channel effect can be suppressed, so that a fine and highly integrated device can be realized.

[0034]

According to the present invention, by confining the conductive carriers in a one-dimensional thin line, carrier scattering is suppressed and the mobility of the conductive carriers is improved, so that a high-speed transistor can be realized and the current driving force can be realized. Can be improved. Further, the bent structure of the interface between the semiconductor and the insulating film suppresses the decrease in the threshold voltage due to the short channel effect, which enables miniaturization and high integration of the transistor.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is an external view showing an embodiment of a semiconductor device according to the present invention.

FIG. 3 is a diagram showing another embodiment of the semiconductor device according to the present invention.

FIG. 4 is a diagram showing another embodiment of the semiconductor device according to the present invention.

FIG. 5 is a diagram showing another embodiment of the semiconductor device according to the present invention.

FIG. 6 is a diagram showing another embodiment of the semiconductor device according to the present invention.

FIG. 7 is a diagram showing another embodiment of the semiconductor device according to the present invention.

FIG. 8 is a characteristic diagram showing a one-dimensional potential distribution in the depth direction for explaining the present invention.

FIG. 9 is a characteristic diagram showing the electron density distribution in the width direction along the surface of the silicon substrate at the center of the gate for explaining the present invention.

FIG. 10 is a characteristic diagram showing a potential distribution in the width direction for explaining the present invention.

FIG. 11 is a characteristic diagram showing gate voltage dependence of drain current.

FIG. 12 is a characteristic diagram showing the drain current ratio of the transistor of the present invention to the drain current of a conventional planar structure MOS transistor.

FIG. 13 is a characteristic diagram showing the effective channel length dependence of the threshold voltage.

FIG. 14 is an external view showing a conventional quantum wire transistor.

FIG. 15 is an external view showing a conventional planar structure MOS transistor.

[Explanation of symbols]

11 ... Silicon substrate, 12 ... Bending angle θ, 13 ... Bending structure period Wp, 14 ... Convex portion, 15 ... Recessed portion, 16 ... Channel, 17 ... Oxide film, 18 ... Gate electrode, 19 ... Channel width Wc, 21 ... Device width W, 22 ... Effective width Wef
f, 23 ... Effective channel length, 24 ... Source diffusion layer, 25
... Drain diffusion layer, 31 ... Gate electrode width Wg per bending cycle, 61 ... High concentration impurity of the same type as the substrate impurity, 7
1 ... Insulating substrate, 72 ... Semiconductor layer, 141 ... Source electrode,
142 ... Drain electrode.

Claims (10)

[Claims] 1. The semiconductor substrate has a structure in which the surface is bent periodically, and the width Wc of the channel formed in the convex portion of the substrate surface is Wp with respect to the bending cycle Wp of the substrate surface. /
A semiconductor device characterized in that 100 ≦ Wc ≦ Wp. 2. The semiconductor substrate has a structure in which the surface is periodically bent, and the width Wc of the channel formed in the convex portion of the substrate surface is relative to the gate electrode width Wg per bending cycle. And Wg / 100 ≦ Wc ≦ Wg. 3. The semiconductor substrate has a structure in which the surface is periodically bent, and the thickness of the insulating film formed on the upper surface of the convex portion of the substrate surface is the thickness of the insulating film on the upper surface of the concave portion. A semiconductor device characterized by being thinner than the thickness. 4. A semiconductor device having a structure in which a surface of a semiconductor substrate is periodically bent, and a high-concentration impurity region of the same type as a substrate impurity is formed in a concave portion of the substrate surface. . 5. The semiconductor device according to claim 1, wherein an angle θ formed by a ridgeline of a convex portion on the surface of the semiconductor substrate is 0 ° <
A semiconductor device characterized in that θ <180 °. 6. The semiconductor device according to claim 1, wherein the bending period Wp of the semiconductor substrate surface is 0.01 μm ≦ Wp ≦ 1.
A semiconductor device having a thickness of 0 μm. 7. A semiconductor layer is formed on an upper surface of an insulating substrate, and the semiconductor layer has a convex portion having a period Wp, and a width Wc of a channel formed in the convex portion is equal to a period Wp. Wp / 100
A semiconductor device characterized in that ≦ Wc ≦ Wp. 8. The semiconductor device according to claim 7, wherein the angle θ formed by the ridgelines of the protrusions of the semiconductor layer on the insulating substrate is 0 ° <
A semiconductor device characterized in that θ <180 °. 9. The semiconductor device according to claim 7, wherein the bending period Wp of the semiconductor layer on the insulating substrate is 0.01 μm ≦.
A semiconductor device characterized in that Wp ≦ 1.0 μm. 10. A semiconductor device comprising a combination of the semiconductor device according to claim 1 and a charge storage capacitor.