JPH08274253A - Module wiring board and memory module constituted by using the board - Google Patents

Abstract

PURPOSE: To accomplish the same efficiency as in the module using a semiconductor device of a perfect article, without generation of access delay using a semiconductor device of incomplete article. CONSTITUTION: On lands 3a to 3d and 4a to 4d on which memory I/O pins are mounted, the lands 3a, 3c, 3d, 4a to 4c on the positions where two each of them are mounted from the end part of a module board 2, are connected to a module I/O terminal 5, the lands 3c and 4d are connected to a land 7, and a land 7a is connected to power source voltage. Other lands 3a, 3c, 3d and 4a to 4c are connected to the module I/O terminal 5, and the lands 3c and 4d are connected to a land 8a. When the lands 3c and 4a are pulled up, a resistor is mounted on lands 8a and 8b, a jumper is mounted on lands 8 and 8a for connection of the lands 3c and 4d to the module I/O terminal 5, and the defective I/O pin only is selectively brought into an electrically fixed state by changing the mounting lands 3 and 4, and also by mounting and dismounting the resistor or the jumper.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a module wiring board and a memory module constructed using the same.
In particular, the present invention relates to a technique effectively applied to the configuration of a memory module including a semiconductor device having a defective bit.

[0002]

2. Description of the Related Art According to a study made by the inventor of the present invention, when a non-defective non-defective memory having a defective bit is used in a memory module, the upper address of the memory is controlled by a gate array or the like, and It is utilized by using only the area.

Incidentally, as an example in which this type of module substrate is described in detail, the Industrial Research Institute Co., Ltd., 19
There is "Hybrid IC Technology" P79-P83, Electronic Materials Editing Department (ed.), Issued June 1, 1984.
The mounting technology in the hybrid IC is described.

[0004]

However, the present inventor has found that the above-described method of utilizing the non-perfect non-defective memory has the following problems.

That is, since address control is performed by a gate array or the like, an access delay occurs, resulting in a problem that the performance is inferior to that of a perfectly good product.

Further, since only the upper address of the memory is controlled, there is a problem that the usable memory is less than half of the completely non-defective memory.

An object of the present invention is to provide a module wiring board which can achieve the same performance as a module using a perfectly good semiconductor device without causing access delay by using an imperfectly good semiconductor device. It is to provide a memory module configured by using the memory module.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, in the module wiring board of the present invention, a predetermined input / output terminal which is defective in the input / output terminal provided in the semiconductor device is connected to the connecting portion on which the semiconductor device is mounted, and the semiconductor device is electrically connected. A first connection part in a fixed state and a second connection part to which a non-defective input / output terminal is connected and which is connected to a predetermined input / output part in the module wiring board are provided. The module constitutes a module equivalent to the module constituted by.

Further, the module wiring board of the present invention comprises 1
Providing two or more of the connection parts on which individual semiconductor devices are mounted,
The first connection part, which is in an electrically fixed state, is provided differently depending on the position of the semiconductor device mounted on the connection part.

Further, the module wiring board of the present invention is
The electrically fixed state of the first connecting portion is pull-up, pull-down or non-connect.

Further, the module wiring board of the present invention is electrically connected to the power supply voltage or the ground potential and the third connection portion electrically connected to the first connection portion or the second connection portion. A fourth connection portion and a fifth connection portion electrically connected to a predetermined input / output portion provided on the module wiring board are provided, and between the third connection portion and the fourth connection portion or The wiring path is switched by selectively attaching and detaching the first conducting means between the third connecting portion and the fifth connecting portion.

Further, the module wiring board of the present invention is
The first conducting means is a jumper or a resistor.

Further, the module wiring board of the present invention is
Six or more connection parts in which one semiconductor device is mounted, and a predetermined input / output terminal which is defective in the input / output terminal provided in the semiconductor device is connected to the connection part and the connection part. An eighth connecting portion electrically connected to a seventh connecting portion to which a non-input / output terminal is connected, a ninth connecting portion electrically connected to a power supply voltage or a ground potential, and a module wiring board. A tenth connecting portion electrically connected to the predetermined input / output portion provided, and between the eighth connecting portion and the ninth connecting portion or between the eighth connecting portion and the tenth connecting portion. A state in which the sixth connecting portion is electrically fixed by selectively attaching and detaching the second conducting means between the switch and the wiring path or changing the position of the semiconductor device mounted on the connecting portion. As a module composed of completely good semiconductor devices. It constitutes a Le equivalent modules.

Further, the module wiring board of the present invention is
The electrically fixed state of the sixth connecting portion is
Pull-up, pull-down or non-connect,
The second conducting means is a jumper or a resistor.

The memory module of the present invention is constructed by using the module wiring board.

[0018]

According to the above-described module wiring board of the present invention, the predetermined connection which is defective in the first connecting portion which is either pull-up, pull-down or non-connect and the input / output terminal provided in the semiconductor device is provided. By connecting the output terminal and the other non-defective input / output terminal to the second connecting portion of the module wiring board, the defective input / output terminal of the semiconductor device is electrically fixed. It is possible to eliminate the unstable operation of the semiconductor device and form a module equivalent to a module including a completely good semiconductor device.

Further, according to the above-described module wiring board of the present invention, the first connecting portion which is electrically fixed to each of the two or more connecting portions on which one semiconductor device is mounted is provided. By changing the position of the semiconductor device provided and mounted, the input / output terminal which is electrically fixed can be changed flexibly.

Further, according to the above-described module wiring board of the present invention, the third connection portion electrically connected to the first connection portion or the second connection portion and the power supply voltage or the ground potential are electrically connected. The first connecting portion is connected between the connected fourth connecting portion or the third connecting portion and a fifth connecting portion electrically connected to a predetermined input / output portion provided on the module wiring board. By selectively attaching or detaching the resistor or the jumper as the conducting means, it is possible to flexibly change the connection destination of the defective input / output terminal and the non-defective input / output terminal of the semiconductor device.

Further, according to the above-described module wiring board of the present invention, the first connection portion, which is electrically fixed to each of the two or more connection portions provided with one semiconductor device, is provided. Changing the position of a semiconductor device to be mounted and mounted, and connecting an eighth connection portion electrically connected to the sixth connection portion or the seventh connection portion and a eighth connection portion electrically connected to the power supply voltage or the ground potential. The second connecting means is between the ninth connecting portion or between the eighth connecting portion and the tenth connecting portion electrically connected to a predetermined input / output portion provided on the module wiring board. The connection destination of the defective input / output terminal and the non-defective input / output terminal of the semiconductor device can be changed more flexibly by the combination of selectively attaching and detaching the resistor or the jumper.

Accordingly, by configuring a memory module using the module wiring board, a module equivalent to a module configured by a perfectly good memory can be obtained even if a memory having a defective bit such as a DRAM semiconductor device is used. Can be configured.

[0023]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a plan view of a module substrate according to Embodiment 1 of the present invention, FIG. 2 is a block diagram diagram comparing module configurations according to Embodiment 1 of the present invention, and FIG. FIG. 4 is a block diagram diagram of a module configuration according to a first embodiment of the invention, and FIG.
5 is a conceptual diagram of the wiring of the module substrate according to the first embodiment of the present invention, FIG. 6 is a mounting diagram of the module substrate according to the first embodiment of the present invention, and FIG.
FIG. 8 is a block diagram diagram comparing the module configurations according to the first embodiment of the present invention. FIG. 8 is a block diagram diagram of the module configurations according to the first embodiment of the present invention.
0 is a mounting diagram of the module substrate according to the first embodiment of the present invention, FIG. 11 is a conceptual diagram of connection of the module substrate according to the first embodiment of the present invention, and FIG. 12 is a mounting state of the module substrate according to the first embodiment of the present invention. 13 and 14 show a first embodiment of the present invention.
FIG. 6 is a pin arrangement diagram of a memory mounted on the module substrate according to the above.

In the first embodiment, for example, SOJ (S
A module board (module wiring board) 2 of a double-sided board on which a memory 1 which is a semiconductor device such as a dynamic memory (hereinafter referred to as DRAM) shown in FIG. As shown in FIG. 1, six memories 1 are mounted on the front surface 2a and the back surface 2b of the module substrate 2 vertically in the longitudinal direction of the module substrate 2.

Lands (connection portions) 3 for electrically connecting the pins of the memory 1 are formed on the front surface 2a and the back surface 2b of the module substrate 2, and mounting positions are provided in the vicinity of the lands 3. Memory 1 by shifting
A land (connecting portion) 4 for mounting is formed.

Therefore, the lands 3 and 4 for mounting the six memories 1 are formed on the front surface 2a of the module substrate 2.
In addition, it is provided on the back surface 2b.

Further, on one of the long sides of the module substrate 2, for example, 72 module I / O terminals (input / output portions) 5 are provided along the longitudinal direction of the module substrate 1.

On the module substrate 2, wiring patterns 6, lands (eighth connection portions) 7 and 8a on which resistors and jumpers, which are chip components described later, are mounted, lands (nine connection portions) 7a, 8b and a land (tenth connection portion) 8 are formed, and the lands 3, 4, 7, 7a, 8, 8a, 8b and the module I / O terminal 5 are electrically connected to a predetermined connection destination by the wiring pattern 6. Connected to each other.

The lands 7 and the lands 7a are provided at predetermined positions on the module substrate 2 at intervals where resistors, which are chip components, are mounted.

Further, the lands 8, 8a, 8b are provided so that their respective positions are equidistant with respect to the land 8a, and the distance is either the land 8 and the land 8a or the land 8a and the land 8b. A resistor or jumper is mounted between the two.

In the first embodiment, the I / O pin (input / output terminal) 1 which is the I / O terminal of the memory 1 shown in FIG.
a to 1d mounted lands (seventh connection portion) 3a, 3
b, 3d, land (sixth connection portion) 3c, and lands (seventh connection portion) 4a to 4c, land (sixth connection portion)
Connection destinations by the wiring pattern 6 other than 4d are not shown.

Further, in the module substrate 2, among the I / O pins 1a to 1d of the memory 1, the land 3a and the land 4a corresponding to the position where the I / O pin 1a is mounted are electrically connected by the wiring pattern 6. Connected to each other.

Further, in the module substrate 2, the land 3b and the land 4b to which the I / O pin 1b of the memory 1 is electrically connected are also electrically connected by the wiring pattern 6.

The land 3a and the land 4a and the land 3b and the land 4b which are connected by the wiring pattern 6 are connected.
Is a predetermined module I depending on the wiring pattern 6, respectively.
It is connected to the / O terminal 5.

Next, the land 3 on the module substrate 2
The c is connected to the land 4d located on the diagonal side thereof by the wiring pattern 6.

The lands 3c and 4d connected by the wiring pattern 6 are connected by the wiring pattern 6 to one land 7 to which a resistor which is a chip component is connected, and the other land 7a is a module I / O. The wiring pattern 6 is connected to a predetermined terminal to which the power supply voltage Vcc at the terminal 5 is supplied.

Further, in the lands 3 and 4 for mounting the two memories 1 from the right end and two from the left end of the module substrate 2, the I / O pins 1c and 1d of the memory 1 are mounted.
The land 3d and the land 4c, which are the positions where the
It is electrically connected by the wiring pattern 6 and is connected to a predetermined terminal in the module I / O terminal 5.

Further, in the lands 3 and 4 for mounting the two memories 1 located in the vicinity of the central portion of the module board 2, the lands 3d and the lands where the I / O pins 1c and 1d of the memory 1 are mounted. 4c is connected to the land 8a located at the center of the lands 8 to 8b provided at equal intervals by the wiring pattern 6.

In the lands 8 and 8b, one land 8 is connected to a predetermined terminal in the module I / O terminal 5, and the other land 8b has a power supply voltage Vcc in the module I / O terminal 5. The wiring pattern 6 is connected to a predetermined terminal to be supplied.

Here, the case where the module substrate 2 constitutes a memory module of 4M words × 32 bits will be described.

First, a block diagram in the case where a memory module of 4 M words × 32 bits is constituted by eight memories DM which are 4 M words × 4 bits DRAM semiconductor devices is as shown in FIG.

For example, in order to configure a memory module of 4M words × 32 bits with a non-perfect non-defective memory, one of 4M words × 4 bits is defective 4 bits.
It is possible to configure eight M words × 3 bits of memory 1 and four 4 M words × 2 bits of memory 1 having a defective 2 bits, and this configuration is shown in a block diagram in FIG. Becomes

The memory 1 mounted on the module board 2 is preliminarily selected and grouped.
In the memory 1 having a 1-bit defect, one of the I / O pins 1c and 1d in the memory 1 has a defect, and
It is assumed that the memory 1 having a defective bit has defective I / O pins 1c and 1d.

Then, eight 1-bit defective memories 1
Is the front surface 2a and the back surface 2b of the module substrate 2.
2 from the right end and the left end of the module board 2, respectively.
They are mounted one by one, and in the vicinity of the central part of the module substrate 2,
Two 2-bit defective memories 1 are mounted on each of the front surface 2a and the back surface 2b.

Here, in the memory 1 having a 1-bit defect, for example, the memory 1 having a defective I / O pin 1c.
When the groups are mounted on the module substrate 2, the resistors are mounted on the lands 7 and 7a.

Then, the I / O pin 1c is connected to the land 3c which is pulled up via a resistor, that is,
All the memories 1 are mounted at the positions of the lands 3.

The two memories 1 having a 2-bit defect mounted near the central portion of the module substrate 2 are I / O pins 1.
Since c and 1d are defective and the memory 1 is mounted at the position of the land 3 as described above, the land 8a,
By mounting a resistor on 8b, the defective pin I /
The O pins 1c and 1d are pulled up via a resistor.

The module board 2 on which the resistor (second conducting means) R and the memory 1 are mounted has an appearance as shown in FIG. 4, and all the resistors R on the module board 2 are mounted when the memory 1 is mounted. Will be.

Therefore, in this module substrate 2, as shown in FIG. 5, the defective I / O pin 1c is pulled up by the resistor R in the 1-bit defective memory 1 and the 2-bit defective memory 1 is pulled up. , Defective I /
The O pins 1c and 1d are pulled up by the resistor R, and the other I / O pins 1a and 1b are connected to the module I / O terminal 5.
Will be connected to a predetermined terminal in.

Next, in the configuration according to the block diagram shown in FIG. 3, the memory 1 in which the I / O pin 1d is defective and the memory 1 in which both the I / O pins 1c and 1d are defective are grouped in advance. The case will be described.

Here, the memory 1 having a 1-bit defect is shown in FIG.
On the front surface 2a and the back surface 2b of the module board 2 shown in FIG. 2, two pieces each are mounted from the right end and the left end of the module board 2 in the same manner as described above, and two 2-bit defective memories 1 are provided near the central part of the module board 2. Are implemented one by one.

Further, in the memory 1 having a 1-bit defect,
For example, when the memories 1 having defective I / O pins 1d are grouped and mounted on the module substrate 2,
Resistors are mounted on the lands 7, 7a.

Then, the I / O pin 1d is connected to the land 4d which is pulled up via a resistor, that is,
All the memories 1 are mounted at the positions of the lands 4.

Further, two memories 1 each having a 2-bit defect mounted near the central portion of the module substrate 2 are I / O.
Since the pins 1c and 1d are defective, by mounting resistors on the lands 8a and 8b, the defective pins I / O pins 1c and 1d are pulled up via the resistors.

Therefore, as shown in FIG. 6, the module substrate 2 has an appearance in which the resistor R is mounted on the lands 8a and 8b and the memory 1 is mounted on the land 4.

Next, using this module substrate 2, 4M
A case of forming a word × 36-bit memory module will be described.

First, a memory module of 4 M words × 36 bits is provided with eight memories 4 M words × 4 bits, which are DRAM semiconductor devices, and four 4 M words × 4.
A block diagram in the case of the memory DM1 which is a bit DRAM semiconductor device has a structure as shown in FIG.

Here, in order to configure a memory module of 4M words × 36 bits with a non-perfect non-defective memory, 4M words × 4 bits, one of which is defective, is 4M.
It is possible to configure 12 words × 3 bits of memory 1,
This structure is shown in a block diagram as shown in FIG.

The memory 1 mounted on the module substrate 2 is preliminarily selected and grouped in the same manner as described above, and the memory 1 having a 1-bit defect is the I / O pins 1c and 1d in the memory 1. It is assumed that any one of them becomes defective.

The 1-bit defective memory 1 is mounted on the module substrate 2 in the same manner as described above.
In the memory 1 having a 1-bit defect, when the memory 1 having the defective I / O pin 1c is grouped, the resistor R is mounted on the lands 7 and 7a.

All the memories 1 are mounted so that the I / O pin 1c is connected to the land 3c pulled up via the resistor R, that is, at the position of the land 3.

Also, in the two memories 1 mounted in the vicinity of the central portion of the module substrate 2, only the I / O pins 1c are defective, so that jumpers (second ones) are formed on the lands 8, 8a (FIG. 1).
Of the module I, and connect the I / O pin 1d to the module I.
A connection is made to a predetermined terminal in the / O terminal 5.

As shown in FIG. 9, the module substrate 2 has jumpers (second conducting means) J on the lands 8 and 8a.
Is mounted, and the memory 1 has the appearance of being mounted on the land 3.

Therefore, in this module board 2, as shown in FIG. 10, the defective I / O pin 1c is pulled up by the resistor R and the other I / O pins 1a, 1 are connected.
b and 1d are connected to predetermined terminals in the module I / O terminal 5.

Next, a description will be given of a case where the memory 1 having a defective I / O pin 1d is selected and grouped in advance in the configuration according to the block diagram shown in FIG.

First, the memory 1 having the defective I / O pin 1d is grouped and the module substrate 2 shown in FIG.
When mounted on the I / O pin 1d, a resistor is mounted on the lands 7 and 7a to pull up the I / O pin 1d.
Is connected to the land 4d that is pulled up via a resistor, that is, all the memories 1 are mounted at the position of the land 4.

Also, since the two memories 1 mounted in the vicinity of the central portion of the module board 2 are defective only in the I / O pin 1d, jumpers are mounted on the lands 8 and 8a to make the I / O.
The pin 1c is connected to a predetermined terminal in the module I / O terminal 5.

As shown in FIG. 11, the module board 2 has an appearance in which the jumper J is mounted on the lands 8 and 8a and the memory 1 is mounted on the land 4.

When mounting the memory 1 having the defective I / O pin 1c and the memory 1 having the defective I / O pin 1d, the left and right positions of the memory 1 are shifted as shown in FIG. To do.

Further, the I / O pins 1a and 1b of the memory 1 are
Is defective, the lands 4c and 4d in the module substrate 2 shown in FIG. 1 are connected to predetermined terminals in the module I / O terminal 5, and the lands 4a and 4b are connected to predetermined destinations via resistors or jumpers. A module substrate (not shown) to be connected may be prepared.

As a result, according to the first embodiment, the defective pins of the I / O pins 1a to 1d are pulled up via the resistor R simply by mounting the non-perfect non-defective memory 1 grouped on the module substrate 2. Defective pin 1a
The memory 1 can be stably operated without being affected by 1d.

Further, since the address control is unnecessary, it is possible to have the same function and performance as the memory module using the perfectly good memory 1.

Further, by changing the mounting position of the memory 1 and attaching / detaching the resistor R and the jumper J, it is possible to flexibly change the position of the defective pin to be pulled up while reducing the number of resistors R and the jumper J used.

(Second Embodiment) FIG. 14 shows a second embodiment of the present invention.
15 is a schematic wiring diagram of the module substrate according to the second embodiment of the present invention, and FIGS. 16 and 17 are plan views of the module substrate according to the second embodiment of the present invention.

In the second embodiment, the front surface 9a and the back surface (not shown) of the module board (module wiring board) 9 of the double-sided board on which the memory 1 (embodiment 1, FIG. 13) which is a DRAM semiconductor device is mounted. , As shown in FIG.
Lands (connecting portions) 10 for electrically connecting the respective pins of the memory 1 are formed so that the six memories are mounted vertically in the longitudinal direction of the module substrate 9.
In the vicinity of the lands 10, lands (connection portions) 11 for mounting the memory 1 are formed by shifting the positions.

Further, in these lands 10 and 11, on the module substrate 9, the lands (second connecting portions) 10a to 10d are connected to the positions where the I / O pins (input / output terminals) 1a to 1d of the memory 1 are connected. 10c, land (first connecting portion) 10d, and land (second connecting portion) 11a, 1
1b, 11d and a land (first connection portion) 11c are provided.

Further, on one of the long sides of the module substrate 9, for example, 72 module I / O terminals (input / output portions) 5 are provided along the longitudinal direction of the module substrate 1.

Then, in the module substrate 9, the lands 10a and the lands 11a are electrically connected by the wiring pattern 6 and are connected to predetermined terminals of the module I / O terminal 5.

In addition, the land 1 on the module substrate 9
0b and the land 11b are also electrically connected by the wiring pattern 6 and are connected to predetermined terminals of the module I / O terminal 5.

Further, the land 10c is electrically connected to the land 11d by a wiring pattern 6, and these lands 10c and 11d are connected to a predetermined terminal of the module I / O terminal 5 by the wiring pattern 6.

The land 10d is electrically connected to the land 11c by a wiring pattern 6, and the wiring pattern 6 is one of the lands on which a resistor (first conduction means) (not shown) which is a chip component is mounted. (Not shown), and the other land is connected to a predetermined terminal of the module I / O terminal 5 to which the power supply voltage Vcc is supplied.

Further, also in the second embodiment, the I / O of the memory 1 is
Connection destinations by the wiring pattern 6 other than the lands 10a to 10d and the lands 11a to 11d on which the I / O pins 1a to 1d which are O terminals are mounted are not shown.

The memory 1 mounted on the module substrate 9 is preselected and grouped as in the first embodiment, and the I / O pin 1 in the memory 1 is selected.
It is assumed that either c or 1d is defective.

Further, the above-mentioned lands 10a to 10d,
A schematic representation of 11a to 11d and the wiring pattern 6 is as shown in FIG. 15, and the lands 10a, 10b, 10 are shown.
d, 11a, 11b and 11c are module I / O terminals 5
And the lands 10c and 11d are pulled up.

Then, using this module substrate 9,
To configure a memory module having a 4M word × 36 bit structure with a non-perfect non-defective memory, for example, among 4M word × 4 bits, one bit is defective 4M word × 3
Twelve bit memories 1 can be configured.

For example, when the memory 1 having the defective I / O pin 1c is grouped, the I / O pin 1c
The memory 1 is mounted so that c is connected to the land 11c that is pulled up via a resistor, that is, at the position of the land 11.

If the memory 1 having the defective I / O pin 1d is previously selected and grouped, I / O
Land 10 whose O pin 1d is pulled up through a resistor
The memory 1 is mounted so as to be connected to d, that is, at the position of the land 10.

As a result, even in the second embodiment, the defective pins of the I / O pins 1a to 1d are pulled up through the resistors only by mounting the non-perfect non-defective memory 1 on the module substrate 9. The memory 1 can be stably operated without being affected by the pins.

Further, together with the module substrate 9, FIG.
6, the I / O pins 1a and 1b are defective by using the module substrate (module wiring board) 12 on which the memory 1 having either one of the I / O pins 1a and 1b defective is grouped and mounted. It is possible to use both the memory 1 that has become defective or the memory 1 that has defective I / O pins 1c and 1d.

Also in this case, the lands (connecting portions) 13, so that six memories are mounted vertically on the both surfaces of the module substrate 12 in the longitudinal direction of the module substrate 9, respectively.
14 are formed, and lands 13a to 13d and lands 14 are formed at the positions where the I / O pins 1a to 1d of the memory 1 are connected.
a to 14d are provided.

Then, in the module substrate 12, the lands (second connecting portions) 13a, 13c, 13d, 14 are formed.
b, 14c and 14d are electrically connected to a predetermined terminal of the module I / O terminal 5 by the wiring pattern 6.

Further, the lands (first connecting portions) 13b, 1
4a is electrically connected to the land 11d by the wiring pattern 6, and these lands 13b and 14a are connected to one land (not shown) on which a resistor (not shown) which is a chip component is mounted. The other land is connected to a predetermined terminal of the module I / O terminal 5 to which the power supply voltage Vcc is supplied.

Also, as shown in FIG. 17, I / O pin 1
Module board (module wiring board) for alternately mounting the memory 1 in which one of a and 1b is defective and the memory 1 in which one of the I / O pins 1c and 1d is defective
Also by using 15, both the memory 1 in which the I / O pins 1a and 1b are defective or the memory 1 in which the I / O pins 1c and 1d are defective can be used.

In this case as well, the lands (second connecting portions) 16a to which the I / O pins 1a to 1d in the memory 1 of the lands (connecting portions) 16 and 17 formed on both surfaces of the module substrate 15 are similarly connected. 16c, 17a, 17b, 17
d, land (second connecting portion) 16a ₁ , 16c ₁ , 16d ₁ ,
17b _{1 to} 17d ₁ , a land (first connecting portion) 16d,
17c and land (first connecting portion) 16b ₁ and 17a ₁
, The lands 16b ₁ and 17a ₁ that pull up either of the defective I / O pins 1a and 1b and the lands that pull up any of the defective I / O pins 1c and 1d (second
16d and 17c are alternately provided.

(Third Embodiment) FIG. 18 shows a third embodiment of the present invention.
Module board mounting diagram by
Is a schematic wiring diagram of the module substrate according to the third embodiment of the present invention, and FIGS. 20 and 21 are mounting diagrams of the module substrate according to the third embodiment of the present invention.

In the third embodiment, as shown in FIG. 18, a module substrate 18 of a double-sided board on which the memory 1 (embodiment 1, FIG. 13) which is a DRAM semiconductor device is mounted has six memories each as a module. Lands for electrically connecting the respective pins of the memory 1 are formed so as to be mounted vertically in the longitudinal direction of the substrate 18.

Further, on one of the long sides of the module board 18, for example, 72 module I / O terminals (input / output portions) 5 are provided along the longitudinal direction of the module board 18.

On the module substrate 18, of the I / O pins (input / output terminals) 1a to 1d of the memory 1, I
In the vicinity of the lands at the positions where the / O pins 1a and 1b are respectively connected, connection destination switching lands (fourth connection portion) 19, 20 and lands (third connection portion) 19a,
20a and lands (fifth connecting portions) 19b and 20b are provided.

These lands 19 to 19b and 20 to 20b
The lands 19 to 19b and the lands 20 to 20b make up one set each, and one set is provided for each of the I / O pins 1a and 1b.

Further, the lands 19 to 19b and 20 to 20b
Are arranged at equal intervals, and the intervals are
The intervals are such that the resistors (first conducting means) or jumpers (first conducting means) that are chip components are mounted.

Further, in the lands 19 to 19b, the lands 19a arranged at the center of the lands 19 to 19b arranged at equal intervals are electrically connected to the lands connected to the I / O pins 1a by the wiring pattern 6. Connected to each other.

The land 19 is electrically connected to the power supply voltage Vcc by the wiring pattern 6, and the land 19b is electrically connected to a predetermined module I / O terminal 5 by the wiring pattern 6.

Also in the lands 20 to 20b,
The lands 20a arranged at the center of the lands 20 to 20b arranged at equal intervals are electrically connected to the lands connected to the I / O pins 1b by the wiring pattern 6.

The land 20 is electrically connected to the power supply voltage Vcc by the wiring pattern 6, and the land 20b is electrically connected to a predetermined module I / O terminal 5 by the wiring pattern 6.

In the third embodiment also, the I / O of the memory 1 is
Connection destinations by the wiring pattern 6 other than lands on which the I / O pins 1a to 1d which are terminals are mounted are not shown.

Here, a schematic representation of the connection by the above-mentioned chip parts is as shown in FIGS. 19 (a) and 19 (b),
If the I / O pin 1c is defective, a resistor is connected to the I / O pin 1c, and a jumper is connected to the I / O pin 1d. If the I / O pin 1d is defective, the jumper is connected to the I / O pin 1c. , I
A resistor is connected to the / O pin 1d.

Lands 10a, 10b, 10d, 11a,
11b and 11c are connected to the module I / O terminal 5,
The lands 10c and 11d are pulled up.

Using this module substrate 18, for example, to configure a memory module of 4 M words × 36 bits by a non-perfect non-defective memory, 4 M words × 4 bits, one bit of which is defective 4 M words × 3
Twelve bit memories 1 can be configured.

Further, the memory 1 mounted on the module substrate 18 is preliminarily selected and grouped similarly to the first and second embodiments, and the I / O in the memory 1 is
It is assumed that one of the O pins 1a and 1b is defective.

For example, when the memory 1 having a defective I / O pin 1a is grouped, the I / O pin 1a
A resistor is mounted between the land 19a connected to the land where a is located and the land 19 connected to the power supply voltage Vcc, and the I / O pin 1a is pulled up.

The I / O pin 1b, which is a non-defective product, has a jumper mounted between the land 20a and the land 20b in order to connect with a predetermined terminal of the module I / O terminal 5, and the predetermined module I / O It is electrically connected to the terminal 5.

Further, the memory 1 having the defective I / O pin 1b
In (1), a resistor is mounted between the land 20a connected to the land where the I / O pin 1b is located and the land 20b connected to the power supply voltage Vcc, and the I / O pin 1b is pulled up.

The I / O pin 1a which is not defective is I
Land 1 connected to the land where the / O pin 1a is located
A jumper wire is mounted between 9a and the land 19 and electrically connected to a predetermined module I / O terminal 5.

As a result, also in the third embodiment, the defect in the I / O pins 1a to 1d is pulled up through the resistor only by mounting the non-perfect non-defective memory 1 on the module substrate 12. The memory 1 can be stably operated without being affected by.

In addition to the module substrate 15, FIG.
As shown in FIG. 0, a module substrate (module wiring) having lands 19 to 19b and 20 to 20b formed on both sides for switching the connection destination of the memory 1 in which one of the I / O pins 1c and 1d is defective by a resistor or a jumper (module wiring) By using the board 21, both the memory 1 having defective I / O pins 1a and 1b or the memory 1 having defective I / O pins 1c and 1d can be used.

Further, as shown in FIG. 21, the memory 1 or I / O in which one of the I / O pins 1a and 1b is defective.
A land 19 for switching the connection destination of the memory 1 in which one of the O pins 1c and 1d is defective by a resistor or a jumper.
.About.19b and 20 to 20b are alternately provided, the module board (module wiring board) 22 is used.
Memory 1 or I / O with defective O pins 1a and 1b
Both of the memories 1 having defective pins 1c and 1d can be used.

(Fourth Embodiment) FIG. 22 shows a fourth embodiment of the present invention.
In the memory mounted on the module board by
23 is a schematic wiring diagram of the module substrate according to the fourth embodiment of the present invention.

In the fourth embodiment, as shown in FIG. 22, a module substrate (not shown) for mounting the semiconductor device 1 provided with I / O pins (input / output terminals) 1a to 1d.
Have all wirings provided in advance by the wiring pattern.

For example, as shown in FIG. 23, the I / O pins 1c and 1d that have been grouped in advance have become defective D.
When the memory 1 which is a RAM semiconductor device is mounted, the module substrate (not shown) has a defective I / O pin 1c,
A wiring pattern is provided so as to pull up 1d.

In addition, other non-defective I / O pin 1
The terminals a and 1b are connected to predetermined terminals of a module I / O terminal (input / output section) not shown.

The module board has I / O pins 1a to 1d.
A plurality of types of module boards having different wirings are prepared depending on the defective position.

As a result, according to the fourth embodiment, the defective I / O pins 1c and 1d are pulled up only by mounting the non-perfect good memory 1 on the module substrate.
The memory 1 can be operated without being affected by the defective I / O pins 1c and 1d.

Further, since the address control is not necessary, it is possible to have the same function and performance as a memory module using a perfectly good memory.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the first to fourth embodiments, the defective I / O pin is electrically fixed by pull-up, but the defective I / O pin may be other than the pull-up. The pull-up, pull-down, and Even if the non-connect is selected and electrically fixed, the memory can be operated well.

In the first to fourth embodiments, six memories are mounted vertically in the longitudinal direction of the module board, but there is no limitation on the direction of the memory mounted in the memory module. Instead, for example, the memory may be mounted laterally in the longitudinal direction of the module substrate.

[0128]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the present invention, a defective input / output terminal in a semiconductor device is electrically fixed, and only non-defective input / output terminals are used. Therefore, a semiconductor having the same performance as a non-defective module can be obtained. The device module can be constructed with stable operation.

(2) Further, according to the present invention, by selectively switching the input / output terminals of the semiconductor device, the flexibility of defective input / output terminals is improved and the specifications of the module substrate can be unified.

(3) Further, in the present invention, the defective semiconductor device can be efficiently utilized and the cost can be reduced by the above (1) and (2).

[Brief description of drawings]

FIG. 1 is a plan view of a module board according to a first embodiment of the present invention.

FIG. 2 is a block diagram diagram comparing module configurations according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a module configuration according to the first embodiment of the present invention.

FIG. 4 is a mounting diagram of a module substrate according to the first embodiment of the present invention.

FIG. 5 is a conceptual diagram of connection of the module substrate according to the first embodiment of the present invention.

FIG. 6 is a mounting diagram of a module substrate according to the first embodiment of the present invention.

FIG. 7 is a block diagram comparing module configurations according to the first embodiment of the present invention.

FIG. 8 is a block diagram of a module configuration according to the first embodiment of the present invention.

FIG. 9 is a mounting diagram of the module substrate according to the first embodiment of the present invention.

FIG. 10 is a mounting diagram of a module substrate according to the first embodiment of the present invention.

FIG. 11 is a wiring connection conceptual diagram of the module substrate according to the first embodiment of the present invention.

FIG. 12 is a mounting state diagram of the module substrate according to the first embodiment of the present invention.

FIG. 13 is a pin arrangement diagram of a memory mounted on the module substrate according to the first embodiment of the present invention.

FIG. 14 is a plan view of a module board according to a second embodiment of the present invention.

FIG. 15 is a schematic wiring diagram of a module substrate according to a second embodiment of the present invention.

FIG. 16 is a plan view of a module board according to a second embodiment of the present invention.

FIG. 17 is a plan view of a module board according to a second embodiment of the present invention.

FIG. 18 is a mounting diagram of a module substrate according to a third embodiment of the present invention.

19 (a) and 19 (b) are schematic wiring diagrams of a module substrate according to a third embodiment of the present invention.

FIG. 20 is a mounting view of a module substrate according to a third embodiment of the present invention.

FIG. 21 is a mounting view of a module board according to a third embodiment of the present invention.

FIG. 22 is a configuration diagram of I / O pins in the memory mounted on the module substrate according to the fourth embodiment of the present invention.

FIG. 23 is a schematic wiring diagram of a module substrate according to a fourth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 memory 1a-1d I / O pin (input / output terminal) 2 module board (module wiring board) 2a front surface 2b back surface 3 land (connection part) 3a land (seventh connection part) 3b land (seventh connection part) 3c land (sixth connection part) 3d land (seventh connection part) 4 land (connection part) 4a to 4c land (seventh connection part) 4d land (sixth connection part) 5 module I / O terminal (Input / output part) 6 Wiring pattern 7 Land (8th connection part) 7a Land (9th connection part) 8 Land (10th connection part) 8a Land (8th connection part) 8b Land (9th connection part) Connection part 9 Module board (module wiring board) 9a Surface 10 Land (connection part) 10a-10c Land (second connection part) 10d Land (first connection part) 11 Land (connection part) 11a Run (Second connection part) 11b Land (second connection part) 11c Land (first connection part) 11d Land (second connection part) 12 Module board (module wiring board) 13 Land (connection part) 13a land (Second connection part) 13b Land (first connection part) 13c Land (second connection part) 13d Land (second connection part) 14 Land (connection part) 14a Land (first connection part) 14b Land (second connecting portion) 14c Land (second connecting portion) 14d Land (second connecting portion) 15 Module board (module wiring board) 16 Land (connecting portion) 16a Land 16b Land (first connecting portion) ) 16c land 16d lands (first connecting portion) 16a ₁ lands 16b ₁ lands (first connecting portion) 16c ₁ lands 16d ₁ land 17 land (connecting portion) 7a lands (second connecting portion) 17b lands 17c lands 17d lands 17a ₁ lands (first connecting portion) 17b ₁ lands 17c ₁ lands 17d ₁ lands 18 module substrate (module wiring substrate) 19 lands (fourth connecting portions ) 19a land (third connection part) 19b land (fifth connection part) 20 land (fourth connection part) 20a land (third connection part) 20b land (fifth connection part) 21 module substrate ( Module wiring board) 22 Module board (module wiring board) R Resistance (second conduction means) J Jumper (second conduction means) Vcc Power supply voltage DM memory DM1 memory

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoshi Chikada, Asahidai, Moroyama-cho, Iruma-gun, Saitama 15 In Asahidai, Hitachi, Ltd. (72) Inventor Shigeru Honjo 5-20, Kamimizumoto-cho, Kodaira-shi, Tokyo No. 1 Incorporated company Hitachi Ltd. Semiconductor Division (72) Inventor Toshio Sasaki 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated Hitachi Ltd Semiconductor Division

Claims (9)

[Claims] 1. A module wiring board on which at least two or more semiconductor devices are mounted, and a connection part on which the semiconductor devices are mounted has a predetermined defective input / output terminal provided in the semiconductor device. The first connection part to which the input / output terminal is connected and is in an electrically fixed state is connected to the non-defective input / output terminal and is connected to a predetermined input / output part on the module wiring board. Second
The module wiring board is characterized in that a module equivalent to the module composed of a completely good semiconductor device is provided. 2. The module wiring board according to claim 1, wherein two or more connection portions on which one semiconductor device is mounted are provided, and the first connection portion in an electrically fixed state is provided with the connection portion. A module wiring board provided differently depending on a position of a semiconductor device mounted on a connection portion. 3. The module wiring board according to claim 1, wherein the electrically fixed state of the first connecting portion is pull-up, pull-down or non-connect. . 4. The module wiring board according to claim 1, wherein a third connection portion electrically connected to the first connection portion or the second connection portion, and a power supply voltage or a ground potential are electrically connected. And a fifth connection portion electrically connected to a predetermined input / output portion provided on the module wiring board, and the third connection portion and the fourth connection portion are provided. Between the connecting portions or between the third connecting portion and the fifth
2. A module wiring board, wherein wiring paths are switched by selectively attaching and detaching the first conducting means between the connecting portions. 5. The module wiring board according to claim 4, wherein the first conducting means is a jumper or a resistor. 6. A memory module comprising the module wiring board according to claim 1. Description: 7. A module wiring board on which at least two or more semiconductor devices are mounted, and two or more connection parts on which one semiconductor device is mounted, and the connection parts provided on the semiconductor device. In the input / output terminal, a sixth connection portion to which the defective predetermined input / output terminal is connected or an eighth connection portion that is electrically connected to a seventh connection portion to which the non-defective input / output terminal is connected A connection part, a ninth connection part electrically connected to a power supply voltage or a ground potential, and a tenth connection part electrically connected to a predetermined input / output part provided on the module wiring board. Wiring provided by selectively attaching and detaching the second conducting means between the eighth connecting portion and the ninth connecting portion or between the eighth connecting portion and the tenth connecting portion. Switching the path or mounting on the connection part A module wiring board, wherein a module equivalent to a module composed of a perfectly good semiconductor device is configured by electrically changing the position of the semiconductor device to electrically fix the sixth connecting portion. 8. The module wiring board according to claim 7, wherein the second conductive means is a jumper or a resistor, and a state in which the sixth connection portion is electrically fixed is pulled up, pulled down or A module wiring board characterized by being non-connected. 9. A memory module comprising the module wiring board according to claim 7 or 8.