JPH08272963A - Method and device for filtering processing of image - Google Patents

Abstract

PURPOSE: To extract a maximum or minimum value from plural image data without sorting them. CONSTITUTION: This device is provided with N stages of examining circuits 100-400 corresponding to the respective bits of N-bit image data. The examining circuit of an (i)th stage (i is 1 to N) finds new examination signals XP2-XT2 showing which of M (5) image data is candidate data on the basis of the value of the (i)th bit of each image data from the most significant digit bit as to image data specified as candidate data with examination signals XP3-XT3 supplied from the precedent stage. Thus, examination signals are found in order for every stage and the maximum value or minimum value is specified with the examination signals XP-XT obtained by the examining circuit 400 of the lowermost stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image filtering method and apparatus for obtaining a maximum value or a minimum value from a predetermined number of image data.

[0002]

2. Description of the Related Art As one type of image filter, a filter for extracting the maximum value or the minimum value from a plurality of image data in a filter area may be used. In the conventional filtering process, a method is generally used in which a plurality of image data are sorted and arranged in order of size to extract the maximum value or the minimum value.

[0003]

However, with the recent demand for higher processing speed of image processing apparatuses, there has been a demand for reducing the time spent for sorting image data as much as possible.

The present invention has been made to solve the above-mentioned problems in the prior art, and an object thereof is to extract the maximum value or the minimum value from a plurality of image data without performing sorting. .

[0005]

In order to solve the above-mentioned problems, the method according to claim 1 of the present invention is a method in which the maximum value is selected from M image data represented by N bits. A method of filtering an image for extracting an extreme value that is one of
For each of the M pieces of image data, a step of selecting the most significant bit as a processing target bit, and (b) performing a logical operation between the processing target bits, whereby the value of the processing target bit is the first A candidate signal indicating that one of the first type image data that is a level and the second type image data that the value of the processing target bit is the second level is the candidate data that can be the extreme value. And (c) performing a logical operation on each of the processing target bits of the M pieces of image data and the candidate signal to obtain, for each of the M pieces of image data,
Generating a test signal indicating whether or not the candidate data, (d) among the M image data, the image data designated as the candidate data by the test signal is The steps (b) to (c) are performed while sequentially selecting the lower bits as the bits to be processed.
Is sequentially performed to generate a test signal that specifies the image data that becomes the extreme value.

In order from the most significant bit, it is checked which of the M image data is the candidate data, and a test signal indicating which of the M image data is the candidate data is provided for each bit. I will seek them one by one. Therefore, the maximum or minimum value can be specified by the test signal obtained for the least significant bit.

In the image filtering method according to the second aspect, the first level is one level,
The second level is 0 level, and the step (d)
Includes the step of generating a test signal that specifies the maximum value among the M image data.

In the image filtering method according to the third aspect, the first level is 0 level,
The second level is one level, and the step (d)
Includes the step of generating a test signal that specifies the minimum value of the M image data.

The device according to claim 4 is N
An image filtering processing device for extracting an extreme value, which is one of a maximum value and a minimum value, from M pieces of image data represented by bits, and a serial processing corresponding to each bit of the N bits. Equipped with N-stage test means connected to
The i-th stage verification means corresponding to the i-th (i is an integer of 1 to N) bit from the higher order among the N bits is the image data designated as valid by the test signal given from the previous stage. , Either the first type image data in which the value of the i-th bit is the first level or the second type image data in which the value of the i-th bit is the second level is the pole. For each of the candidate signal generating means for generating a candidate signal indicating whether it can be value candidate data, and the image data designated as valid by the verification signal given from the preceding stage, the i-th bit and the candidate signal A new test signal indicating whether or not it is the candidate data is generated for each of the M image data, and the new test signal is supplied to the test means in the next stage. Discrimination Comprising a stage, a test unit of the N-th stage corresponding to the least significant bit, characterized in that it has a means for outputting a test signal for identifying the extreme values in the M image data.

The i-th stage verification means examines which of the M pieces of image data is the candidate data for the i-th bit, and determines which of the M pieces of image data is the candidate data. Obtain the test signal shown. Further, the next-stage verification means obtains the verification signal for the (i + 1) th bit based on the previous-stage verification signal. Therefore, the N-th stage verification means for the least significant bit can obtain a verification signal that specifies the maximum value or the minimum value.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an image filtering processing apparatus for applying an embodiment of the present invention to filter image data. The apparatus shown in FIG. 1 is an apparatus for generating test signals XP to XT that specify the maximum value from five image data P to T. The five pieces of input image data P to T are 4-bit data. Each bit of the first image data P is described as P3, P2, P1, P0 in order from the most significant bit. The same applies to other image data. This apparatus includes a four-stage verification circuit 100 corresponding to each of the four bits of image data.
400 are arranged in series. The uppermost test circuit 100 corresponding to the most significant bit has five AND circuits 11
1-115, five determination circuits 121-125, and NO
R circuit 130. Other test circuits 200-4
00 has the same configuration. The most significant bits P3 to T3 of each image data are respectively input to one terminals of the five AND circuits 111 to 115 of the uppermost test circuit 100,
The verification signals XP3 to XT3 are input to the other terminals, respectively.

FIG. 2 is a block diagram showing configurations of AND circuit 115, discrimination circuit 125 and NOR circuit 130 shown in FIG. The discrimination circuit 125 includes an EXOR circuit 126,
AND circuit 127.

The AND circuit 115 receives the most significant bit T3 of the fifth image data T and the test signal XT3 for the most significant bit T3 of the fifth image data T.
The verification signal XT3 is a signal indicating whether or not the image data T becomes a candidate for the maximum value. However, the verification signals XP3 to XT3 for the most significant bit of each image data are used to indicate whether or not each image data is to be processed. That is, among the five image data P to T, the image data to be filtered is the image data to be excluded from being processed by setting the test signals XP3 to XT3 for the most significant bit to 1 level. , The test signals XP3 to XT3 for the most significant bit are set to 0 level. In the example of FIG. 1, since all the test signals for the most significant bit are set to 1 level, all five image data are to be processed.

The output of the AND circuit 115 is 5-input NO together with the outputs of the other AND circuits 111 to 114 (FIG. 1).
It is input to the R circuit 130. In the examples of FIGS. 1 and 2, since the test signals XP3 to XT3 for the most significant bit are all set to 1 level, the most significant bit P3 of each image data is set.
.About.T3 is directly input to the NOR circuit 130. NO
The R circuit 130 outputs a candidate signal Y3 having the following level according to the levels of the five bits P3 to T3 inputted.

If at least one is one level: Y3
= “0” (indicates that image data whose processing target bit is 1 level is candidate data)

When all are at 0 level: Y3 = "1"
(Indicates that the image data whose processing target bit is 0 level is the candidate data)

When there is at least one 1-level bit, the image data having 1-level bit is a candidate for the maximum value. On the other hand, when there are no 1-level bits, the image data having 0-level bits is a candidate for the maximum value. For the candidate signal Y3, either of the first type image data in which the bit to be processed is 1 level (first level) or the second type image data in which the bit to be processed is 0 level (second level) is selected. It is a signal indicating whether or not it becomes candidate data.

As described above, the NOR circuit 130 performs a logical operation on the processing target bits to determine whether the first-type image data in which the processing target bits have one level (first level) is the candidate data. , And has a function as a candidate signal generation unit that generates a candidate signal indicating whether the second-type image data whose processing target bit is 0 level (second level) is the candidate data.

The discrimination circuit 125 has three input signals IN.
a, INb, and INc are input. The first input signal INa is the test signal XT3, and the second input signal INb is the output of the AND circuit 115 (that is, the processing target bit T3.
), The third input signal INc is the candidate signal Y3. The EXOR circuit 12 receives the second and third input signals INb and INc.
It has been entered in 6. In addition, the first input signals INa and E
The output of the XOR circuit 126 is input to the AND circuit 127. The output of the discrimination circuit 125 is input to the next-stage test circuit 200 as the test signal XT2 of the next lower bit T2.

FIG. 3 is a truth table of the discrimination circuit 125. When the test signal XT3 given from the previous stage is at 0 level, the test signal XT2 of the next stage output from the discrimination circuit 125.
Also becomes 0 level. In other words, when the test signal XT3 given from the previous stage indicates that it is not the candidate data, it also indicates that the test signal XT2 in the next stage is also not the candidate data.

When the test signal XT3 given from the previous stage is at the 1 level, the second input signal INb and the third input signal Ib are input.
The level of the test signal XT2 at the next stage is determined according to the level of Nc. That is, when the third input signal INc (candidate signal Y3) is at 0 level, the second input signal INb
The level of (processing target bit T3) becomes the level of the next-stage verification signal XT2 as it is. As described above, the candidate signal Y
When 3 is 0 level, the image data whose processing target bit is 1 level becomes the candidate data, and therefore the processing target bit (second input signal INb) is output as it is as the level of the test signal XT2 of the next stage. It is. On the other hand, when the third input signal INc (candidate signal Y3) is at 1 level, the signal of the level obtained by inverting the second input signal INb (processing target bit T3) becomes the test signal XT2 of the next stage. When the candidate signal XT3 is at the 1 level, the image data whose processing target bit is at the 0 level becomes the candidate data, so the processing target bit (second input signal INb) is inverted and the verification signal XT2 of the next stage is inverted. Is output as the level of.

As described above, the discrimination circuit 125 performs a logical operation of the processing target bit T3 and the candidate signal Y3 for the image data indicated by the test signal XT3 given from the preceding stage as the candidate data, New verification signal X indicating whether or not this image data is candidate data
It has the function of generating T2.

Discrimination circuits 121 to 125 in the first-stage inspection circuit 100 shown in FIG. 1 generate new inspection signals XP2 to XT2 indicating whether or not each image data is candidate data.
The verification circuit 200 in the next stage receives these signals XP2 to XT2,
In accordance with the upper second bits P2 to T2 of each image data, further verification signals XP1 to XT1 of the next stage are generated. Thus
The i-th test circuit corresponding to the i-th bit from the higher order generates a new test signal based on the test signal given from the previous stage and the i-th bit of the M pieces of image data to generate the new test signal. Supply to the test circuit of. Then, the test signal XP ~ output from the test circuit 400 corresponding to the least significant bit
The maximum value is specified by XT. That is, the image data in which the level of the test signals XP0 to XT0 is 1 is the maximum value. A selector is provided downstream of the verification circuit 400 at the bottom,
The maximum value can be extracted by selecting one of the five image data P to T according to the test signals XP to XT.

FIG. 4 shows an example in which actual values are input to the image data P to T. The value of each image data shown in FIG. 4 is expressed in decimal notation P = 2, Q = 5, R = 1, S =
8, T = 12, and in binary notation, P = 0010, Q =
0101, R = 0001, S = 1000, and T = 1100. Further, the final stage verification signal XT for the image data T (= 12) having the maximum value becomes 1 level, and the final stage verification signal for other image data becomes 0 level.

When there are a plurality of maximum values among the five image data P to T, the final stage verification signals for the plurality of image data are all one level. The image data in which the final-stage verification signal is one level all have the same value, so the same is true regardless of which is extracted.

In the above-described embodiment, the i-th
The maximum value can be extracted only by inputting the th bit to the i-th test circuit. Therefore, there is an advantage that the maximum value can be extracted at high speed by the hardware circuit without performing the sorting process of the image data. Further, only the image data in which one level is input to the uppermost verification signals XP3 to XT3 can be selectively processed. Therefore, by preparing a circuit in which the number M of image data that can be input is sufficiently large and adjusting the level of the test signal in the uppermost stage in accordance with the number of image data to be processed, filters of various sizes can be obtained. The filtering process can be performed in the same circuit. For example, when the number M of image data that can be input is 100, it is possible to execute the filtering process on the filter having a size up to 10 × 10 pixels.

In the above embodiment, the maximum value of M image data was extracted, but the minimum value can be extracted by a similar circuit. FIG. 5 is a block diagram showing a circuit configuration capable of selectively extracting one of the maximum value and the minimum value of M pieces of image data.

The circuit shown in FIG. 5 is obtained by adding an EXOR circuit 116 to the input side of the AND circuit 115 of the circuit shown in FIG. To the EXOR circuit 116, the processing target bit T3 of the image data and the inverted signal INV are input. The EXOR circuit 116 functions as an inverter that allows the processing target bit T3 to pass as it is when the inversion signal INV is at 0 level, and inverts the level of the processing target bit T3 when the inversion signal INV is at 1 level. One such EXOR circuit 116 is provided on the input side of each AND circuit shown in FIG. The inverted signal INV input to the EXOR circuit 116 is a signal common to all bits of all image data. When the inversion signal INV is 0 level,
Since the operation of the circuit of FIG. 5 is the same as that of the circuit of FIG. 2, this device functions as a circuit for extracting the maximum value. On the other hand, when the inversion signal INV is 1 level,
The circuit of 1 functions as a circuit for extracting the maximum value in the data obtained by inverting the image data P to T. The maximum value of the inverted image data is the minimum value of the original image data. Therefore, the circuit of FIG. 5 functions as a circuit for extracting the minimum of the image data P to T when the inversion signal INV is 1 level.

As described above, by providing the EXOR circuit on the input side of each AND circuit of the apparatus of FIG. 1, the apparatus for extracting the maximum value or the minimum value of M pieces of image data can be configured. If an inverter is provided instead of the EXOR circuit, a device for extracting the minimum value can be obtained.

FIG. 6 is a block diagram showing another circuit configuration for extracting the minimum value. This circuit corresponds to the AN in FIG.
The D circuits 111 to 115 are replaced with OR circuits 141 to 145, the NOR circuit 130 is replaced with an AND circuit 160, and the determination circuits 121 to 125 are replaced with other determination circuits 1.
It has the structure replaced by 51-155. FIG.
The OR circuit 145, the determination circuit 155, and the NOR circuit in FIG.
FIG. 3 is a block diagram showing a configuration of a circuit 160 and is a diagram corresponding to FIG. 2 described above. The determination circuit 155 replaces the AND circuit 127 in the determination circuit 125 shown in FIG. 2 with the OR circuit 157.
It has a configuration replaced with.

As shown in the upper part of FIG. 6, the verification signals XP3 to XT3 input to the first-stage verification circuit 102 are at 0 level. That is, in the apparatus shown in FIGS. 6 and 7, the image data whose verification signal is 0 level is the candidate data. Therefore, the image data in which the verification signals XP to XT output from the final verification circuit 402 are at the 0 level is extracted as the minimum value.

As described above, various logically equivalent configurations can be adopted as the circuit configuration of the image filtering apparatus in this embodiment.

In the above embodiment, the maximum value or the minimum value is obtained by using the hardware circuit, but the configuration of the present invention can be realized by the CPU executing the software program.

FIG. 8 is a flowchart showing the procedure for extracting the maximum value from the M pieces of image data. In step 11, it is judged whether or not there is data of one level in the most significant bit. If there is data in which the most significant bit is 1 level, in step 12, the image data in which the most significant bit is 0 level is excluded from the candidate data. The process of determining whether or not the data is candidate data will be referred to as “verification” below. If all the most significant bits are 0 level, the process proceeds to step 13 and the image data whose most significant bit is 1 level is excluded from the candidate data. The processing of steps 11 to 13 is the same as the content of the processing executed by the NOR circuit 130 shown in FIG.

If the test for the least significant bit has not been completed, the process proceeds from step 14 to step 15. In step S15, it is determined whether or not there is one-level data in the next bit, and one of steps 12 and 13 is executed according to this result. Also, step 1
5 is also executed again. Thus, steps 12 to 15 are repeated until the least significant bit is reached. When the test for the least significant bit is completed, in step 16, data that is not excluded from the candidate data is extracted from the result of the test for the least significant bit.

FIG. 7 is a flowchart showing the procedure for extracting the minimum value from the M pieces of image data. Steps 21 to 26 in FIG. 7 are the ones in which the “0” level and the “1” level in steps 11 to 16 in FIG. 6 are exchanged.
Since this is the same as inverting the level of the input image data, in the circuit shown in FIG.
The operation when V is set to 1 level has the same processing content.
Therefore, according to the procedure of FIG. 7, the minimum value can be extracted.

By the way, the filter for extracting the maximum value or the minimum value from the M pieces of image data can be used for various image processes. For example, it can be used as a filter for determining whether the image is a continuous tone image such as a photograph or a binary image such as a character based on the maximum value and the minimum value in the filter area. it can. It can also be used as an edge detection filter that determines whether or not an edge (contour) of an image exists in the filter area based on the difference between the maximum value and the minimum value in the filter area.

The present invention is not limited to the above-described embodiments, but can be implemented in various modes without departing from the scope of the invention.

[0039]

As described above, according to the present invention, the maximum value or the minimum value can be extracted from a plurality of image data without performing sorting.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an image filtering processing apparatus that performs an image data filtering process by applying an embodiment of the present invention.

FIG. 2 is a block diagram showing the configurations of an AND circuit 115, a discrimination circuit 125, and a NOR circuit 130.

FIG. 3 is an explanatory diagram showing a truth table of a discrimination circuit 125.

FIG. 4 is an explanatory diagram showing a result of inputting actual values to image data P to T.

FIG. 5 is a block diagram showing a circuit configuration for extracting a maximum value or a minimum value of M pieces of image data.

FIG. 6 is a block diagram showing another circuit configuration for extracting the minimum value.

FIG. 7 is a block diagram showing the configurations of an OR circuit 145, a determination circuit 155, and an AND circuit 160.

FIG. 8 is a flowchart showing a procedure for extracting a maximum value from M pieces of image data.

FIG. 9 is a flowchart showing a procedure for extracting a minimum value from M pieces of image data.

[Explanation of symbols]

 100-400 ... Test circuit 111-115 ... AND circuit 116 ... EXOR circuit 121-125 ... Discrimination circuit 126 ... EXOR circuit 127 ... AND circuit 130 ... NOR circuit

Claims (4)

[Claims] 1. A method of filtering an image for extracting an extreme value, which is one of a maximum value and a minimum value, from M pieces of image data represented by N bits respectively. For each of the M image data,
Selecting the most significant bit as the bit to be processed,
(B) By performing a logical operation between the processing target bits, the first type image data in which the value of the processing target bit is the first level and the value of the processing target bit are in the second level. A step of generating a candidate signal indicating that one of the certain second type image data is the candidate data which can be the extreme value, and (c) a processing target bit of each of the M image data, Generating a test signal indicating whether or not the candidate data is the candidate data for each of the M image data by performing a logical operation with the candidate signal; and (d) the M image data. Among the image data designated as the candidate data by the verification signal, the steps (b) to (c) are sequentially performed while sequentially selecting the next lower bit as a processing target bit. By row, and generating a test signal for specifying the image data to be the extreme,
An image filtering method, comprising: 2. The image filtering method according to claim 1, wherein the first level is 1 level, the second level is 0 level, and the step (d) is An image filtering method, comprising the step of generating a test signal that specifies the maximum value of M image data. 3. The image filtering method according to claim 1, wherein the first level is 0 level, the second level is 1 level, and the step (d) is A method of filtering an image, comprising the step of generating a test signal that specifies the image data having the minimum value among M image data. 4. An image filtering processing apparatus for extracting an extreme value, which is one of a maximum value and a minimum value, from M pieces of image data represented by N bits, respectively. N connected in series corresponding to each bit
The verification means of the stage is provided, and the verification means of the i-th stage corresponding to the i-th bit (i is an integer of 1 to N) from the higher order among the N bits is designated as valid by the verification signal given from the previous stage. The value of the i-th bit is the first
A candidate signal indicating which of the first-type image data at the level of ## EQU1 ## and the second-type image data at which the value of the i-th bit is at the second level can be the extreme-value candidate data. With respect to each of the candidate signal generating means for generating and the image data designated as valid by the verification signal given from the preceding stage, a logical operation is performed on the i-th bit and the candidate signal to obtain the M number of signals. For each of the image data, a determination means for generating a new test signal indicating whether or not the candidate data, and supplying the new test signal to the test means of the next stage,
An image filtering processing apparatus, characterized in that the N-th stage inspection means corresponding to the least significant bit has a means for outputting an inspection signal for specifying an extreme value in the M pieces of image data.