JPH08272671A - Memory control method for dram - Google Patents

Abstract

PURPOSE: To provide a memory control method which performs data read and write operations in a short time in the case of the use of a DRAM. CONSTITUTION: This memory control method is provided for a memory consisting of m memory areas ((m) is a natural number equal to or larger than 2) and is provided with a memory 1 where data is stored, a memory control part 2 which designates an address at the time of data write to or read from the memory 1, and a memory control part 2 which designates the address of the j-th memory area ((j) is a natural number equal to or smaller than (m)) of the memory 1 to read out the data and writes data in the k-th memory area ((k) is a natural number equal to or smaller than (m)) in the period of addressing of the j-th memory area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control method in a dynamic random access memory (hereinafter referred to as DRAM) used in an information processing device such as a personal computer, a workstation and a word processor.

[0002]

2. Description of the Related Art A large number of DRAMs are used in information processing apparatuses currently in use, and it is frequently performed to transfer data from a certain memory area in a DRAM on the same bus to another memory area. It is being appreciated.

In such a case, data is read from a certain memory area of the DRAM in a certain cycle, and the read data is written to another memory area in the DRAM on the same bus in the next cycle. Data is transferred, and at the time of transferring such data, at least two bus cycles are required for data read operation and data write operation.

1 and 4 show the operation when the data is read from a certain memory area of the above-mentioned DRAM and then the data is transferred to another memory area of the DRAM on the same bus.
Will be explained.

FIG. 1 shows a memory control unit and a DRA.
It is a schematic block diagram of the periphery of M.

Reference numeral 1 denotes D for storing image data, voice data, or character data (hereinafter simply referred to as data).
This is a RAM, and the DRAM 1 of this embodiment is composed of a first memory area 1a and a second memory area 1b. Two
Reads data from DRAM1 or DR
When writing data to AM1, such D
A memory control unit that controls commands such as an address designation signal and a write signal of the RAM 1, and this memory control unit 2 is an MA (memory address) for the DRAM 1.
A signal, a RAS (row address selection) signal, a CAS (column address selection) signal, and a WE (write) signal can be applied.

Here, when the MA signal is active,
Data is read from the addressed DRAM 1 by applying the RAS signal and the CAS signal to the DRAM 1.

On the other hand, when the MA signal and the WE signal are active, the RAS signal and the CAS signal are the DRAM 1
DRAM addressed by being applied to
The data is written in 1.

Reference numeral 3 is a CPU for controlling the DRAM 1 and the memory control unit 2, and 4 is a data bus for data transfer between the first memory area 1a and the second memory area 1b of the DRAM 1.

By the way, FIG. 4 shows a timing chart when data is transferred from the first memory area 1a to the second memory area 1b in the conventional DRAM 1.

Address, Read, Wr in FIG.
ite and Ready are the memory control unit 2 and C
It shows signals to and from PU3, and also MA signal, RA
S signal, CAS0 signal, CAS1 signal, and WE1 indicate signals sent from the memory control unit 2 to the DRAM 1.

The operation of transferring data from the first memory area 1a to the second memory area 1b of the DRAM 1 using the above-mentioned structure will be described with reference to FIGS. 1 and 4.

First, the operation of reading data from the first memory area 1a will be described.

The CPU 3 activates the Address signal applied to the memory controller 2 and
Activate the Read signal. As a result, the memory control unit 2 activates the MA signal, specifies the address of the first memory area 1a by the RAS signal and the CAS0 signal, and reads the data in the first memory area 1a.

Next, the operation of writing the data read from the first memory area 1a into the second memory area 1b will be described.

The CPU 3 activates the Address signal applied to the memory controller 2 and
Activates the Write signal. As a result, the memory control unit 2 activates the MA signal, designates the address of the second memory area 1b by the RAS signal and the CAS1 signal, and activates the WE1 signal so that the second memory area 1b is activated. Data can be written.

As a result, the data read from the first memory area 1a is transferred by being written in the second memory area 1b through the data bus.

[0018]

However, one cycle is required for each of the data read operation from the first memory area 1a and the data write operation to the second memory area 1b, and high-speed processing is required. Processors must use faster DRAMs, which are expensive.

Therefore, the present invention has been made in view of the above problems, and it is possible to perform a data read operation and a data write operation in a short time even when a conventional DRAM is used. It is an object to provide a memory control method.

[0020]

The present invention is based on m (where m
Is a memory control method of a memory composed of two or more memory areas, and a memory for storing data and a memory for designating an address when writing or reading data to or from the memory. The control unit and the j-th (j is a natural number of m or less) memory area related to the memory are addressed to read data, and the k-th memory area is read within the addressing period of the j-th memory area.
(K is a natural number of m or less), and a memory control unit for writing data in the memory area.

[0021]

According to the present invention, by including the above-mentioned means, when the data read from the j-th memory area is written in the k-th memory area, the k-th memory area is read within the addressed period. By designating an address for writing to the memory area, it becomes possible to write data to the kth memory area within a read addressing period in the jth memory area, which shortens the data read operation and the write operation. Can be done in time.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory control method for a DRAM of the present invention will be described with reference to FIGS.

The memory control unit 2 in the present invention,
Since the configuration around the DRAM 1 and the DRAM 1 is the same as the conventional one, the same numbers are given to the configuration, and a detailed description will be omitted.

A major difference of the memory control method of the present invention from that of the conventional method is that data can be read and written into the DRAM 1 in a short time, that is, transferred.
More specifically, RA in the first memory area 1a
By switching the CAS1 signal and WE1 to active during the period in which the RAS signal is active within the period of addressing by the S signal and the CAS0 signal, the data read from the first memory area 1a can be written in a short time. This is the point stored in the second memory area 1b.

FIG. 2 is a concrete configuration diagram of the memory control unit 2 of the present invention.

Reference numeral 21 is addre sent from the CPU 3.
a mode set port set to a first mode (a mode that operates according to the algorithm shown in FIG. 4) or a second mode (a mode that operates according to the algorithm shown in FIG. 3 described later) according to the ss signal and the Write signal;
Reference numeral 22 is an address decoding unit for decoding an address according to the address signal sent from the CPU 3, 23
Is an MA (memory address) control unit that multiplexes a memory address signal when addressing to the DRAM 1 in accordance with an address signal sent from the CPU 3, 24 is a Read signal sent from the CPU 3, Wr
an ITE signal, or a Ready control unit that returns a Ready signal to the CPU 3 in accordance with the address signal sent from the address decoding unit 22, 25 a mode signal sent from the mode set port 21, and a Read signal sent from the CPU 3, A RAS control unit for designating a row address in the DRAM 1 according to a Write signal or a select signal sent from the address decoding unit 22. The RAS control unit 25 is a first memory area 1a and a second memory area of the DRAM 1. 1b is connected to send a RAS signal.

Reference numeral 26 is a mode signal sent from the mode set port 21, and Read sent from the CPU 3.
A CAS control unit for designating a column address in the DRAM 1 in accordance with the signal and the Write signal, sending a CAS0 signal to the first memory area 1a of the DRAM 1, and a second
It is connected to send the CAS1 signal to the memory area 1b.

27 is a Write sent from the CPU 3.
The WE control unit 27 sends out a WE0 signal or a WE1 signal for making data writable to the DRAM 1 according to the signal and the mode signal sent from the mode set port 21.
Is connected to send the WE0 signal to the first memory area 1a and send the WE1 signal to the second memory area 1b.

By the way, FIG. 3 is a timing chart for transferring data from the first memory area 1a to the second memory area 1b in the present invention.
Also, the operation will be described with reference to FIG.

First, similarly to the conventional case, the CPU 3 activates the Address signal applied to the address decoding unit 22 and activates the Read signal. Accordingly, the MA control unit 23 activates the MA signal applied to the DRAM 1 and the RAS control unit 25 causes the RAS to operate.
The CAS control unit 26 designates the address of the first memory area 1a by activating the signal and the CAS0 signal, and reads the data of the first memory area 1a at the address.

On the other hand, while the RAS control unit 25 and the CAS control unit 26 are addressing by the RAS signal and the CAS0 signal, the WE control unit 27 sets the second address.
The WE1 signal applied to the memory area 1b is made writable.

At the same time, the CAS controller 26 activates the CAS1 signal while the WE1 signal is in the writable state. As a result, since the RAS signal is active, the second memory area 1b is addressed by the RAS signal and the CAS1 signal, and the data is written to the second memory area 1b within the addressing period. .

In the above embodiment, the DRAM 1 is described as being composed of two memory areas, but the present invention is not limited to this, and the present invention can be applied if the DRAM 1 is composed of a plurality of memory areas. Is.

[0034]

As is apparent from the above description, according to the present invention, the second memory area is addressed and the second memory area is addressed within the addressing period when data is read from the first memory area in the DRAM. By setting the area to the data writable state, it becomes possible to write the data to the second memory area, and the data transfer between the memories can be performed in a short time.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a periphery of a memory control unit 2 and a DRAM 1 according to the present invention.

FIG. 2 is a specific configuration diagram of a memory control unit 2 of the present invention.

FIG. 3 is a timing chart when transferring data from the first memory area 1a to the second memory area 1b in the present invention.

FIG. 4 is a diagram showing a first memory area 1 in a conventional DRAM 1.
It is a timing chart at the time of transferring data from a to the 2nd memory area 1b.

[Explanation of symbols]

 1 ... DRAM 1a ... First memory area 1b ... Second memory area 2 ... Memory control section 3 ... CPU 4 ... Data bus

Claims (2)

[Claims] 1. A memory control method of a memory configured by m (where m is a natural number of 2 or more) memory areas, the memory storing data and the writing of data to the memory, or A memory control unit for designating an address at the time of reading, wherein the memory control unit is the j-th (j
Is a natural number less than or equal to m) and the data is read out while writing data to the k-th (k is a natural number less than or equal to m) memory area within the addressing period of the j-th memory area. DR characterized by performing
Memory control method in AM. 2. The memory control unit, within a period in which the row addressing signal is active among a row addressing signal and a column addressing signal applied to the memory when reading data from the jth memory area. 2. The DR according to claim 1, wherein a write signal for writing data to the kth memory area and a column addressing signal are applied to the kth memory area.
Memory control method in AM.