JPH08272410A - Synchronous operation start/stop control system - Google Patents

Abstract

PURPOSE: To provide a synchronous operation start/stop control system capable of performing the synchronous/simultaneous operation of plural devices to be controlled. CONSTITUTION: Registers 21-2n and synchronous start/stop terminals D(1)-D(n) connected to each other are provided in each of the plural devices 2(1)-2(n) to be controlled connected to a controller 1 via a bus, and command data to regulate the operation of the devices 2(1)-2(n) to be controlled from the controller 1 and the command data out of synchronous start/stop are stored in the registers 21-2n transiently, and when at least one of the synchronous start/stop terminals D(1)-D(n) receives the synchronous start/stop, the whole operations of the plural devices 2(1)-2(n) to be controlled are started/stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous operation start / stop control system, and more particularly to a synchronous operation start / stop control system which enables high-speed synchronous simultaneous operation of a plurality of controlled devices.

[0002]

2. Description of the Related Art A synchronous operation start control system for synchronously and simultaneously operating a plurality of devices by a control signal from a control device side is widely adopted in various fields. For example, in an NC processing machine, in order to move a work or a cutting tool with respect to the X-axis, Y-axis, Z-axis, and θ-axis, a plurality of pulse generation functions for rotationally driving a stepping motor for driving each axis are provided. It is necessary to operate each IC simultaneously and individually.

In order to operate a plurality of ICs at the same time, conventionally, a start command composed of a predetermined specific pattern transmitted from a CPU via a data bus and an address designating an IC to be controlled is received. The received IC interprets the received start command, and starts its operation when the interpreted address matches the address of its own IC. 4 and 5, in the conventional synchronous operation start control system, n ICs 2 (1) to 2 (n) are CP
A system configuration diagram for operating U1 in a substantially simultaneous synchronization state and an operation timing chart thereof are shown.

4 and 5, a plurality of ICs 2
(1) to 2 (n) are connected to the CPU 1 via a data bus, and from the CPU 1, I including an address designating an IC to be operated and a start instruction specifying pattern.
Start command S1 for C2 (1) to 2 (n),
, Sn are sequentially transmitted in time series. The IC2 (1) that receives and interprets the start command S1 recognizes that it is a self-designated address and starts operating, and the IC2 (2) that receives the start command S2 is also a self-designated address. Is recognized, the operation is started, and thereafter, a similar operation is executed in each IC, and finally, I
The operation is started when C2 (n) receives the start command Sn. This also applies to the synchronous operation stop control in which the operation is stopped and controlled synchronously.

[0005]

As described above, in the conventional synchronous operation start / stop control system, the operation of each IC is started / stopped in synchronization with the start / stop command sent from the CPU 1 in time series. It

Therefore, there is a problem that a deviation occurs in the start of operation of each IC, and especially when the operation speed of the CPU is slow, the deviation becomes large and it becomes difficult to synchronize or simultaneously operate each IC.

Therefore, an object of the present invention is to start a synchronous operation for synchronizing and simultaneously operating a plurality of controlled devices.
It is to provide a stop control method.

[0008]

In order to solve the above-mentioned problems, in the synchronous operation start / stop control system according to the present invention, a plurality of controlled devices are connected to a control device via a bus, and the control device controls A synchronous operation start / stop control system for controlling the controlled device by a control command sent via a bus, wherein each of the plurality of controlled devices is provided with a register and a synchronous start / stop terminal. The synchronous start / stop terminals of the plurality of controlled devices are connected to each other, and command data and synchronous start / stop commands that define the operation of the controlled device are sent from the control device via the bus. The command data received in the register is temporarily stored and at least one of the synchronous start / stop terminals is stored. Synchronous start / stop terminal configured to start / stop all operations of the plurality of controlled devices become active by receiving the synchronization start / stop command.

Here, the controlled device individually starts / starts the operation of the controlled device sent from the control device.
Further comprising means for starting / stopping the operation in response to receiving a start / stop command for stopping,
Further, the control device may be a CPU, and the controlled device may be a pulse generation control circuit that controls a pulse generation mode.

[0010]

According to the present invention, each of a plurality of controlled devices connected to the control device via the bus is provided with a register and a synchronous start / stop terminal connected to each other, and the controlled device operates from the control device. Command data for defining the command and command data of synchronous start / stop are temporarily stored in a register, and when at least one of the synchronous start / stop terminals receives the synchronous start / stop, a plurality of controlled objects are controlled. All operations of the device are started / stopped.

[0011]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a system configuration diagram of a synchronous operation start control system showing an embodiment of a synchronous operation start / stop control system according to the present invention.

In this embodiment, a plurality of ICs 2 (1) -2
(N) is connected to the CPU via the data bus.
IC2 (1), 2 (2), ..., 2 (n) are commonly connected to synchronous start terminals D (1), D
(2), ..., D (n) are provided. IC2
Registers (1), 2 (2), ..., 2 (n) that are connected to the CPU 1 via a data bus and temporarily store command data that is sent from the CPU 1 and that specifies the operation corresponding to each IC 21, 22, ..., 2n are provided.

The operation of this embodiment will be described with reference to FIG. 2 showing the operation timing chart of the embodiment shown in FIG. 1. The CPU 1 causes the register to temporarily store the command data including the above command data. A hold command for sending is sent to each IC via the data bus.

First, the IC2 (1) which has received and interpreted the hold command H1 for the IC1 temporarily stores the received command data in the register 21. Then, the IC2 (2) temporarily stores the received command data in the register 22 in response to the hold command H2 transmitted from the CPU1, and thereafter, similarly, the received command data is temporarily stored in the register of the corresponding IC, and finally the IC2 The received command data corresponding to the register 2n of (n) is temporarily stored.

In this way, after all the command data are stored in the corresponding IC registers, the synchronous start command D sent from the CPU 1 is received by the IC 2 (1).

Upon receiving the synchronous start command for activating the synchronous start terminal, the IC2 (1) immediately starts the operation according to the command stored in the register 21. On the other hand, since the synchronous start terminals D (2), ..., D (n) of the other ICs 2 (2), ..., 2 (n) are commonly connected to D (1), IC2 (2) ,. 2 (n) also receive the synchronous start terminal active signal at the same time, and eventually, the operations of the ICs 2 (1) to 2 (n) are started simultaneously in a synchronized state.

FIG. 3 shows a configuration example of the operation control unit of the IC that can be used in the above-mentioned embodiment. This configuration is a circuit that enables not only synchronous and simultaneous operation of each IC but also individual independent operation of conventional ICs.

When the one-shot timer 22 is activated by the synchronous start command received via the data bus, a high level pulse is supplied to the base of the NPN transistor 23 as a switching circuit. NP
The emitter of the N-transistor 23 is grounded, and when a high-level pulse is supplied to the base from the one-shot timer 22, the NPN transistor 23 is turned on, the synchronous start terminal 2 (1) D becomes low-level, and is commonly connected. The low level data is also sent to the synchronous start terminals D (2), ..., D (n) of the other ICs 2 (2) ,.

This low level data is transferred to the inverter 24.
Is inverted and becomes high level data, and the OR gate 25
Is supplied to one input terminal. A normal start command similar to the conventional one is supplied to the other input terminal of the OR gate 25, and the output of the OR gate 25 starts the operation of the IC. Therefore, the operation of each IC is started in response to the reception of the normal start command or the synchronous start command, and the independent operation control of each IC and the synchronous and simultaneous operation control are possible.

In the above embodiments, the synchronous operation start control method is used, but it is clear that the present invention can be applied to the synchronous operation stop control method in exactly the same manner.

[0021]

As described above, according to the synchronous operation start / stop control system of the present invention, it is possible to synchronize and simultaneously operate a plurality of controlled devices.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of a synchronous operation start control system showing an embodiment of a synchronous operation start / stop control system according to the present invention.

FIG. 2 is an operation timing chart of the embodiment shown in FIG.

FIG. 3 is a circuit diagram of an operation control unit of an IC used in the embodiment shown in FIG.

FIG. 4 is a system configuration diagram in a conventional synchronous operation start control system.

FIG. 5 is an operation timing chart of a conventional synchronous operation start control method.

[Explanation of symbols]

1 CPU 2 (2), ..., 2 (n) ICs 21, 22, ..., 2 (n) Registers D (1), D (2), ..., D (n) Synchronous start terminal

Claims (3)

[Claims] 1. A synchronous operation start / stop control system in which a plurality of controlled devices are connected to a control device via a bus, and the controlled device is controlled by a control command sent from the control device via the bus. A register and a synchronous start / stop terminal are provided in each of the plurality of controlled devices, and the synchronous start / stop terminals of the plurality of controlled devices are connected to each other,
Command data defining the operation of the controlled device and a synchronous start / stop command are sent from the control device via the bus, and the command data received in the register is temporarily stored and the synchronous start / stop command is sent. Synchronous start / at least one of the stop terminals
A synchronous operation start / stop control method characterized in that a stop terminal becomes active when the synchronous start / stop command is received to start / stop all operations of the plurality of controlled devices. 2. The controlled device further comprises means for starting / stopping operation in response to reception of a start / stop command for individually starting / stopping the controlled device sent from the control device. Item 1
The synchronous operation start / stop control method described in. 3. The synchronous operation start / stop control system according to claim 1, wherein the control device is a CPU, and the controlled device is a pulse generation control circuit for controlling a pulse generation mode.