JPH08265163A - Signal processing unit - Google Patents

Abstract

PURPOSE: To miniaturize by directly filtering a 1-bit input signal so as to process an acoustic signal with a simple circuit configuration. CONSTITUTION: The processing unit is provided with a signal generating section 1 generating an acoustic signal, a signal processing section 2 processing the acoustic generating signal, and a speaker 4 sounding an output based on the acoustic generating signal. The signal processing section 2 being an A/D converter of oversampling system comprising a modulator 5 and a digital data generating section 7 has a filtering section 6 with 1-bit input and 1-bit output between the modulator 5 and the generating section 7. Thus, the signal expressed in 1-bit is obtained by th over-sampling system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device used for acoustic signal processing and the like.

[0002]

2. Description of the Related Art In recent years, attention has been paid to, for example, a signal processing device for acoustic signal processing. FIG. 10 is a diagram showing a configuration example of a conventional signal processing device of this type. Referring to FIG.
This signal processing device uses a signal generation unit 51 that generates a sound generation signal and a sound generation signal from the signal generation unit 51 as A
A / D conversion unit 52 that performs A / D conversion, digital filter unit 53 that changes the property of the sound generation signal that is converted into a digital signal by A / D conversion unit 52, and digital signal that has the property changed by digital filter unit 53 It has a D / A converter 54 for D / A converting and a speaker 55 for outputting sound based on the sound generation signal converted into an analog signal by the D / A converter 54.

In this type of signal processing device, for example, a virtual speaker 55 'exists at a position different from the actual speaker 55, and the sound output from the speaker H by the human H is generated by this virtual sound source (virtual speaker 55'). ), The characteristics of the signal can be changed in the digital filter unit 53 so that it can be heard as being output from the digital filter unit.

[0004]

By the way, in the above-described conventional signal processing apparatus, the A / D conversion section 52 has, for example, the configuration shown in FIG.
Conventional type as shown in 1 (successive comparison type in the example of FIG. 11)
Analog input (signal generation unit 51
The voltage of the sound generating signal) is converted into a 16-bit or 24-bit digital signal by the comparator 61, the D / A converter 62, and the successive approximation register 63. That is, in this successive approximation type A / D converter, the binary search method is used so that the output voltage of the reference D / A converter 62 is closest to the input signal (analog input).
You are getting a bit or 24-bit digital signal.

Further, in the above-mentioned conventional signal processing device,
A DSP (digital signal processor) is used for the digital filter unit 53, and the digital filter unit 53 uses A
The 16-bit or 24-bit digital signal from the / D converter 52 is subjected to filtering (sum of products operation) using a DSP.

However, in such a signal processing device, a 16-bit or 24-bit A / D converter and a DSP for multiply-accumulate operation have a relatively large circuit configuration, so that There was a problem that it was not possible to reduce the size and cost.

It is an object of the present invention to provide a signal processing device that can perform processing of an acoustic signal, for example, with a simple circuit configuration, and can realize downsizing and cost reduction.

[0008]

In order to achieve the above object, according to the invention of claim 1, there is provided a signal accumulating means for accumulating a 1-bit input signal represented by 1 bit,
Coefficient storage means for storing the filter coefficient represented by 1 bit, and filtering result output means for calculating a filtering result by the 1-bit input signal from the signal storage means and the 1-bit filter coefficient from the coefficient storage means are provided. The 1-bit input signal represented by 1 bit is directly filtered by the oversampling method to obtain a filtering result represented by 1 bit. As a result, the filtering process for the signal represented by 1 bit can be realized by a circuit having a simple configuration.
An FIR filtering method having an advantage such as linear phase property is possible with a simple configuration.

According to the second aspect of the invention, the ΔΣ modulation method is used as the oversampling method. As a result, the signal processing accuracy can be improved, and the F
The IR filter can be realized with a very simple structure.

According to the third aspect of the invention, the filtering result output means corresponds to one 1-bit filter coefficient selected from the coefficient storage means and the signal storage means per one filtering result output. One 1-bit input signal is used to output one filtering result. As a result, the filtering process for the 1-bit signal can be performed with a very simple hard-wired logic.

Further, in the invention according to claim 4, the filtering result output means, for each filtering result output, a plurality of 1-bit filter coefficients selected from the coefficient storage means and a corresponding plurality of 1-bit filter coefficients selected from the signal storage means. The 1-bit input signal and the plurality of filtering results are output in parallel. As a result, the number of times of filtering processing can be reduced and the circuit can be operated with a relatively low operation clock.

According to the present invention, the oversampling ratio of the probability density modulation is M, the length of the probability density modulated 1-bit filter coefficient is N · M,
When the numerical value that guarantees the accuracy of the output signal is Q, the number X of output signals from the filtering result output means for one sampling of the probability density modulated signal is X ≧ N ² · Q ² /
M is set to satisfy the relationship of M, or the oversampling ratio of probability density modulation is M, the length of the probability density modulated 1-bit filter coefficient is N · M, and the numerical value that guarantees the accuracy of the output signal is Q. And the number of signals used for filtering is P, the number X of output signals from the filtering result output means for one sampling of the probability density modulated signal is X ≧ N ² Q ² / (M · P)
Are configured to satisfy the relationship. As a result, the expected accuracy of the output signal can be increased.

[0013]

1 is a block diagram of an embodiment of a signal processing apparatus according to the present invention. In the example of FIG. 1, the signal processing device is configured as a signal processing device for acoustic signal processing, and a signal generation unit 1 that generates an acoustic generation signal and an acoustic generation signal from the signal generation unit 1 Signal processing unit 2 for performing processing
And a speaker 4 that outputs sound based on the sound generation signal processed by the signal processing unit 2.

Here, the signal processing unit 2 includes a modulator 5 such as a Δ (delta) modulator or a ΔΣ (delta sigma) modulator.
A filtering unit 6 for performing a filtering process for changing the characteristics of the signal from the modulator 5, and a digital data generating unit 7 for generating digital data for sound generation from the signal resulting from the filtering process. Have

Similarly to the conventional signal processing apparatus shown in FIG. 10, the signal processing apparatus of the present embodiment also has, for example, a virtual speaker 4'at a position different from the actual speaker 4, and the human H is a speaker. The signal output from the virtual sound source 4 is processed so that the sound can be heard as being output from this virtual sound source (virtual speaker 4 '). The configuration is intended to be simpler than that of the conventional one. Therefore, instead of the A / D conversion unit 52 and the digital filter unit 53 of the conventional signal processing device shown in FIG. 10, the modulator 5 is used. ，
The filtering unit 6 and the signal processing unit 2 of the digital data generation unit 7 are provided.

That is, in the signal processing device of FIG. 1, the modulator 5 of the signal processing unit 2 is disclosed in, for example, the document “Nikkei Electronics 1988.7.25 (NO.452), pages 277 to 285”,
"Nikkei Electronics 1988.8.8 (NO.453), 211-2
Page 22 ”,“ Nikkei Electronics 1988.8.22 (NO.45)
4), pp. 277-286 "," Nikkei Electronics 1988.10.
17 (NO.458), pages 223-231 "," Nikkei Electronics
1988.10.31 (NO.459), pages 233 to 239 "," Nikkei Electronics 1988.11.14 (NO.460), pages 271 to 277 ", represented by one bit by the oversampling method. It is designed to get a signal.

2 and 3, as an example of the modulator 5,
The configurations of the Δ modulator and ΔΣ modulator are shown respectively.
Referring to FIG. 2, the Δ modulator includes a voltage comparator 11 as a 1-bit quantizer, a 1-bit D / A converter 12, and
It is composed of an analog integrator 13 and a D flip-flop (1 sample delay device) 14 that holds the output of the comparator 11 only for the time of one sampling cycle. In addition, 1
The bit D / A converter 12 and the analog integrator 13 function as a prediction filter 15 that predicts an input signal. That is, the analog integrator 13 outputs a prediction signal for the input signal.

In such a Δ modulator, the magnitude of the input signal and the prediction signal is compared by the comparator 1 at each sampling timing.
When the input signal is larger, the output of the comparator 11 is “1”. On the contrary, when the predicted signal is larger, the output of the comparator 11 is “0”. Become. When the output of the comparator 11 becomes "1",
The control signal for increasing the prediction signal, and when the output of the comparator 11 is "0", the control signal for decreasing the prediction signal is 1-bit D / The prediction filter 15 of the A converter 12 and the analog integrator 13 is fed back to the prediction filter 1
5 updates the prediction signal according to the feedback signal.

By repeating this operation, the Δ modulator outputs a digital code string (high-speed data string quantized into 1 bit) corresponding to the input signal. As is clear from the above description, this digital code string is an encoded difference between the input signal and the prediction signal, and the Δ modulator encodes it so that the difference between the prediction signal and the input signal is minimized. The conversion is performed.

Further, referring to FIG. 3, the ΔΣ modulator is
Integrator 21 and voltage comparator 2 as 1-bit quantizer
2 and a D flip-flop (1 sample delay device) 2 for holding the output of the comparator 22 for a time of 1 sampling period
3 and a 1-bit D / A converter 24.

This ΔΣ modulator can be regarded as a modification of the Δ modulator. That is, the ΔΣ modulator has the same characteristics as the addition of the integrator to the preceding stage of the Δ modulator shown in FIG. 2, and the integrator 21 of the ΔΣ modulator is the integrator added to the preceding stage of the Δ modulator. And the integrator 13 of the Δ modulator are combined into one.

In the Δ modulator described above, the output is the difference sign between the input signal and the prediction signal, but in the ΔΣ modulator, Δ
Since it has the same characteristics as adding an integrator in the preceding stage of the modulator, it is equivalent to integrating the input signal and then inputting it to the Δ modulator, eliminating the property that the output is a differential code and increasing the slope transient. It is also possible to eliminate the restriction on the input signal due to the load (a phenomenon in which the predictor of the modulator cannot follow the input signal that changes abruptly). That is, the drawback of the Δ modulation method can be improved.

As described above, by using the Δ modulator, the ΔΣ modulator, etc. as the modulator 5, the analog input (the sound generation signal from the signal generating section 1) is quantized into 1 bit and 1
Although it is output as a bit quantized data string, in the present invention, in particular, in order to improve signal processing accuracy and to realize an FIR filter with a simple configuration as described later, the modulator 5 Is better to use a ΔΣ modulator. That is, in the ΔΣ modulator, since the property before sampling remains as it is in the low frequency region, the signal processing accuracy can be improved.

FIG. 4 shows the filtering section 6 of the signal processing section 2.
It is a figure which shows the structural example. In the configuration example of FIG. 4, the filtering unit 6 includes a clock generator 31 that generates a clock CLK and a clock CL from the clock generator 31.
A frequency divider 32 that divides K to generate a divided signal DS, a mono-multivibrator 33 that generates a timing pulse WE from the output from the frequency divider 32, and a timing pulse WE from the mono-multivibrator 33 A signal storage unit (for example, a signal RAM) 34 for controlling the writing of the 1-bit input signal DIN and a logical product of the inversion signal of the clock pulse CLK and the timing pulse WE are obtained, and a signal R is obtained.
A for generating clock pulse CLK ₁ for reading AM34
The ND circuit 35, the counter 36 that counts the clock pulse CLK ₁ and addresses the signal RAM 34 by the count value, and the coefficient storage unit (for example, the coefficient RO that stores the filter coefficient represented by 1 bit).
M) 37, a counter 38 that counts the clock pulse CLK and addresses the coefficient ROM 37 according to the count value, a 1-bit filter coefficient D ₂ that is selectively output from the coefficient storage unit 37, and a selective output from the signal storage unit 34. And a filtering result output unit 39 that calculates a filtering result expressed by 1 bit by using the 1-bit input signal D ₁ .

In the example of FIG. 4, the filtering result output unit 39 is composed of an XOR circuit (exclusive OR circuit). Specifically, the filtering result output unit 39, that is, the XOR circuit is adapted to multiply the 1-bit input signal D ₁ and the 1-bit filter coefficient D ₂ .

FIG. 5 is a diagram for explaining the function of the filtering result output unit 39, that is, the XOR circuit. X
The OR circuit outputs "0" when one of the 1-bit input signal and the 1-bit filter coefficient is "1" and the other is "0", and both the 1-bit input signal and the 1-bit filter coefficient are "0". , Or "1", "1" is output.
The digital data generator 7 connected to the output stage of the XOR circuit processes “1” as “+1” and processes “0” as “−”.
When configured to process as "1", when the "1" is output from the XOR circuit, this is regarded as "+1" in the digital data generation unit 7, and X
When "0" is output from the OR circuit, this is "-
Therefore, when one of the 1-bit input signal and the 1-bit filter coefficient is "1" and the other is "0", the XOR circuit effectively multiplies "+1" and "-1". It is possible to output the result as “0”, that is, “−1”.
When both of the bit filter coefficients are "0" or "1", the XOR circuit is substantially "+1" and "+1".
It is possible to perform multiplication with and or multiplication with "-1" and "-1", and output the result as "1", that is, "+1".

Further, when the filtering result expressed by 1 bit from the filtering unit 6 is input in time series, the digital data generating unit 7 generates digital data for sound generation based on the filtering result input in time series. It is designed to function as a regenerator to generate. Although a specific configuration example of the digital data generation unit 7 will not be described in detail, when a Δ modulator is used as the modulator 5, for example, a counter (digital integrator) can be used, and the modulator can also be used. When a ΔΣ modulator is used for 5, a low pass filter can be used, for example.

In the signal processing unit 2, the output of the modulator 5 such as a Δ modulator or ΔΣ modulator is temporarily generated without providing the filtering unit 6 to generate digital data such as a counter (digital integrator) or a digital low-pass filter. When the signal is input to the unit 7, the signal processing unit 2 uses A / A of the oversampling method disclosed in the above-mentioned document.
It is the same as the D converter. That is, if a circuit similar to the predictive filter used for the modulator (for example, a digital integrator) is connected as a regenerator to the output stage of the Δ modulator, the digital low-pass filter is reproduced at the output stage of the ΔΣ modulator. Digital signal corresponding to the input waveform can be obtained from these regenerators if connected as an A / D converter.
A converter can be constructed. In this case, the Δ modulator,
The A / D converter using the ΔΣ modulator has a shorter sampling interval and a higher speed than the A / D converter 52 of the conventional signal processing device shown in FIG. 11, that is, a normal A / D converter. Sampling can be performed.

In other words, the signal processor 2 of this embodiment is
An oversampling A / D converter including a modulator 5 and a digital data generator 7 is further provided with a 1-bit input / 1-bit output filtering unit 6 between the modulator 5 and the digital data generator 7. In addition, the filtering unit 6 itself for 1-bit input and 1-bit output has a feature.

Next, a specific operation of the signal processing device having such a configuration will be described. In the following description, a ΔΣ modulator is used as the modulator 5 of the signal processing unit 2 and a low-pass filter is used as the digital data generating unit 7.

When the signal for sound generation is generated from the signal generation unit 1 and applied to the signal processing unit 2, the modulator 5 of the signal processing unit 2 performs ΔΣ modulation and converts it into a 1-bit data string, and 1 Filtering unit 6 as bit input signal DIN
Give to. Assuming that the filtering unit 6 has the configuration shown in FIG. 4, the filtering unit 6 receives the 1-bit input signal DIN from the modulator 5 and receives the 1-bit input signal DIN from the modulator 5, for example.
Works like Note that in FIG. 6, the oversampling ratio M of ΔΣ modulation is “5”, and the 1-bit input signal DIN and the 1-bit filter coefficient stored in the coefficient ROM 37 are oversampled by 5 times. The time chart in the case where ten 1-bit filter coefficients W _{0 to} W ₉ (filter coefficient length = 10) are stored in the coefficient ROM 37 is shown.

Referring to FIG. 6, a clock CLK (for example, a frequency of 25.92 MHz) is generated from the clock generator 31.
When the occurrence of 1 occurs, the frequency divider 32 divides the clock CLK into, for example, 1/10 to generate the divided signal DS. The mono-multivibrator 33 also generates a timing pulse WE based on the frequency-divided signal DS from the frequency divider 32. A
The ND circuit 35 takes the logical product of the clock CLK and the inverted signal of the timing pulse WE to generate the clock CLK ₁ for the counter 36. When the 1-bit input signal DIN is received under such various control signals, the 1-bit input signal DIN is stored in the signal storage unit (signal RAM) 34 when the timing pulse (write enable signal) WE is at the high level. Is written. That is, the clock C
F _n−1 , f _n , f at a frequency division timing of 1/10 of LK
_{n + 1} and fn _{+ 2} are sequentially written.

On the other hand, when the timing pulse (write enable signal) WE is at the low level, the signal accumulating section (signal RAM) 34 is in the reading mode, and the data at the address is read out by addressing with the count value of the counter 36. . For example, after f _n is written in the signal storage unit (signal RAM) 34, the 1-bit input signal D is output from the signal storage unit (signal RAM) 34.
_{After fn} , fn _-1 , ..., Fn _-9 are sequentially read as 1 and then fn _{+ 1} is written, a 1-bit input is made from the signal storage unit (signal RAM) 34. As the signal D ₁ , f
_{n + 1} , f _n , ..., F _n-8 are sequentially read.

The counter 38 counts according to the clock CLK, and the coefficient storage section (coefficient ROM) 37.
Is addressed by the count value of the counter 38 and the data at that address is read.
More specifically, the counter 38 uses the timing pulse WE.
Can be configured as a cyclic counter synchronized with, in this case, from the coefficient storage unit (coefficient ROM) 37, after the timing pulse WE becomes low level, as a 1-bit filter coefficients D _2, W _0, W _1, ..., W ₉ are sequentially read.

Filtering result output section, that is, XO
In the R circuit 39, as described above, the signal storage unit (signal RA
M) The 1-bit input signal D ₁ from the 34 and the 1-bit filter coefficient D ₂ from the coefficient storage unit (coefficient ROM) 37 are multiplied. As a result, the filtering result output unit 39
Outputs the filtering result, that is, the output signal as shown in FIG. That is, when the 1-bit data string f _n is input from the modulator 5 to the filtering unit 6,
From the filtering result output unit 39, f _n-9 · W ₉ , f
_{When n-8} · W ₈ , ..., F _n · W ₀ are sequentially output as output signals, and then the 1-bit data string f _{n + 1} is input from the modulator 5 to the filtering unit 6, the filtering result output unit 39 From f _n-8 · W ₉ , f _n-7 · W ₈ , ..., f _{n + 1}
-W ₀ is sequentially output as an output signal.

In the digital data generator 7, the FI is applied to the 1-bit input signal by taking the sum of these.
The result of R (finite impulse response) filtering can be obtained. That is, the value F (n) of the filtered signal is converted into a 1-bit filter coefficient W (k) corresponding to the 1-bit input signal f (n−k) k sampling earlier than the current point n as shown in the following equation. The FIR filtering method expressed by sum of products can be applied.

[0037]

[Equation 1]

The filtering unit 6 also outputs one 1-bit filter coefficient selected from the coefficient storage unit 37 and one corresponding 1-bit input signal selected from the signal storage unit 34 for each filtering result output. The FIR filter can be realized with a very simple circuit configuration by simply performing the calculation using

As described above, in the present embodiment, it is understood that the FIR filter for the 1-bit input signal can be realized with a simple structure. And for 1-bit input signal,
By performing the FIR filtering process, the characteristics of the signal can be changed and a desired sound can be output from the speaker 4. The FIR filter has advantages such as linear phase property, and it is extremely advantageous that the FIR filter can be realized with a simple configuration.

By the way, in the above filtering process, the oversampling ratio of ΔΣ modulation is set to M,
The tap length is N, the length of the ΔΣ-modulated 1-bit filter coefficient is N · M, and the numerical value that guarantees the accuracy of the output signal is Q (Q
> 1), the number X of output signals per 1-bit input signal should satisfy the following equation.

[0041]

[Formula 2] X ≧ N ² · Q ² / M

For example, FIG. 6 shows the case where the length of the ΔΣ-modulated 1-bit filter coefficient is “10”, and here, the information that the oversampling ratio M is “2” is given. If given, the tap length N of the filter is "5" from the following equation.

[0043]

## EQU3 ## N = (length of filter coefficient) / M = 10/2 = 5

In this case, with respect to the number X of output signals per 1-bit input signal, it is preferable that the guaranteed value Q of the accuracy of the output signal satisfies the following equation from the equation (2).

[0045]

[Expression 4] X ≧ 5 ² · Q ² /2=12.5×Q ²

However, since X = 10 from FIG. 7, in this case, Q becomes smaller than "1".
(Q <1). Therefore, the oversampling ratio M is "2".
In this case, if the condition of Expression 2 is satisfied, Q becomes smaller than “1”, which may reduce the accuracy of the output signal.

On the other hand, if the information that the oversampling ratio M is "5" is given, the tap length N of the filter becomes "2" from the following equation.

[0048]

(5) N = (length of filter coefficient) / M = 10/5 = 2

In this case, the condition of Expression 2 is as follows.

[0050]

[Equation 6] X ≧ 2 ² · Q ² /5=0.8×Q ²

From FIG. 7, since X = 10,
In this case, Q ≦ 12.5, and the condition of Q> 1 can also be satisfied. That is, the oversampling ratio M
When is “5”, it is possible to satisfy both the condition of Expression 2 and the condition of Q> 1.

That is, in the ΔΣ-modulated signal, when the original signal normalized by the maximum value is f, the probability P (+1) =
“1” is output at (1 + f) / 2, and the probability P (−1) =
It can be considered as the result (binomial distribution) of repeated trials of outputting "-1" at (1-f) / 2. In this case, as the filtering process, [f (n−k)] XOR [W
If the result of (k)] is output, the expected average value matches the result of normal FIR filtering, but the variance of the actual average value increases as the number X of output signals per time decreases.

Specifically, when the number of output signals during normal sampling is X ', the variance, standard deviation, and average of the deviations are as follows.

[0054]

(Equation 7)

FIG. 8 shows the deviation from the expected value. Here, assuming that P (+1) = P (−1) = 1/2, the number of output signals X ′ satisfies the following equation in order to fall within a predetermined deviation 1 / (2NQ) from the expected value. There is a need.

[0056]

[Expression 8] X '= N ² Q ²

Since X'is the number of output signals during normal sampling, the number X of output signals must satisfy the following expression during one oversampling.

[0058]

[Equation 9] X = N ² Q ² / M

From this, 1 / Q of the maximum value of the output signal
The allowable error is up to 95% reliability and 1 variance
It can be seen that the number X of output signals per input signal must satisfy the equation 2 in order to fall within the range of / Q.

That is, in the above-described filtering unit 6, if no special limitation is imposed on the input signal and the filter coefficient, the number of times the filtering process result is output (output frequency) is set to an extent indicated by X defined by the equation 2. For example, the expected accuracy can be increased, and the value obtained by applying the low-pass filter to the output signal can be set to a value close to the result of normal FIR filtering.

On the other hand, in this filtering unit 6, the capacity of the memory (the capacity of the signal storage unit and the coefficient storage unit) for storing the 1-bit input signal and the 1-bit filter coefficient for the filtering process becomes a serious problem.

Even if the number X of output signals per input signal is larger than the filter length N · M, it is wasteful to repeat the calculation many times with the same coefficient of the filter. To avoid this waste, , The following formula should be satisfied.

[0063]

[Equation 10] N ・ M ≧ X

From Equations 2 and 10, X that minimizes N · M
The following equation is obtained by obtaining.

[0065]

[Equation 11] X = N · M

That is, if signals for all filter coefficients are output for one input signal (in other words, the product of the 1-bit input signal and the 1-bit filter coefficient is
It can be seen that the memory capacity (capacity of the signal accumulating section and coefficient storing section) can be minimized by calculating and outputting for all filter coefficients for one sampling.

When oversampling is performed, the memory is
Since the number of signals to be (accumulated) is expected to increase dramatically as compared to the case of performing normal sampling, it is not possible to minimize the memory capacity by defining the number of output signals X as shown in equation 11. It is very advantageous in the device design.

For example, in the filtering unit 6 of FIG. 4, when the value corresponding to Q is 10, the number of taps N is 36, and the oversampling ratio M is 60, the minimum value of the number of output signals X is 2160. Good. Further, in this case, since the length of the filter coefficient is N · M = 2160, it is understood that when the number of output signals X is 2160, the calculation result of all filter coefficients is output for one sampling.

FIG. 9 is a diagram showing another configuration example of the filtering unit 6. In the example of FIG. 9, the filtering unit 6
Is a clock generator 41 that generates a clock CLK _2.
A plurality of stages of signal storage units (shift registers) 42 for serially inputting 1-bit input signals DIN serially, a coefficient storage unit (coefficient ROM) 43 storing a plurality of 1-bit filter coefficients, and signals The P 1-bit input signals selected from the storage unit 42 and the P 1-bit filter coefficients selected from the coefficient storage unit 43 corresponding to these are used to output the filtering result expressed by 1 bit as P 1 Filtering result output section 44 for outputting in parallel
And a summation unit 45 for summing P filtering results
And have.

In the example of FIG. 9, the filtering result output unit 44 includes P XOR circuits (exclusive OR circuits).
Each XOR circuit is configured to perform multiplication of one 1-bit input signal from the signal accumulator 42 and one corresponding 1-bit filter coefficient from the coefficient storage 43. ing. In such a configuration, for example, assuming that the input signal and the filter coefficient are oversampled 60 times, the clock CLK ₂ is 12 KH.
z frequency, signal storage (shift register)
If the number of stages P of 42 and the number of XOR circuits P are 2160, the signal storage unit (shift register) 42 has 2160.
Pieces of 1-bit input signal data are sequentially accumulated. At this time, in the shift register 42, the oldest data is removed every time one 1-bit input signal is accumulated.

In the filtering result output section 44, 21
The operation (multiplication) for 2160 operates in parallel by the 60 XORs, and the summation unit 45 sums up the 2160 multiplication results and outputs it. Since the output result of the filtering unit shown in FIG. 9 is an analog value in which high frequencies are weighted by noise, it is necessary to further use a low-pass filter for the output value depending on the subsequent processing.

As described above, the filtering unit 6 is configured as shown in FIG.
It is considered that the operation of the filtering section shown in FIG. 4 is performed P times in parallel at the same time. This makes it possible to reduce the number of times the filtering result is output. That is, the number of filtering processes can be reduced. Further, the circuit can be operated with a relatively low operation clock.

Even when the filtering unit 6 is constructed as shown in FIG. 9, the number X of output signals is
Basically, it is subject to the same limitation as the filtering unit shown in FIG. 4, but since P times are output in parallel, the number X of output signals from the filtering unit per sampling of the ΔΣ-modulated signal is The following formula should be satisfied.

[0074]

[Equation 12] X ≧ N ² Q ² / (MP)

By setting the number X of output signals to satisfy the expression 12, the value obtained by applying the low-pass filter to the output signal can be made a value close to the result of normal FIR filtering.

Further, in the configuration of FIG. 9, one result can be output particularly for one ΔΣ-modulated sampling. In this case, the input / output circuit can be operated with the same operation clock for both signal input and output, which facilitates the design of the operation timing.

Specifically, in equation 12, when the numerical value corresponding to Q is 10, N is 36, P is 2160, and M is 60, the number X of output signals per input signal is calculated.
Therefore, it is possible to realize a configuration in which one result is output for one sampling of the ΔΣ modulated signal.

Further, in the configuration of FIG. 9, the sum of the products of the P 1-bit filter coefficients arbitrarily selected from the coefficient storage unit 43 and the corresponding P 1-bit signals selected from the signal storage unit 42 is calculated. , ΔΣ-modulated and output, the output signal also becomes a 1-bit signal, and it is possible to add another digital signal processing after the filtering section.

Specifically, it is also possible to connect an analog low-pass filter in the subsequent stage of the filtering section of FIG. 9 and add the output signal thereof to a ΔΣ modulator to perform ΔΣ modulation.

In this case, the digital signal processing cannot be performed directly in the latter stage of the output, but the circuit configuration becomes simple.

In the above-described embodiment, the ΔΣ modulation is used as the oversampling method. Particularly, by using the ΔΣ modulation, the signal processing accuracy is increased and the FIR filter has a simple structure as described above. However, the present invention is not limited to the ΔΣ modulation, and can be similarly applied to the case where a more broad probability density modulation including the ΔΣ modulation is used as the oversampling method.

Further, in the above-described embodiments, the signal processing device is applied to the acoustic signal processing, but the present invention is not limited to the acoustic signal processing, but may be any other application as long as it changes the characteristics of the signal. It can be used for various purposes.

[0083]

As described above, according to the first aspect of the invention, the signal accumulating means for accumulating the 1-bit input signal represented by 1 bit and the filter coefficient represented by 1 bit are stored. And a filtering result output means for calculating a filtering result by the 1-bit input signal from the signal storage means and the 1-bit filter coefficient from the coefficient storage means. Since the expressed 1-bit input signal is directly filtered to obtain the filtering result expressed by 1-bit, the filtering process for the signal expressed by 1-bit can be realized by a circuit having a simple configuration, and in particular, the linear phase characteristic FI with advantages such as
The R filtering method is possible with a simple configuration.

According to the second aspect of the invention, since the ΔΣ modulation method is used as the oversampling method, the signal processing accuracy can be improved and the FIR processing can be performed.
The filter can be realized with a very simple structure.

According to the third aspect of the present invention, the filtering result outputting means selects one 1-bit filter coefficient selected from the coefficient storing means and the signal accumulating means for each filtering result output. Corresponding 1
One filtering result is output using one 1-bit input signal and
Logic can perform a filtering process on a 1-bit signal.

According to the fourth aspect of the invention, the filtering result output means selects a plurality of 1-bit filter coefficients selected from the coefficient storage means and the signal storage means for each filtering result output. Since a plurality of filtering results are output in parallel by using a plurality of 1-bit input signals, the number of filtering processes can be reduced, and the circuit can be operated with a relatively low operation clock.

According to the inventions of claims 5 and 6,
When the oversampling ratio of the probability density modulation is M, the length of the probability density modulated 1-bit filter coefficient is N · M, and the numerical value that guarantees the accuracy of the output signal is Q, the probability density modulated signal is 1 The number X of output signals from the filtering result output means for sampling is X ≧ N ² ·
It is configured to satisfy the relationship of Q ² / M. Further, the oversampling ratio of probability density modulation is M, the length of the probability density modulated 1-bit filter coefficient is N · M, the numerical value that guarantees the accuracy of the output signal is Q, and the number of multiple signals used for filtering is set. Where P is P, the number X of output signals from the filtering result output means for one sampling of the probability density modulated signal is X ≧ N ² Q ²
Since it is configured to satisfy the relationship of / (MP), the expected accuracy of the output signal can be increased.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a signal processing device according to the present invention.

FIG. 2 is a diagram showing a configuration of a Δ modulator.

FIG. 3 is a diagram showing a configuration of a ΔΣ modulator.

FIG. 4 is a diagram illustrating a configuration example of a filtering unit.

FIG. 5 is a diagram for explaining the function of an XOR circuit.

FIG. 6 is a time chart for explaining the operation of the filtering unit in FIG.

FIG. 7 is a diagram showing a filtering result output from the filtering unit of FIG.

FIG. 8 is a diagram for explaining a deviation of an output signal from an expected value.

FIG. 9 is a diagram illustrating another configuration example of a filtering unit.

FIG. 10 is a diagram showing a configuration example of a conventional signal processing device.

FIG. 11 is a diagram showing a conventional A / D converter.

[Explanation of symbols]

 1 signal generation section 2 signal processing section 4 speaker 5 modulator 6 filtering section 7 digital data generation section 31,41 clock generator 32 minute cycle 33 mono-multivibrator 34,42 signal storage section 35 AND circuit 36 counter 37, 43 coefficient storage Section 38 counter 39,44 filtering result output section 45 summing section

Claims (6)

[Claims] 1. A signal storage means for storing a 1-bit input signal represented by 1 bit, a coefficient storage means for storing a filter coefficient represented by 1 bit, and a 1-bit input signal from the signal storage means. And a filtering result output means for calculating a filtering result by the 1-bit filter coefficient from the coefficient storage means, and the 1-bit input signal expressed by 1 bit by the oversampling method is directly filtered and expressed by 1 bit. A signal processing device, which obtains a filtered result. 2. The signal processing device according to claim 1, wherein
A signal processing apparatus, wherein a ΔΣ modulation method is used for the oversampling method. 3. The signal processing device according to claim 1, wherein
The filtering result output means uses one 1-bit filter coefficient selected from the coefficient storage means and one corresponding 1-bit input signal selected from the signal storage means for each filtering result output, A signal processing device which outputs one filtering result. 4. The signal processing device according to claim 1, wherein
The filtering result output means uses a plurality of 1-bit filter coefficients selected from the coefficient storage means and a plurality of corresponding 1-bit input signals selected from the signal accumulating means for each filtering result output, and performs a plurality of filtering operations. A signal processing device, which outputs results in parallel. 5. The signal processing device according to claim 3,
When the oversampling ratio of the probability density modulation is M, the length of the probability density modulated 1-bit filter coefficient is N · M, and the numerical value that guarantees the accuracy of the output signal is Q, the probability density modulated signal is 1 The number X of output signals from the filtering result output means for sampling is X ≧ N
A signal processing device, characterized in that it is configured to satisfy the relationship of ² · Q ² / M. 6. The signal processing device according to claim 4,
The oversampling ratio of probability density modulation is M, the length of the probability density modulated 1-bit filter coefficient is N · M, the numerical value that guarantees the accuracy of the output signal is Q, and the number of multiple signals used for filtering is P. Then, the number X of output signals from the filtering result output means for one sampling of the probability density modulated signal is X ≧ N ² Q ²
A signal processing device, which is configured to satisfy a relationship of / (M · P).