JPH08264916A - Electric interconnection assembly,solder bump forming method,electrical connecting method and alloy - Google Patents

Electric interconnection assembly,solder bump forming method,electrical connecting method and alloy

Info

Publication number
JPH08264916A
JPH08264916A JP8034444A JP3444496A JPH08264916A JP H08264916 A JPH08264916 A JP H08264916A JP 8034444 A JP8034444 A JP 8034444A JP 3444496 A JP3444496 A JP 3444496A JP H08264916 A JPH08264916 A JP H08264916A
Authority
JP
Japan
Prior art keywords
substrate
wettable
mask
solder
solder bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8034444A
Other languages
Japanese (ja)
Inventor
Zequn Mei
メイ ゼクン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH08264916A publication Critical patent/JPH08264916A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0244—Powders, particles or spheres; Preforms made therefrom
    • B23K35/025—Pastes, creams, slurries
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/264—Bi as the principal constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C12/00—Alloys based on antimony or bismuth
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1216—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by screen printing or stencil printing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide alloy for solder having low hardness, high strength low brittleness and high fatigue resistance and an electrical interconnection assembly using the alloy thereof. SOLUTION: This assembly is an electrical interconnection assembly 354, wherein a wettable region and a non wettable region are specified on the surface and a first substrate 342 and a second substrate 350 are included. A metal mask is arranged on the first substrate. The solder paste comprising Sn-Bi-Ag (or In) is applied on the aperture of the metal mask. The solder paste is made to reflow, and a solder bump 338 is formed on the wettable region. After the bump is formed. the metal mask is removed. The solder bump formed on the first substrate is made to agree with the wettable region on the second substrate. The surface of the first substrate is arranged in parallel with the surface of the second substrate. Reflowing is performed under heating, and the electric connection is formed between the first and second substrates.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、三元共晶（ｔｅｒ
ｎａｒｙ ｅｕｔｅｃｔｉｃ）の挙動を示し、且つスズ
−ビスマス共晶のはんだより１００％の延性の増大を実
現する、ビスマス−スズ−及び第三の金属を包含する無
鉛合金に関する。TECHNICAL FIELD The present invention relates to a ternary eutectic crystal (ter)
It relates to a lead-free alloy comprising bismuth-tin- and a third metal, which exhibits a nary eutectical behavior and which achieves a 100% increase in ductility over tin-bismuth eutectic solders.

【０００２】[0002]

【技術背景】電子部品の組立には電気的接続が必要であ
り、接続は、典型的に、１種類以上のはんだを必要とし
てきた。BACKGROUND OF THE INVENTION The assembly of electronic components requires electrical connections, which typically have required more than one type of solder.

【０００３】低温はんだは、電子回路組立工程におい
て、リフロー温度（ｒｅ−ｆｌｏｗｔｅｍｐｅｒａｔｕ
ｒｅ）を下げるのに有用である。本明細書で用いられる
低温は、６３Ｓｎ−３７Ｐｂ（共晶）合金のそれより低
い融点を有するはんだ付け合金に該当する。６３Ｓｎ−
３７Ｐｂはんだに対するリフロー温度は、２２０℃で発
生する。電子回路組立に低温はんだを使うことにより、
リフロー温度を低下させる。比較的低い温度のリフロー
の利点は：１）温度感知部品のコスト低減；２）基板、
はんだ及び種々の部品の間の熱膨張係数の差に起因する
熱衝撃のリスクの軽減；３）階層組立の選択の実現、が
含まれる。鉛の無いはんだは、環境のハザード（ｈａｚ
ａｒｄ）を軽減する。さらに、部品及び接続はどんどん
小さくなっているので、電子実装工業では、電気的接続
としてのみならず機械的支持としても同様に役立ち得る
はんだをますます必要としている。Low temperature solder is a re-flow temperature (re-flow temperature) in an electronic circuit assembly process.
re) is useful. The low temperatures used herein refer to soldering alloys that have melting points lower than that of 63Sn-37Pb (eutectic) alloy. 63Sn-
The reflow temperature for 37Pb solder occurs at 220 ° C. By using low temperature solder for electronic circuit assembly,
Lower the reflow temperature. The advantages of relatively low temperature reflow are: 1) cost reduction of temperature sensing components; 2) substrate,
Reducing the risk of thermal shock due to the difference in coefficient of thermal expansion between the solder and the various components; 3) implementing a choice of hierarchical assembly. Lead-free solder is an environmental hazard.
ard) is reduced. Moreover, as components and connections are becoming smaller and smaller, the electronic packaging industry is increasingly requiring solders that can serve not only as electrical connections but also as mechanical supports.

【０００４】５８Ｂｉ−４２Ｓｎ（ビスマス−スズ）合
金は、電子実装における用途が限定される。それは、６
３Ｓｎ−３７Ｐｂより大きい強度とクリープ抵抗（ｃｒ
ｅｅｐ ｒｅｓｉｓｔａｎｃｅ）を示すが、その延性及
び疲労抵抗が劣るので、その有用性が極めて低下する。
５８Ｂｉ−４２Ｓｎ合金の延性及び疲労抵抗の劣性のた
め、結果としての組立体が梱包及び出荷の過酷さに適切
に耐えることができないという理由から、電子実装及び
組立におけるその有用性が大いに限定される。従って、
その電子部品の接続部が５８Ｂｉ−４２Ｓｎではんだ付
けされている製品は、特に今日の過度の要求をする使用
者並びに競合市場に適合させるには、十分信頼できな
い。The 58Bi-42Sn (bismuth-tin) alloy has limited applications in electronic packaging. It is 6
Strength and creep resistance (cr) greater than 3Sn-37Pb
However, since its ductility and fatigue resistance are poor, its usefulness is extremely reduced.
The poor ductility and fatigue resistance of the 58Bi-42Sn alloy greatly limits its utility in electronic packaging and assembly because the resulting assembly cannot adequately withstand the rigors of packaging and shipping. . Therefore,
Products whose electronic component connections are soldered with 58Bi-42Sn are not sufficiently reliable, especially to meet today's over-demanding users as well as the competitive market.

【０００５】ビスマス−スズはんだペーストの混合物が
金又は銀で電気めっきされた表面に適用され、そして
（ビスマス−スズの溶融温度より高い温度で生ずる）リ
フロー中に電気めっきされた金属が溶けて接続を形成す
ることが報告されている（Ｍｅｌｔｏｎ等、米国特許第
５，３２０，２７２号）。そのように形成された接続は
硬度が高く、従って、電子実装が使用中に受ける温度変
位に耐えるよう接続の特性を改善することが主張されて
きた。しかし、強度だけが増大すると、脆性が増え、結
果として疲労寿命が短くなり又は初期疲労を招来するこ
とになる。共晶のＢｉ−Ｓｎは、十分な強度とクリープ
抵抗を示すが、使用期間即ち必要な延性と疲労抵抗が不
足する。最適の接続とは、疲労寿命（動作時間）の増加
と延性（横せん断に耐える性質）の増大という機械的特
性を示すものである。さらに、そのような接続を形成す
るプロセスによって、直ちに作業者環境に対するハザー
ドが極力小さく抑えられるべきであり、しかも全体とし
て環境と調和しなければならない。３つの金属から成る
合金は、電子回路の組立の目的には、三元共晶として又
は“三元に近い”（ｎｅａｒ−ｔｅｒｎａｒｙ）共晶と
して挙動することも望まれる。A mixture of bismuth-tin solder paste is applied to the gold or silver electroplated surface and the electroplated metal melts and connects during reflow (which occurs above the melting temperature of bismuth-tin). (Melton et al., US Pat. No. 5,320,272). It has been argued that the connections so formed are rigid and therefore improve the properties of the connections to withstand the temperature excursions experienced by electronic packaging during use. However, if only strength increases, brittleness increases, and as a result, fatigue life becomes short or initial fatigue is caused. Eu-eutectic Bi-Sn exhibits sufficient strength and creep resistance, but lacks the period of use, that is, the required ductility and fatigue resistance. The optimum connection exhibits mechanical properties of increased fatigue life (operating time) and ductility (property to withstand transverse shear). Furthermore, the process of making such connections should immediately minimize the hazards to the worker's environment and yet be in harmony with the environment as a whole. It is also desired that the alloy of three metals behaves as a ternary eutectic or as a "near-ternary" eutectic for the purpose of assembling electronic circuits.

【０００６】[0006]

【発明の目的】本発明は、低硬度、高強度、低脆性で、
高疲労抵抗を有する、従って電子実装の使用中における
特性が良好な、はんだ用の合金と、この合金を使用した
電気的相互接続組立体を提供することを目的とする。OBJECT OF THE INVENTION The present invention is of low hardness, high strength, low brittleness,
It is an object to provide an alloy for soldering, which has a high fatigue resistance and thus good properties during use in electronic packaging, and an electrical interconnection assembly using this alloy.

【０００７】本発明における合金及びはんだの組成は、
鉛を含有せず、低溶融温度を有し、且つ電気的接続及び
機械的支持の両方に有用な組成となる有益な機械的特性
を有するものである。The alloy and solder compositions in the present invention are as follows:
It is lead-free, has a low melting temperature, and has beneficial mechanical properties that make it a useful composition for both electrical connection and mechanical support.

【０００８】[0008]

【発明の概要】本発明は、合金、より詳細には、電子回
路の組立及び実装に適用される合金に関する新処方を包
含する。さらに詳細には、本発明は、三元合金の金属粉
末から作られるはんだペーストを包含する。その合金
は、本質的に、３つの構成要素：ビスマス、スズ、及び
インジウムと銀から成る群から選択される第三の金属を
含有するものである。三元金属は、比較的小量、即ち２
重量％未満で存在する。ビスマス及びスズは、重量で存
在する。３つの構成要素から成る合金は、三元又は三元
に近い共晶として挙動し、且つ単一の温度、即ち約１３
６〜１３７℃の狭い温度範囲で溶融する。合金の共晶特
性を用いれば、電子回路組立中の加熱を軽減でき（比較
的短期間の比較的少ない熱）、別法でははんだを溶融す
るのに要する高温に耐えることができないという理由か
ら使用できなかった部品を、選択することが可能とな
る。そのような部品は、より高い温度に耐えることがで
きる材料から特に設計されたそれらの同等品より、ほと
んど常に低廉である。またここに教示される合金の共晶
特性で最低の粘性が得られ、そして低粘性はウエーブ・
ソルダリング（ｗａｖｅ ｓｏｌｄｅｒｉｎｇ）を容易
化することになる。さらに、本発明の実体に“含有ペー
スト・デポジション”（ｃｏｎｔａｉｎｅｄ ｐａｓｔ
ｅ ｄｅｐｏｓｉｔｉｏｎ−ＣＰＤ）として知られてい
る結合はんだバンピング（ｂｕｍｐｉｎｇ）プロセスを
含む他のはんだ付け技法においても、優れた結果がその
新合金から期待される。ＣＰＤは、ペーストを特殊マス
クの事前に軸調整されたアパーチャの中へ押し込み、そ
のマスク−基板−ペースト組立体を加熱し、そしてはん
だボール形成後そのマスクを除去することによって、基
板のぬれ可能領域（ｗｅｔｔａｂｌｅ ｒｅｇｉｏｎ
ｓ）上にはんだペーストをステンシル印刷（ｓｔｅｎｃ
ｉｌｌｉｎｇ）する工程を利用するものである。ＣＰＤ
により、清浄且つ迅速なはんだバンピング処置の特典と
して、電気めっき及び全ての関連設備が不要となる。本
発明における合金を採用している組立回路は、疲労寿命
と延性が１００％のオーダで増大することを立証し、梱
包及び出荷に関わる機械的ストレス並びに動作上の熱及
び他のストレスに耐えることができるさらに頑丈な相互
接続に転換するものである。SUMMARY OF THE INVENTION The present invention includes a new formulation for alloys, and more particularly for alloys applied in the assembly and packaging of electronic circuits. More specifically, the present invention includes a solder paste made from ternary alloy metal powder. The alloy is essentially one that contains three components: bismuth, tin, and a third metal selected from the group consisting of indium and silver. Tertiary metals are relatively small, ie 2
Present in less than weight percent. Bismuth and tin are present by weight. The three component alloy behaves as a ternary or near ternary eutectic and at a single temperature, ie about 13
It melts in a narrow temperature range of 6 to 137 ° C. Used because the eutectic properties of the alloy can be used to reduce heating during electronic circuit assembly (less heat for a relatively short period of time) and otherwise cannot withstand the high temperatures required to melt solder It is possible to select a part that could not be done. Such parts are almost always cheaper than their counterparts, which are specifically designed from materials that can withstand higher temperatures. The eutectic properties of the alloys taught herein also provide the lowest viscosities, and low viscosities
This will facilitate the soldering. Further, the substance of the present invention is "contained paste deposition" (contained paste).
Excellent results are also expected from the new alloys in other soldering techniques, including the bonded solder bumping process known as e-deposition-CPD). The CPD is a wettable area of a substrate by pushing the paste into the pre-aligned apertures of a special mask, heating the mask-substrate-paste assembly, and removing the mask after solder ball formation. (Wettable region
s) Stencil printing (stenc) of solder paste on
illing) is used. CPD
This eliminates the need for electroplating and all associated equipment as a benefit of clean and rapid solder bumping procedures. Assembly circuits employing the alloys of the present invention demonstrate increased fatigue life and ductility on the order of 100% and withstand mechanical and operational heat and other stresses associated with packaging and shipping. It is a switch to a more robust interconnect that can.

【０００９】[0009]

【発明の実施の形態】好ましい具体例では、本発明によ
るペーストは、基板上及びその間で電気的相互接続を作
り出すために、無鉛三元又は三元に近い共晶合金接続を
形成するのに用いられる。合金ペーストは、２つの基板
を物理的に付着させ且つ電気的に接続して、機械的支持
並びに電気的相互接続を実現する接続を形成する。In a preferred embodiment, the paste according to the present invention is used to form lead-free or near ternary eutectic alloy connections to create electrical interconnections on and between substrates. To be The alloy paste physically attaches and electrically connects the two substrates to form a connection that provides mechanical support as well as electrical interconnection.

【００１０】本発明による好ましいペーストは、所望合
金の金属粉末から作ることができた。所望合金は、本質
的には、次の成分要素から形成される：スズ（４８重量
％）、ビスマス（５０〜５１．５重量％）、及び銀又
は、その代わりとして、インジウム（０．５〜１．５重
量％）。ペースト状の同合金の供給者は、Ｉｎｄｉｕｍ
Ｃｏｒｐｏｒａｔｉｏｎ ｏｆ Ａｍｅｒｉｃａであっ
た。The preferred pastes according to the invention could be made from metal powders of the desired alloys. The desired alloy is essentially formed from the following constituent elements: tin (48% by weight), bismuth (50-51.5% by weight) and silver or, alternatively, indium (0.5-% by weight). 1.5% by weight). The supplier of the pasty alloy is Indium
It was a Corporation of America.

【００１１】代替具体例では、金が可能なように、銀を
インジウムに置き換えてよい。スズの重量％は約４８％
に留まり（可能範囲は４７〜４９％）；ビスマスと三元
要素の配合比は、好ましくは約０．５〜２．０％まで変
わる第三の要素に伴って変化してよく、残余はビスマス
で調製される。第三の要素の上限は、高過ぎると得られ
る合金の延性に悪影響を及ぼす可能性があるので、約４
％である。このように、今までの実験では、約５０Ｂｉ
−４８Ｓｎ−２Ａｇで最良の延性を示している。同様の
結果は、インジウムでも期待される。実験では、好まし
い具体例は、ＮＩＳＴによって計算されるような三元共
晶の特性を明示する合金を産することを示した（図７参
照）。In an alternative embodiment, silver may be replaced with indium so that gold is possible. About 48% by weight of tin
(Possible range 47-49%); the blending ratio of bismuth and ternary element may vary with the third element, preferably varying from about 0.5-2.0%, the balance being bismuth. Is prepared in. The upper limit of the third factor is about 4 as it can adversely affect the ductility of the resulting alloy if too high.
%. Thus, in the experiments so far, about 50 Bi
The best ductility is shown at -48Sn-2Ag. Similar results are expected with indium. Experiments have shown that the preferred embodiment yields alloys that exhibit ternary eutectic properties as calculated by NIST (see Figure 7).

【００１２】図１及び図２は、銅板間で２つの合金、５
８Ｂｉ−４２Ｓｎと５０Ｂｉ−４８Ｓｎ−２Ａｇから形
成されるはんだ接合について、３種類の温度（２０℃、
６５℃及び１１０℃）及び２種類のひずみ速度（それぞ
れ、０．０１ｓｅｃｏｎｄ−１及び０．００１ｓｅｃｏ
ｎｄ−１）でのせん断試験の結果を示す。本発明におけ
る合金の延性の値（ここで、延性とは、はんだ接合が剥
離する以前に保持しているひずみ量として見られるもの
である）は、事実上、全ての試験条件において５８Ｂｉ
−４２Ｓｎより明らかに大きい。疲労寿命の実験結果
は、１００％の疲労寿命の増加を立証するであろうこと
が期待される。同様の結果は、第三の金属がインジウム
である場合の接続からも得られるであろうことが期待さ
れる。1 and 2 show two alloys, 5 between copper plates.
For solder joints formed from 8Bi-42Sn and 50Bi-48Sn-2Ag, three types of temperatures (20 ° C,
65 ° C. and 110 ° C.) and two strain rates (0.01 second −1 and 0.001 sec, respectively)
The result of the shearing test at nd −1 ) is shown. The ductility value of the alloys of the present invention (where ductility is the amount of strain held before the solder joint peels) is virtually 58 Bi under all test conditions.
Clearly larger than -42Sn. It is expected that the fatigue life experimental results will demonstrate a 100% increase in fatigue life. It is expected that similar results will be obtained from connections where the third metal is indium.

【００１３】好ましい具体例では、図３の３Ａ〜図４の
３Ｈを参照して説明すれば、本発明は、２つの基板間で
電気的衝撃波が流れるように１つの基板を他に接続可能
な、バンプ（ｂｕｍｐ）を含む電気伝導性結合構造体を
形成するのに用いられる。In the preferred embodiment, described with reference to 3A of FIG. 3 to 3H of FIG. 4, the present invention allows one substrate to be connected to another so that an electrical shock wave can flow between the two substrates. , Used to form an electrically conductive bond structure including bumps.

【００１４】図５に略述したように、ＣＰＤ法に用いら
れる合金は、一般的に、次の処置を包含する：基板、マ
スク及びペースト（この場合、本発明の合金）を選択す
るステップ４１０；基板とマスクを組立るステップ４１
２；基板−マスクを軸調整するステップ４１４；ペース
トをデポジットするステップ４１６；基板−マスク−ペ
ーストをリフローするステップ４２２；マスクを除去す
るステップ４２４；マスクを洗浄するステップ４３０；
マスクを別の反復プロセスに再使用するステップ。ある
いは、ある種の補助的方法では、マスクは除去しない。
さらに、全ての方法論の変更は、はんだペースト・デポ
ジションの均一な厚み及びボール配置を確保するため
に、中間検査ステップ４１８、４２６及び手直しステッ
プ４２０、４２８を包含する。もしぬれ不可能表面が使
われるなら、バンプされた基板よりはむしろ、容積を制
御したはんだボールが作られる。As outlined in FIG. 5, the alloys used in the CPD method generally include the following steps: Step 410 of selecting the substrate, mask and paste (in this case the alloy of the invention). Step 41 of assembling the substrate and the mask
2; substrate-mask alignment step 414; paste deposition step 416; substrate-mask-paste reflow step 422; mask removal step 424; mask cleaning step 430;
Reusing the mask for another iterative process. Alternatively, some auxiliary methods do not remove the mask.
In addition, all methodological changes include intermediate inspection steps 418, 426 and rework steps 420, 428 to ensure uniform thickness and ball placement of the solder paste deposition. If non-wettable surfaces are used, volume controlled solder balls are made rather than bumped substrates.

【００１５】図３の３Ａ〜図４の３Ｈは、フリップチッ
プ（ｆｌｉｐ ｃｈｉｐ）の形成及びフリップチップの
組立に用いられるような合金を包含して説明するもので
ある。ぬれ可能即ちはんだ可能領域３２２又ははんだ可
能なバンプ制限金属（ＢＬＭ）領域が付着されている表
面３２１又は活性側面を有する選択基板３２０が、電気
的相互接続の形成のために選択される。好ましい具体例
では、選択される基板は、デポジットされる合金によっ
て“ぬらす”ことが可能なＢＬＭを付けたシリコンウェ
ハである。亜鉛化パッド（無電解Ｚｎ、Ｎｉで処理さ
れ、次いでＡｕめっきされたＡｌパッド）を有し、且つ
ＳｉＮ（窒化シリコン）で不活性化されたシリコンウェ
ハは、好ましい具体例の基板／ＢＬＭの組合せである。
４００ミクロン未満のピッチではんだ可能な（もしくは
ぬれ可能な）ＢＬＭを有するウェハを作成することは、
簡単且つ効果的である。各ぬれ可能なＢＬＭの間の中心
間距離は、バンプのピッチに一致し；好ましい具体例で
は、１５０〜３５０ミクロンの範囲のピッチが設けられ
る。この最小ピッチ限界は、現在はマスク技術で左右さ
れ、マスク成形技術の改善で、さらに小さいピッチでさ
え、本発明により達成される。3A to 3H of FIG. 3 are intended to be described inclusive of alloys such as those used in flip chip formation and flip chip assembly. A selectable substrate 320 having a wettable or solderable area 322 or a surface 321 to which solderable bump limiting metal (BLM) areas are attached or active sides is selected for the formation of electrical interconnects. In the preferred embodiment, the substrate of choice is a BLM-loaded silicon wafer that is "wettable" by the alloy being deposited. Silicon wafers with zincated pads (Al electroless Zn, Ni treated, then Au plated Al) and passivated with SiN (silicon nitride) are preferred substrate / BLM combination. Is.
Creating a wafer with solderable (or wettable) BLM at a pitch of less than 400 microns is
Easy and effective. The center-to-center distance between each wettable BLM corresponds to the pitch of the bumps; in the preferred embodiment, a pitch in the range of 150-350 microns is provided. This minimum pitch limit is now dominated by mask technology, and with improvements in mask molding technology, even smaller pitches are achieved by the present invention.

【００１６】基板表面３２１の残りの領域は、ぬれ不可
能領域（例えば、ポリイミド、窒化シリコン、又は二酸
化シリコンのようなぬれ不可能材料で被覆された基板領
域）３２４でなければならない。５０Ｂｉ−４８Ｓｎ−
２Ａｇバンプに関する好ましい具体例では、シリコンウ
ェハは、Ｎｉ−Ａｕのぬれ可能領域と窒化シリコンのぬ
れ不可能領域とを有する。The remaining area of the substrate surface 321 must be a non-wettable area (eg, a substrate area coated with a non-wettable material such as polyimide, silicon nitride, or silicon dioxide) 324. 50Bi-48Sn-
In a preferred embodiment for 2Ag bumps, the silicon wafer has wettable regions of Ni-Au and non-wettable regions of silicon nitride.

【００１７】次に、基板３２０、マスク３２６及びはん
だ３３４の全体の組立体は、はんだ３３４がリフローす
るよう加熱される（図３の３Ｃ参照）。即ち、はんだペ
ーストと金属球３３４が、単一の球即ちマスクアパーチ
ャ３３０当り１つのはんだバンプ３３８に合体するまで
それを加熱する。The entire assembly of substrate 320, mask 326 and solder 334 is then heated to reflow the solder 334 (see 3C in FIG. 3). That is, it is heated until the solder paste and metal sphere 334 coalesce into one solder bump 338 per single sphere or mask aperture 330.

【００１８】含有ペースト・デポジションのリフロー処
理は、標準の表面取付処理（ＳＭＴ）に用いられるそれ
とほとんど同一である。金属粉末のコアレッセンス（ｃ
ｏａｌｅｓｃｅｎｃｅ）を促進して金属バンプを形成す
るために、３つのよく知られた時間−温度領域をリフロ
ー・プロフィル（ｒｅｆｌｏｗ ｐｒｏｆｉｌｅ）で維
持しなければならない：The reflow process of the contained paste deposition is almost identical to that used in the standard surface mount process (SMT). Coalescence of metal powder (c
In order to promote oalescence and form metal bumps, three well-known time-temperature regimes must be maintained in the reflow profile:

【００１９】１．溶媒の蒸発：プロセスのスキージング
（ｓｑｕｅｅｇｅｅｉｎｇ）部分を制御するために、は
んだペーストに溶媒が添加される。これらの溶媒は、リ
フロー操作中に（金属の溶融に先立って）蒸発しなけれ
ばならない。様々なはんだペーストの調製には、種々の
温度と時間を必要とする。1. Solvent Evaporation: Solvent is added to the solder paste to control the squeegeeing portion of the process. These solvents must evaporate (prior to melting the metal) during the reflow operation. Preparation of different solder pastes requires different temperatures and times.

【００２０】２．フラックスの活性化：金属粉末を単一
の金属バンプにコアレッセンスするために、並びにアン
ダーバンプ・メタライゼーション（ｕｎｄｅｒ−ｂｕｍ
ｐｍｅｔａｌｌｉｚａｔｉｏｎ）に対して金属結合を形
成するために、はんだペーストと基板の温度を、前述の
温度で特定の長さの時間の間維持して、はんだペースト
中の活性化因子が、アンダーバンプ・メタライゼーショ
ン及び個々の金属粒子のそれぞれの表面の両方から金属
酸化物を除去できるようにしなければならない。５０Ｂ
ｉ−４８Ｓｎ−２Ａｇに関するフラックス活性化温度
は、１３０℃未満であることが予想される。他のはんだ
ペーストの調製には、種々の温度と時間を必要とする。2. Flux activation: for coalescing metal powder into single metal bumps, as well as under-bump metallization (under-bum)
In order to form a metal bond to the metallization, the temperature of the solder paste and the substrate is maintained at the above temperature for a certain length of time so that the activator in the solder paste has an under bump metallurgy. It must be possible to remove the metal oxides both from the activation and the respective surface of the individual metal particles. 50B
The flux activation temperature for i-48Sn-2Ag is expected to be below 130 ° C. Preparation of other solder pastes requires various temperatures and times.

【００２１】３．最高温度：一般的なリフローはんだ付
けの実施では、最高はんだ温度は、はんだ粉末の融点よ
り３０〜５０℃高い温度にすべきであると推奨されてい
る。本発明における共晶又は共晶に近い合金に関して
は、リフローの最高温度は、１５５℃と１７０℃の間で
ある。他の金属合金は、種々の融点を有し、種々の最高
温度を使う必要がある。3. Maximum Temperature: In typical reflow soldering practices, it is recommended that the maximum solder temperature should be 30 to 50 ° C. above the melting point of the solder powder. For eutectic or near eutectic alloys in the present invention, the maximum reflow temperature is between 155 ° C and 170 ° C. Other metal alloys have different melting points and require the use of different maximum temperatures.

【００２２】最高温度変化率は、標準の表面取付組立プ
ロセスとは多少異なる。標準の表面取付リフロー・プロ
セスでは、最高温度変化率は、急速な温度変化に耐える
一定の表面取付部品の性能によって記述される。含有ペ
ースト・デポジションでは、最高温度変化率は、マスク
と基板が同一の率で温度を変えるという必要条件で決め
られる。The maximum rate of temperature change is somewhat different from the standard surface mount assembly process. In the standard surface mount reflow process, the maximum rate of temperature change is described by the ability of certain surface mount components to withstand rapid temperature changes. For contained paste deposition, the maximum rate of temperature change is determined by the requirement that the mask and substrate change temperature at the same rate.

【００２３】リフロー・プロセス中にバンプが形成さ
れ、且つその組立体が冷却された後、はんだペースト・
フラックスのベヒクル（ｖｅｈｉｃｌｅ）の一部が残留
し（残渣）そしてマスク３２６を基板３２０へ付着させ
る可能性がある。これらの残渣は、マスクと基板を適当
な溶剤に浸せば溶解する。初めの具体例では、イソプロ
ピルアルコール５０％と水５０％の混合液により、残渣
が溶解し、マスクを基板から除去することができる。分
離後、基板とマスクは、さらに十分洗浄する。洗浄後、
マスクは別の基板に再利用できるようプロセスのスター
ト点へ戻す。After the bumps have been formed during the reflow process and the assembly has cooled, the solder paste
Some of the flux vehicle may remain (residue) and cause mask 326 to adhere to substrate 320. These residues dissolve if the mask and substrate are dipped in a suitable solvent. In the first specific example, a mixture of 50% isopropyl alcohol and 50% water dissolves the residue, and the mask can be removed from the substrate. After the separation, the substrate and the mask are further thoroughly washed. After washing
The mask is returned to the starting point of the process so that it can be reused on another substrate.

【００２４】なお、図６に、本発明の好ましい具体例に
おけるマスクと基板の組立法を示す。FIG. 6 shows a method of assembling the mask and the substrate in the preferred embodiment of the present invention.

【００２５】本発明における合金は、そのいくつかの利
点の中でも、低粘性と高延性を有し、現在知られている
又はこれから開発される電気的相互接続の他の形成方法
において望ましい。The alloys of the present invention, among other advantages, have low viscosity and high ductility and are desirable in other methods of forming electrical interconnects now known or to be developed.

【００２６】以上のように、本発明は、〔１〕それぞれ
の表面がぬれ可能な領域とぬれ不可能な領域とに予め規
定されている第一の基板（３４２）及び第二の基板（３
５０）を含んで成る電気的相互接続組立体（３５４）で
あって： Ａ）第一の基板が、その表面のぬれ可能な領域上に、次
のステップにより、はんだバンプ（３３８）が形成さ
れ： ａ）マスク（３３０）の複数のアパーチャがぬれ可能な
領域（３２２）と軸調整されるように、ぬれ不可能な金
属マスク（３２６）を第一の基板の表面に配置するステ
ップ； ｂ）はんだペースト（３３４）がマスク・アパーチャを
埋めるように、スズ−ビスマス−銀から成るはんだペー
ストを金属マスクに適用するステップ； ｃ）はんだペーストをリフローしてぬれ可能な領域上に
はんだバンプを形成するステップ；及び ｄ）はんだバンプ（３３８）の形成後、金属マスク（３
２６）を除去するステップ； Ｂ）そして、この第一の基板（３４２）上に形成された
はんだバンプが、第二の基板（３５０）の表面上のぬれ
可能な領域と合致するよう、第一の基板の表面を第二の
基板の表面に実質的に平行に配置し且つ、加熱下で、リ
フローして第一及び第二の基板間で電気的接続を形成さ
せるステップ；によって製作されて成る電気的相互接続
組立体（３５４）に関する。As described above, according to the present invention, [1] each of the first substrate (342) and the second substrate (3) has its surface preliminarily defined as a wettable region and a non-wettable region.
50) An electrical interconnect assembly (354) comprising: A) a first substrate having solder bumps (338) formed on the wettable area of its surface by the following steps. A) disposing a non-wettable metal mask (326) on the surface of the first substrate such that the multiple apertures of the mask (330) are aligned with the wettable area (322); b). Applying a tin-bismuth-silver solder paste to the metal mask so that the solder paste (334) fills the mask aperture; c) reflowing the solder paste to form solder bumps on the wettable area. Step; and d) after formation of solder bumps (338), metal mask (3
26) removing B) and so that the solder bumps formed on the first substrate (342) match the wettable areas on the surface of the second substrate (350). Arranging the surface of the substrate substantially parallel to the surface of the second substrate and reflowing under heat to form an electrical connection between the first and second substrates. 1. Related to electrical interconnection assembly (354).

【００２７】また、本発明は、〔２〕複数のぬれ可能な
パッドを有する基板上に三元共晶のはんだバンプを直接
形成する方法であって： ａ）マスクの複数のアパーチャがパッドと軸調整される
ように、ぬれ不可能な金属マスクを基板上に配置するス
テップ（４１０、４１２、４１４）； ｂ）はんだペーストがマスク・アパーチャを埋めるよう
に、それぞれ５０：４８：２と５１．５：４８：０．５
の間の重量比のビスマス−スズ−銀又はビスマス−スズ
−インジウムの群から選択されるはんだペーストを金属
マスクに適用するステップ（４１６）； ｃ）はんだペーストをリフローしてパッド上にはんだバ
ンプを形成するステップ（４２２）；及び ｄ）はんだバンプの形成後、金属マスクを除去するステ
ップ（４２４）；を含んで成るはんだバンプの形成方法
に関し、次のような好ましい実施態様を有する。The invention also provides [2] a method of directly forming ternary eutectic solder bumps on a substrate having a plurality of wettable pads: a) a plurality of apertures in a mask and pads. Placing a non-wettable metal mask on the substrate as adjusted (410, 412, 414); b) 50: 48: 2 and 51.5, respectively, so that the solder paste fills the mask aperture. : 48: 0.5
Applying a solder paste selected from the group of bismuth-tin-silver or bismuth-tin-indium in a weight ratio between 416 to the metal mask; c) reflowing the solder paste to form solder bumps on the pad. Forming (422); and d) removing the metal mask after forming the solder bumps (424); and having the following preferred embodiments.

【００２８】〔３〕はんだペーストが、ビスマス、ス
ズ、及び銀とインジウムから成る群から選択される第三
の要素から成る無鉛の共晶三元合金の群から選択され、
且つ相互接続の溶融温度がビスマス−スズ共晶の溶融温
度より低くなるよう前記第三の要素がビスマスとスズと
の相対量で存在することを特徴とする〔２〕記載の方
法。[3] The solder paste is selected from the group of lead-free eutectic ternary alloys consisting of bismuth, tin, and a third element selected from the group consisting of silver and indium,
And the third element is present in relative amounts of bismuth and tin such that the melting temperature of the interconnect is lower than the melting temperature of the bismuth-tin eutectic.

【００２９】さらに、本発明は、〔４〕表面がぬれ可能
な領域とぬれ不可能な領域とに予め規定されている第一
の基板（３４２）及び第二の基板（３５０）を含んで成
る電気的相互接続組立体（３５４）であって： Ａ）第一の基板が、その表面のぬれ可能な領域（３２
２）上に、次のステップにより、はんだバンプ（３３
８）が形成され： ａ）マスク（３２６）の複数のアパーチャ（３３０）が
ぬれ可能な領域（３２２）と軸調整されるように、ぬれ
不可能な金属マスク（３２６）を第一の基板の表面に配
置するステップ； ｂ）ビスマス−スズ−ｘ（ここで、ｘは実質的に銀とイ
ンジウムから成る群から選択される化合物であり、且つ
ｘは相互接続の溶融温度がビスマス−スズ共晶の溶融温
度より低くなるのに有効な量で存在）を含有するはんだ
ペースト（３３４）を、はんだペーストがマスク・アパ
ーチャを埋めるように、金属マスクに適用するステッ
プ； ｃ）はんだペーストをリフローしてぬれ可能な領域上に
はんだバンプ（３３８）を形成するステップ；及び ｄ）はんだバンプの形成後、金属マスク（３３６）を除
去するステップ； Ｂ）そして、この第一の基板上のはんだバンプが第二の
基板（３５２）上のぬれ可能な領域と合致するよう、第
一の基板の表面を第二の基板の表面に実質的に平行に配
置し且つ、加熱下で、リフローして第一及び第二の基板
間で電気的接続を形成させるステップ；によって作製さ
れて成る電気的相互接続組立体（３５４）に関する。Furthermore, the present invention comprises [4] a first substrate (342) and a second substrate (350) whose surfaces are defined in advance in wettable areas and non-wettable areas. An electrical interconnect assembly (354) comprising: A) a first substrate having a wettable area (32) on its surface.
2) the solder bumps (33
8) is formed: a) A non-wettable metal mask (326) is deposited on the first substrate so that the apertures (330) of the mask (326) are aligned with the wettable area (322). B) bismuth-tin-x, where x is a compound selected from the group consisting essentially of silver and indium, and x is a bismuth-tin eutectic with a melting temperature of the interconnect. A solder paste (334), which is present in an amount effective to be below the melting temperature of,) to the metal mask so that the solder paste fills the mask aperture; c) reflowing the solder paste. Forming solder bumps (338) on the wettable area; and d) removing the metal mask (336) after forming the solder bumps; B) and this Arranging the surface of the first substrate substantially parallel to the surface of the second substrate and heating so that the solder bumps on the one substrate match the wettable areas on the second substrate (352). And reflowing to form an electrical connection between the first and second substrates, below.

【００３０】また、本発明は、〔５〕複数のぬれ可能な
パッドを有する第一の基板を複数のぬれ可能なパッドを
有する第二の基板に電気的に接続する方法であって： Ａ）第一の基板上のはんだパンプを次のステップにより
形成し： ａ）マスク・アパーチャがパッドと軸調整されるよう
に、基板上に複数のアパーチャを有するぬれ不可能な金
属のステンシル・マスクを付着させるステップ（４１
０、４１２、４１４）； ｂ）ビスマス−スズ−ｘ（ここで、ｘは実質的に銀とイ
ンジウムから成る群から選択される化合物であり、且つ
ｘは相互接続の溶融温度がビスマス−スズ共晶の溶融温
度より低くなるのに有効な量で存在）を含有するはんだ
ペーストを、はんだペーストがマスク・アパーチャを埋
めるように、金属マスクに適用するステップ（４１
６）； ｃ）はんだペーストをリフローしてパッド上にはんだバ
ンプを形成するステップ（４２２）；及び ｄ）はんだバンプの形成後、金属マスクを除去するステ
ップ（４２４）； Ｂ）そして、 ａ）この第一の基板上に形成されたはんだバンプを第二
の基板のぬれ可能なパッドと合致させて配置するステッ
プ；及び ｂ）はんだバンプをリフローして第一及び第二の基板間
で電気的相互接続を形成させるステップ； を含んで成る電気的接続方法に関し、次のような好まし
い実施態様を有する。The present invention also provides [5] a method of electrically connecting a first substrate having a plurality of wettable pads to a second substrate having a plurality of wettable pads: A) Form a solder bump on the first substrate by the following steps: a) Deposit a non-wettable metal stencil mask with multiple apertures on the substrate so that the mask aperture is aligned with the pad. Step (41)
0, 412, 414); b) bismuth-tin-x (where x is a compound selected from the group consisting essentially of silver and indium, and x is a bismuth-tin co-melting temperature). (41) present in an amount effective to lower the melting temperature of the crystal) to the metal mask so that the solder paste fills the mask aperture (41).
6); c) reflowing the solder paste to form solder bumps on the pad (422); and d) removing the metal mask after forming the solder bumps (424); B) and a) this. Arranging the solder bumps formed on the first substrate in alignment with the wettable pads of the second substrate; and b) reflowing the solder bumps to electrically interconnect the first and second substrates. Forming a connection; and having the following preferred embodiments.

【００３１】〔６〕バンプが１５０〜３５０ミクロンの
範囲のピッチを有する〔５〕記載の方法。[6] The method according to [5], wherein the bumps have a pitch in the range of 150 to 350 microns.

【００３２】そして、本発明は、〔７〕本質的に、重量
比で、 スズ：約４８％ 銀又はインジウム：０．５〜２．０％ ビスマス：残り（５０〜５１．５％） の構成成分から成る合金に関し、次のような好ましい実
施態様を有する。The present invention [7] essentially comprises, by weight, tin: about 48%, silver or indium: 0.5-2.0%, bismuth: balance (50-51.5%). With regard to the alloy composed of the components, the following preferred embodiments are provided.

【００３３】〔８〕延性がスズ−ビスマス共晶の延性の
２倍より大きい〔７〕記載の合金。[8] The alloy according to [7], which has a ductility greater than twice that of a tin-bismuth eutectic.

【００３４】[0034]

【発明の効果】本発明によれば、低硬度、高強度、低脆
性で、高疲労抵抗を有する、従って電子実装の使用中に
おける特性が良好な、はんだペースト用合金を提供する
ことができる。また、この合金を使用することにより、
本発明によれば、上記の優れた特性を有する電気的相互
接続組立体を提供することができる。According to the present invention, it is possible to provide a solder paste alloy which has low hardness, high strength, low brittleness, high fatigue resistance, and thus has excellent characteristics during use in electronic packaging. Also, by using this alloy,
According to the present invention, it is possible to provide an electrical interconnection assembly having the above-mentioned excellent characteristics.

【図面の簡単な説明】[Brief description of drawings]

【図１】銅板の間で２種類の合金（５８Ｂｉ−４２Ｓｎ
と５０Ｂｉ−４２Ｓｎ−２Ａｇ）から作ったはんだ接合
部についての３つの温度及び０．０１ｓｅｃｏｎｄ−１
のひずみ速度で実施されたせん断試験の結果を示すグラ
フである。FIG. 1 shows two kinds of alloys (58Bi-42Sn) between copper plates.
Temperature and 0.01 second −1 for a solder joint made from 50Bi-42Sn-2Ag) and
3 is a graph showing the results of shear tests carried out at different strain rates.

【図２】銅板の間で２種類の合金（５８Ｂｉ−４２Ｓｎ
と５０Ｂｉ−４８Ｓｎ−２Ａｇ）から作ったはんだ接合
部についての３つの温度及び０．００１ｓｅｃｏｎｄ
−１のひずみ速度で実施されたせん断試験の結果を示す
グラフである。FIG. 2 shows two kinds of alloys (58Bi-42Sn) between copper plates.
Temperature and 0.001 second for solder joints made from 50Bi-48Sn-2Ag) and 50Bi-48Sn-2Ag)
It is a graph which shows the result of the shear test implemented by the strain rate of -1 .

【図３】本発明における合金を利用するＣＰＤバンピン
グ法を説明する図である。FIG. 3 is a diagram illustrating a CPD bumping method using an alloy according to the present invention.

【図４】本発明における合金を利用するＣＰＤバンピン
グ法を説明する図である。FIG. 4 is a diagram illustrating a CPD bumping method using an alloy according to the present invention.

【図５】本発明における合金の応用例を表すバンプ形成
法のフローチャートである。FIG. 5 is a flowchart of a bump forming method showing an application example of an alloy in the present invention.

【図６】好ましい具体例におけるマスクと基板の組立法
を説明する図である。FIG. 6 is a diagram illustrating a method of assembling a mask and a substrate in a preferred specific example.

【図７】スズ−ビスマス−銀合金の実際の共晶遷移温度
及びその理論値を示す図表である。FIG. 7 is a chart showing the actual eutectic transition temperature of a tin-bismuth-silver alloy and its theoretical value.

【符号の説明】[Explanation of symbols]

３２０ 基板 ３２１ ぬれ可能（はんだ可能）な基板表面 ３２２ ぬれ可能（はんだ可能）領域 ３２４ ぬれ不可能領域 ３２６ マスク ３３０ マスクアパーチャ ３３４ はんだペーストと金属球 ３３８ はんだバンプ ３４２ 第一の基板 ３５０ 第二の基板 ３５４ 電気的相互接続組立体 320 substrate 321 wettable (solderable) substrate surface 322 wettable (solderable) region 324 non-wettable region 326 mask 330 mask aperture 334 solder paste and metal sphere 338 solder bump 342 first substrate 350 second substrate 354 Electrical interconnection assembly

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 それぞれの表面がぬれ可能な領域とぬれ
不可能な領域とに予め規定されている第一の基板（３４
２）及び第二の基板（３５０）を含んで成る電気的相互
接続組立体（３５４）であって： Ａ）第一の基板が、その表面のぬれ可能な領域上に、次
のステップにより、はんだバンプ（３３８）が形成さ
れ： ａ）マスク（３３０）の複数のアパーチャがぬれ可能な
領域（３２２）と軸調整されるように、ぬれ不可能な金
属マスク（３２６）を第一の基板の表面に配置するステ
ップ； ｂ）はんだペースト（３３４）がマスク・アパーチャを
埋めるように、スズ−ビスマス−銀から成るはんだペー
ストを金属マスクに適用するステップ； ｃ）はんだペーストをリフローしてぬれ可能な領域上に
はんだバンプを形成するステップ；及び ｄ）はんだバンプ（３３８）の形成後、金属マスク（３
２６）を除去するステップ； Ｂ）そして、この第一の基板（３４２）上に形成された
はんだバンプが、第二の基板（３５０）の表面上のぬれ
可能な領域と合致するよう、第一の基板の表面を第二の
基板の表面に実質的に平行に配置し且つ、加熱下で、リ
フローして第一及び第二の基板間で電気的接続を形成さ
せるステップ；によって製作されて成る電気的相互接続
組立体（３５４）。1. A first substrate (34), each surface of which is defined in advance in a wettable area and a non-wettable area.
An electrical interconnection assembly (354) comprising 2) and a second substrate (350): A) a first substrate on the wettable area of its surface, by the following steps: Solder bumps (338) are formed: a) A non-wettable metal mask (326) is applied to the first substrate so that the apertures of the mask (330) are aligned with the wettable areas (322). B) applying a tin-bismuth-silver solder paste to the metal mask so that the solder paste (334) fills the mask aperture; c) reflowing the solder paste to make it wettable Forming solder bumps on the regions; and d) after forming solder bumps (338), a metal mask (3
26) removing B) and so that the solder bumps formed on the first substrate (342) match the wettable areas on the surface of the second substrate (350). Arranging the surface of the substrate substantially parallel to the surface of the second substrate and reflowing under heat to form an electrical connection between the first and second substrates. Electrical interconnection assembly (354). 【請求項２】 複数のぬれ可能なパッドを有する基板上
に三元共晶のはんだバンプを直接形成する方法であっ
て： ａ）マスクの複数のアパーチャがパッドと軸調整される
ように、ぬれ不可能な金属マスクを基板上に配置するス
テップ（４１０、４１２、４１４）； ｂ）はんだペーストがマスク・アパーチャを埋めるよう
に、それぞれ５０：４８：２と５１．５：４８：０．５
の間の重量比のビスマス−スズ−銀又はビスマス−スズ
−インジウムの群から選択されるはんだペーストを金属
マスクに適用するステップ（４１６）； ｃ）はんだペーストをリフローしてパッド上にはんだバ
ンプを形成するステップ（４２２）；及び ｄ）はんだバンプの形成後、金属マスクを除去するステ
ップ（４２４）；を含んで成るはんだバンプ形成方法。2. A method of directly forming ternary eutectic solder bumps on a substrate having a plurality of wettable pads, comprising: a) wetting such that the plurality of apertures in the mask are aligned with the pads. Placing an impossible metal mask on the substrate (410, 412, 414); b) 50: 48: 2 and 51.5: 48: 0.5, respectively, so that the solder paste fills the mask aperture.
Applying a solder paste selected from the group of bismuth-tin-silver or bismuth-tin-indium in a weight ratio between 416 to the metal mask; c) reflowing the solder paste to form solder bumps on the pad. Forming (422); and d) removing the metal mask after forming the solder bumps (424); 【請求項３】 表面がぬれ可能な領域とぬれ不可能な領
域とに予め規定されている第一の基板（３４２）及び第
二の基板（３５０）を含んで成る電気的相互接続組立体
（３５４）であって： Ａ）第一の基板が、その表面のぬれ可能な領域（３２
２）上に、次のステップにより、はんだバンプ（３３
８）が形成され： ａ）マスク（３２６）の複数のアパーチャ（３３０）が
ぬれ可能な領域（３２２）と軸調整されるように、ぬれ
不可能な金属マスク（３２６）を第一の基板の表面に配
置するステップ； ｂ）ビスマス−スズ−ｘ（ここで、ｘは実質的に銀とイ
ンジウムから成る群から選択される化合物であり、且つ
ｘは相互接続の溶融温度がビスマス−スズ共晶の溶融温
度より低くなるのに有効な量で存在）を含有するはんだ
ペースト（３３４）を、はんだペーストがマスク・アパ
ーチャを埋めるように、金属マスクに適用するステッ
プ； ｃ）はんだペーストをリフローしてぬれ可能な領域上に
はんだバンプ（３３８）を形成するステップ；及び ｄ）はんだバンプの形成後、金属マスク（３３６）を除
去するステップ； Ｂ）そして、この第一の基板上のはんだバンプが第二の
基板（３５２）上のぬれ可能な領域と合致するよう、第
一の基板の表面を第二の基板の表面に実質的に平行に配
置し且つ、加熱下で、リフローして第一及び第二の基板
間で電気的接続を形成させるステップ；によって作製さ
れて成る電気的相互接続組立体（３５４）。3. An electrical interconnection assembly (1) comprising a first substrate (342) and a second substrate (350) whose surfaces are pre-defined in wettable and non-wettable areas. 354): A) The first substrate has a wettable region (32) on its surface.
2) the solder bumps (33
8) is formed: a) A non-wettable metal mask (326) is deposited on the first substrate so that the apertures (330) of the mask (326) are aligned with the wettable area (322). B) bismuth-tin-x, where x is a compound selected from the group consisting essentially of silver and indium, and x is a bismuth-tin eutectic with a melting temperature of the interconnect. A solder paste (334), which is present in an amount effective to be below the melting temperature of,) to the metal mask so that the solder paste fills the mask aperture; c) reflowing the solder paste. Forming solder bumps (338) on the wettable area; and d) removing the metal mask (336) after forming the solder bumps; B) and this Arranging the surface of the first substrate substantially parallel to the surface of the second substrate and heating so that the solder bumps on the one substrate match the wettable areas on the second substrate (352). An electrical interconnection assembly (354) made by reflowing to form an electrical connection between the first and second substrates, below. 【請求項４】 複数のぬれ可能なパッドを有する第一の
基板を複数のぬれ可能なパッドを有する第二の基板に電
気的に接続する方法であって： Ａ）第一の基板上のはんだパンプを次のステップにより
形成し： ａ）マスク・アパーチャがパッドと軸調整されるよう
に、基板上に複数のアパーチャを有するぬれ不可能な金
属のステンシル・マスクを付着させるステップ（４１
０、４１２、４１４）； ｂ）ビスマス−スズ−ｘ（ここで、ｘは実質的に銀とイ
ンジウムから成る群から選択される化合物であり、且つ
ｘは相互接続の溶融温度がビスマス−スズ共晶の溶融温
度より低くなるのに有効な量で存在）を含有するはんだ
ペーストを、はんだペーストがマスク・アパーチャを埋
めるように、金属マスクに適用するステップ（４１
６）； ｃ）はんだペーストをリフローしてパッド上にはんだバ
ンプを形成するステップ（４２２）；及び ｄ）はんだバンプの形成後、金属マスクを除去するステ
ップ（４２４）； Ｂ）そして、 ａ）この第一の基板上に形成されたはんだバンプを第二
の基板のぬれ可能なパッドと合致させて配置するステッ
プ；及び ｂ）はんだバンプをリフローして第一及び第二の基板間
で電気的相互接続を形成させるステップ；を含んで成る
電気的接続方法。4. A method of electrically connecting a first substrate having a plurality of wettable pads to a second substrate having a plurality of wettable pads: A) Solder on the first substrate. A pump is formed by the following steps: a) depositing a non-wettable metal stencil mask with multiple apertures on the substrate so that the mask apertures are aligned with the pads (41).
0, 412, 414); b) bismuth-tin-x (where x is a compound selected from the group consisting essentially of silver and indium, and x is a bismuth-tin co-melting temperature). (41) present in an amount effective to lower the melting temperature of the crystal) to the metal mask so that the solder paste fills the mask aperture (41).
6); c) reflowing the solder paste to form solder bumps on the pad (422); and d) removing the metal mask after forming the solder bumps (424); B) and a) this. Arranging the solder bumps formed on the first substrate in alignment with the wettable pads of the second substrate; and b) reflowing the solder bumps to electrically interconnect the first and second substrates. Forming an electrical connection; 【請求項５】 本質的に、重量比で、 スズ：約４８％ 銀又はインジウム：０．５〜２．０％ ビスマス：残り（５０〜５１．５％） の構成成分から成る合金。5. An alloy consisting essentially of by weight: tin: about 48% silver or indium: 0.5-2.0% bismuth: balance (50-51.5%).
JP8034444A 1995-01-31 1996-01-29 Electric interconnection assembly,solder bump forming method,electrical connecting method and alloy Pending JPH08264916A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38138195A 1995-01-31 1995-01-31
US381381 1995-01-31

Publications (1)

Publication Number Publication Date
JPH08264916A true JPH08264916A (en) 1996-10-11

Family

ID=23504818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8034444A Pending JPH08264916A (en) 1995-01-31 1996-01-29 Electric interconnection assembly,solder bump forming method,electrical connecting method and alloy

Country Status (3)

Country Link
JP (1) JPH08264916A (en)
DE (1) DE19542043A1 (en)
GB (1) GB2297507A (en)

Cited By (1)

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KR100716434B1 (en) * 2006-04-17 2007-05-10 주식회사 파이컴 Method of bonding probes and method of manufacturing a probe card

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US5755896A (en) * 1996-11-26 1998-05-26 Ford Motor Company Low temperature lead-free solder compositions
US5833921A (en) * 1997-09-26 1998-11-10 Ford Motor Company Lead-free, low-temperature solder compositions
DE10103390B4 (en) * 2001-01-26 2005-09-22 Robert Bosch Gmbh Method and system for producing a substantially annular solder joint
DE10117404A1 (en) * 2001-04-06 2002-10-17 Paff Stannol Loetmittel Wave soldering process used in the production of printed circuit boards comprises using a lead-free solder having a lower melting point than a usual tin-lead solder, and a fluxing agent having no-clean properties
US7745321B2 (en) 2008-01-11 2010-06-29 Qimonda Ag Solder contacts and methods of forming same
US7973417B2 (en) 2008-04-18 2011-07-05 Qimonda Ag Integrated circuit and method of fabricating the same
DE102008031836A1 (en) * 2008-07-05 2010-01-21 Deutsche Cell Gmbh solder contact
CN112490137A (en) * 2020-11-30 2021-03-12 安徽光智科技有限公司 Preparation method of focal plane flip interconnection indium column

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GB2257386B (en) * 1991-06-24 1995-07-05 Tani Denki Kogyo Kk Screen printing apparatus
US5389160A (en) * 1993-06-01 1995-02-14 Motorola, Inc. Tin bismuth solder paste, and method using paste to form connection having improved high temperature properties

Cited By (3)

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Publication number Priority date Publication date Assignee Title
KR100716434B1 (en) * 2006-04-17 2007-05-10 주식회사 파이컴 Method of bonding probes and method of manufacturing a probe card
WO2007119930A1 (en) * 2006-04-17 2007-10-25 Phicom Corporation Method of bonding probes and method of manufacturing a probe card using the same
US7886957B2 (en) 2006-04-17 2011-02-15 Phicom Corporation Method of bonding probes and method of manufacturing a probe card using the same

Also Published As

Publication number Publication date
GB9601257D0 (en) 1996-03-27
GB2297507A (en) 1996-08-07
DE19542043A1 (en) 1996-08-01

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