JPH08264773A - Manufacture of mos integrated circuit - Google Patents

Abstract

PURPOSE: To prevent gate insulating film breakdown due to charge-up at the time of ion implantation for forming a source-drain region, by arranging direct contact electrodes at intervals narrower than or equal to the ion beam diameter of ion implantation. CONSTITUTION: A silicon thermal oxide film as a field insulating film 2 for element isolation is formed on a semiconductor substrate 1. An element forming region 3 and direct contact regions 4 are defined. In the regions 3, 4, a silicon oxide film as a gate insulating film is formed. The gate insulating film 5 except the element forming region 3 is eliminated, and a silicon substrate 1 is exposed. On the whole part, poly silicon is formed as a gate electrode film 6 turning to a gate electrode. A gate electrode 7 is formed by etching the gate electrode film 6. Direct contact electrodes 8 are formed in the direct contact regions 4, to be isolated from the gate electrode. In this state, ions are implanted, and a source region and a drain region are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOS integrated circuit.

[0002]

2. Description of the Related Art Conventionally, an ion implantation process for forming a source region and a drain region of a MOS integrated circuit has been performed with a gate electrode and a semiconductor substrate insulated from each other through a gate insulating film. However, as the gate insulating film becomes thinner along with the miniaturization of elements, this method has a problem that the gate insulating film is deteriorated or destroyed due to charge-up at the time of ion implantation, and the manufacturing yield of the MOS integrated circuit is reduced. Has occurred. Charge-up at the time of ion implantation occurs because the gate electrode is in an electrically floating state.

Therefore, a new manufacturing method has been devised to prevent the charge-up of the gate electrode (Japanese Patent Laid-Open No. Hei 4).
No. 168728).

FIG. 4 is a sectional view of a semiconductor device showing the conventional method of manufacturing a MOS integrated circuit in the order of steps. First, a field insulating film 2, which is a thermal oxide film of silicon for element isolation, is selectively formed on a semiconductor substrate 1 of silicon to partition an element forming region 3 and a direct contact region 4 (FIG. 4A). A gate insulating film 5 of a silicon oxide film is formed in the element forming region 3 and the direct contact region 4 where the MOS transistor is formed (FIG. 4B). The gate insulating film 5 other than the element forming region 3 is removed by a photolithography process to expose the silicon substrate (FIG. 4C). A silicon gate electrode film 6 to be a gate electrode is formed on the entire surface (FIG. 4D). The gate electrode film 6 is etched by a photolithography process to form a gate electrode 7 (FIG. 4E). However, at this point, the gate electrode 7 is connected to the semiconductor substrate 1 through the direct contact region 4. In this state, ion implantation is performed to form a source region and a drain region in the element formation region 3 (FIG. 4 (f)). However, the source region and the drain region are portions which are perpendicular to the paper surface and are not shown. A part of the gate electrode 7 is etched by a photolithography process to disconnect the gate electrode 7 from the semiconductor substrate 1 (FIG. 4G).

In this method, ion implantation is performed in a structure in which the gate electrode 7 is connected to the semiconductor substrate 1 through the direct contact region 4 (FIG. 4 (e)). By doing so, the positive charges incident on the gate electrode 7 flow to the semiconductor substrate 1, so that the semiconductor substrate 1 and the gate electrode 7
Have almost the same potential, and the gate insulating film 5 is not destroyed.

[0006]

However, in the above method, it is necessary to arrange the direct contact region in accordance with the arrangement of the gate electrode, which has a problem that it becomes a great obstacle to integration. Even if the direct contact region is arranged on the scribe region, the wiring length between the direct contact region and the gate electrode becomes long, which causes a problem of hindering integration. Arranging the direct contact region also causes a problem that the integrated circuit design becomes complicated. Further, from the viewpoint of the manufacturing process, a photolithography process for disconnecting the connection between the gate electrode and the direct contact region is required, which causes a problem of increasing the number of processes.

The present invention has been made to solve the above problems, and does not hinder integration, does not complicate circuit design, and does not increase the number of steps. An object of the present invention is to provide a method for manufacturing a MOS integrated circuit, which prevents a gate insulating film from being destroyed by charge-up that occurs during ion implantation for forming source and drain regions.

[0008]

The present inventor has found that even if the gate electrode is not in direct contact with the semiconductor substrate, the gate electrode is directly contacted with the gate electrode (and hence the semiconductor substrate) via the ion beam (plasma) during ion implantation. The present invention has been completed, focusing on the fact that it can be electrically contacted with.

That is, in order to achieve the above object, the method of manufacturing a MOS integrated circuit according to the present invention is characterized by including the following steps, as shown in FIG.

A step of selectively forming a field insulating film 2 on a semiconductor substrate 1 to partition an element forming region 3 and a direct contact region 4 (FIG. 1A). At this time,
The distance between the direct contact regions 4 is set to be equal to or smaller than the ion beam diameter of the ion implantation used in the subsequent step of forming the source region and the drain region.

A gate insulating film 5 is formed on the device forming region 3.
Forming step (FIGS. 1B and 1C).

A direct contact electrode 8 which contacts the semiconductor substrate 1 in the direct contact region 4.
And forming a gate electrode 7 insulated from the semiconductor substrate 1 and the gate insulating film 5 in the element formation region 3 (FIGS. 1D and 1E).

Ion implantation is performed to form a source region and a drain region in the element forming region 3 (FIG. 1).
(F)).

[0014]

The ion implantation is performed by irradiating an ion beam having a predetermined ion beam diameter while scanning the wafer.

FIG. 2 shows the distance L between the direct contact electrodes.
2 is a schematic cross-sectional view of the semiconductor device at the time of ion implantation when is smaller than the ion beam diameter D. FIG. (A) is a figure at a certain time point, (b) is a figure after a predetermined time, and shows the situation where the ion beam scans. Naturally, one direct contact electrode is included in the range of the ion beam. That is, the direct contact electrode 81 is included in the situation of (a), and the direct contact electrode 82 is included in the situation of (b).

In this case, for example, in the situation of (a), the gate electrodes 71 and 72 and the direct contact electrode 81 (thus the semiconductor substrate 1) via the ion beam 10.
Are electrically connected. Therefore, the gate electrodes 71, 7
2 and the difference between the potential of the direct contact electrode 81 and the potential of the semiconductor substrate 1 becomes small, and the gate insulating film 5
The voltage applied to 1, 52 is small. Therefore, the gate insulating film is not destroyed due to charge-up of the gate electrode during ion implantation.

In the situation of (b), similarly, the gate electrodes 71 and 72 and the direct contact electrode 82 (and therefore the semiconductor substrate 1) are electrically connected via the ion beam 10. That is, the difference between the potentials of the gate electrodes 71 and 72, the potential of the direct contact electrode 82, and the potential of the semiconductor substrate 1 becomes small, and the gate insulating films 51 and 52.
The voltage applied to the gate becomes small and the gate insulating film is not destroyed.

FIG. 3 shows the distance L between direct contact electrodes.
2 is a schematic cross-sectional view of the semiconductor device at the time of ion implantation when is larger than the ion beam diameter D. FIG. (A) is a diagram at a certain time point, (b) is a diagram after a predetermined time, and shows a situation where the ion beam scans similarly to FIG. 2. In the situation of (a), the direct contact electrode is included in the range of the ion beam, but in the situation of (b), the direct contact electrode is not included in the range of the ion beam.

In this case, in the situation of FIG.
Similar to (a) and (b), the voltage applied to the gate insulating films 51 and 52 by electrically connecting the gate electrodes 71 and 72 and the direct contact electrode 81 (hence the semiconductor substrate 1) via the ion beam 10. Is small, and the gate insulating film is not destroyed.

However, in the case of (b), since the direct contact electrode is not included in the range of the ion beam, the positive charge incident on the gate electrodes 71, 72, 73 is the gate electrodes 71, 72, 73. Will be accumulated in and cause charge-up. Therefore, this gate electrode 7
A potential difference is generated between 1, 72, 73 and the semiconductor substrate 1,
The gate insulating films 51, 52, 53 may be destroyed.

That is, by providing the direct contact electrodes at intervals less than or equal to the ion beam diameter of the ion implantation, even if the gate electrode does not directly contact the semiconductor substrate,
The gate electrode and the direct contact electrode (and therefore the semiconductor substrate) can be reliably electrically connected via the ion beam (plasma), and the gate insulating film can be prevented from being destroyed by charge-up of the gate electrode during ion implantation. it can.

By doing so, it is not necessary to connect and arrange the direct contact electrode and the gate electrode, so that the direct contact electrode can be formed at an arbitrary position, and can also be formed at an arbitrary position on the scribe region. It will be fine. Therefore, it is unnecessary to dispose the direct contact electrode (region) in accordance with the gate electrode, and the provision of the direct contact electrode (region) does not hinder integration and does not complicate the design.

With this structure, the gate electrode and the direct contact electrode can be cut at the same time in the step of forming the gate electrode. Therefore, the gate electrode and the direct contact electrode which are in the conventional method using the direct contact can be cut. It is possible to eliminate the step (FIG. 4 (g)).

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a MOS integrated circuit according to the present invention will be described below with reference to the drawings. In this example, an antenna MOS structure having a gate electrode area of 2000 μm × 2000 μm and an active region area of 2.5 μm × 2.5 μm was manufactured and evaluated in order to further clarify the charge-up suppressing effect. The active region is a region where the gate electrode and the semiconductor substrate are opposed to each other with the gate insulating film interposed therebetween. In addition, the direct contact electrode has an electrode area of 10 μm.
The contact area was 8 μm × 8 μm. The contact region mentioned here is a region where the direct contact electrode and the semiconductor substrate are in direct contact with each other.

FIG. 1 is a sectional view of a semiconductor device showing an embodiment of a method of manufacturing a MOS integrated circuit according to the present invention in the order of steps.
First, a silicon thermal oxide film having a thickness of 60 is formed as a field insulating film 2 for element isolation on a silicon substrate which is a semiconductor substrate 1.
The element formation region 3 and the direct contact region 4 were defined by 0 nm selective formation (FIG. 1A). In addition,
In this embodiment, the direct contact region 4 is set to 3
It was arranged at an interval of cm. A silicon oxide film having a thickness of 10 nm was formed as the gate insulating film 5 in the element forming region 3 and the direct contact region 4 (FIG. 1B). The gate insulating film 5 other than the element forming region 3 was removed by a photolithography process to expose the silicon substrate (FIG. 1C). A 400 nm-thickness of polysilicon is formed on the entire surface as a gate electrode film 6 to be a gate electrode (FIG.
(D)). The gate electrode film 6 was etched by a photolithography process to form a gate electrode 7 (see FIG. 1).
(E)). At this time, the direct contact electrode 8 was formed in the direct contact region 4 by cutting it from the gate electrode 7. Therefore, the connection between the gate electrode 7 and the semiconductor substrate 1 is cut off. In this state, ion implantation was performed to form a source region and a drain region in the element formation region 3 (FIG. 1 (f)). As for the ion implantation, 80 As ions are used.
keV, 5 × 10 ¹⁵ cm ⁻² , and ion beam diameter 5 cm.

With respect to the MOS structure thus manufactured, the breakdown voltage characteristics of the gate insulating film were measured. As a result, the gate insulating film was not broken in this example.

On the other hand, when the direct contact regions 4 were arranged at an interval of 6 cm and the same ion implantation was performed, about 80% of the gate insulating films were broken.

[0028]

As described above, according to the method for manufacturing a MOS integrated circuit of the present invention, it is possible to prevent the gate insulating film from being destroyed due to the charge-up that occurs during the ion implantation for forming the source region and the drain region, and to integrate it. The MOS integrated circuit can be manufactured without any of the problems described above, without complicating the circuit design, and without increasing the number of steps.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of a method of manufacturing a MOS integrated circuit according to the present invention in the order of steps.

FIG. 2 is a schematic cross-sectional view of a semiconductor device during ion implantation when the distance L between direct contact electrodes is smaller than the ion beam diameter D.

FIG. 3 is a schematic cross-sectional view of a semiconductor device during ion implantation when the distance L between direct contact electrodes is larger than the ion beam diameter D.

FIG. 4 is a cross-sectional view of a semiconductor device showing a method of manufacturing a conventional MOS integrated circuit in process order.

[Explanation of symbols]

 1 semiconductor substrate 2 field insulating film 3 element forming region 4 direct contact region 5 gate insulating film 6 gate electrode film 7 gate electrode 8 direct contact electrode 10 ion beam 71 gate electrode 72 gate electrode 73 gate electrode 81 direct contact electrode 82 direct contact electrode

Claims (1)

[Claims] 1. An ion implantation used in a step of selectively forming a field insulating film on a semiconductor substrate to partition an element formation region and a direct contact region, and forming the direct contact region later in a source region and a drain region. Of the ion beam diameter or less, a step of forming a gate insulating film on the element forming region, a direct contact electrode in contact with the semiconductor substrate in the direct contact region, and a semiconductor in the element forming region. A method of manufacturing a MOS integrated circuit, comprising: a step of forming a gate electrode insulated from a substrate by a gate insulating film; and a step of performing ion implantation to form a source region and a drain region in the element forming region.