JPH08264726A - Semiconductor memory and semiconductor logic circuit - Google Patents

Abstract

PURPOSE: To obtain a semiconductor memory for reading/writing information by means of optical signals or electric signals through a simple constitution while simplifying the fabrication process by controlling the bistable state, estab lished by each semiconductor constituting a pn junction and a load, through irradiation of light having energy higher than the band gap of semiconductor constituting a pn junction. CONSTITUTION: Collector contact layers 2, 3, a base layer 4, first and second emitter layers 51 , 52 , first and second emitter contact layers 61 , 62 , and first and second emitter layers 71 , 72 are formed on an Inp semiinsulating substrate 1. In the voltage current characteristics, a bistable state having stabilization points S1 , S2 on the low and high voltage sides appears upon application of a constant voltage of about 1V between the emitters 71 , 72 . When the base layer 4 is irradiated with light having energy higher than the energy gap of semiconductor material, forward current of the tunnel diode decreases as a whole and the stabilization points are shifted equally to the high voltage side thus bringing about a state where only the stabilization point S1 on the high voltage side is present.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a semiconductor logic circuit device.

[0002]

2. Description of the Related Art In recent years, with the rapid progress and diversification of information processing technology or telecommunications technology, an optical semiconductor device which responds to an optical signal or outputs an optical signal and an electrical semiconductor which responds to an electrical signal There is a strong demand to develop a device that makes use of the characteristics of each semiconductor device that outputs a signal.

As a feature of the optical semiconductor device, speeding up of signal processing and parallel processing of signals are easier than that of a semiconductor device which responds to or outputs an electric signal. However, despite various proposals of information storage devices using optical semiconductor devices, none have been put into practical use at present.

One of the reasons why the information storage device using the optical semiconductor device is not put into practical use is that even if the information storage device can be constructed by the optical semiconductor device, peripheral logic circuits and switching circuits must be constructed by the semiconductor device. It is considered that under the present circumstances, it is impossible to improve the characteristics of the entire device in which the optical semiconductor device and the semiconductor device are combined.

[0005]

Therefore, it is important to develop an optical semiconductor device and a device capable of utilizing the respective characteristics of the semiconductor device. According to the present invention, a bistable state formed by a circuit composed of a load and a semiconductor element having a negative resistance characteristic including a pn junction, a pnp junction, or an npn junction having an impurity concentration higher than the effective state density and a negative resistance characteristic By irradiating weak light and strong light having energy higher than the band gap of the semiconductor constituting the semiconductor element having, or applying voltage to the semiconductor element having this negative resistance characteristic, or irradiating light to the load. An object of the present invention is to provide a semiconductor memory device or a semiconductor logic circuit device by controlling the high voltage side stable point and the low voltage side stable point to be turned on (1) or turned off (10).

[0006]

In a semiconductor memory device according to the present invention, a tunnel diode having a negative resistance characteristic in which an impurity concentration of each semiconductor forming a pn junction is equal to or higher than an effective state density, a tunnel diode, and an ohmic diode. A bistable state formed by a circuit using a resistive element, a Schottky diode, a constant current source, etc. as a load, and irradiating the pn junction with light having energy higher than the band gap of the semiconductor forming the pn junction. The configuration that controls by this is adopted.

Further, in another semiconductor memory device according to the present invention, a semiconductor element having a negative resistance characteristic in which the impurity concentration of each semiconductor of the pnp junction or the npn junction is equal to or higher than the effective state density, a tunnel diode, and an ohmic property. Irradiating the semiconductor element with a bistable state formed by a circuit having a load such as a resistance element, a Schottky diode, or a constant current source, with light having an energy larger than the band gap of the semiconductor forming the semiconductor element. The configuration controlled by is adopted.

Further, in another semiconductor memory device according to the present invention, a tunnel diode having an impurity concentration of each semiconductor forming a pn junction is equal to or higher than an effective state density and having a negative resistance characteristic, and an npn type or a pnp type. A structure in which a bistable state formed by a circuit using a bipolar transistor as a load is controlled by irradiating the pn junction with light having energy higher than the band gap of the semiconductor forming the pn junction is adopted.

Further, in another semiconductor memory device according to the present invention, a semiconductor element having a negative resistance characteristic in which the impurity concentration of each semiconductor of the pnp junction or the npn junction is equal to or higher than the effective state density, and the npn junction or the pnp junction. A structure in which a bistable state formed by a circuit having a bipolar transistor having a load is controlled by irradiating the semiconductor element with light having energy higher than the band gap of the semiconductor forming the semiconductor element is adopted. .

In another semiconductor memory device according to the present invention, a tunnel diode having an impurity concentration of each semiconductor forming a pn junction is equal to or higher than an effective state density and having a negative resistance characteristic, and an npn junction or a pnp junction. A configuration is adopted in which the bistable state formed by the circuit having the bipolar transistor as a load is controlled by irradiating the bipolar transistor with light having energy higher than the band gap of the semiconductor forming the bipolar transistor.

Further, in another semiconductor memory device according to the present invention, a semiconductor element having a negative resistance characteristic in which the impurity concentration of each semiconductor of the pnp junction or the npn junction is equal to or higher than the effective state density, and the npn junction or the pnp junction. A bistable state formed by a circuit having a bipolar transistor as a load,
A structure is adopted in which the bipolar transistor is controlled by irradiating it with light having energy higher than the band gap of the semiconductor.

In these cases, it is possible to change the stored information by moving the stable point in the bistable state according to the irradiation intensity of light.

Further, in this case, there are provided two or more emitter layers of the first conductivity type, a common base layer of the second conductivity type, and a common collector layer of the first conductivity type, and the emitter layer and the base. A multi-emitter heterojunction bipolar transistor in which the impurity concentration of the layer is equal to or higher than the effective state density can be used.

In this case, the peak current and the valley current of the pnp or npn junction when the weak light having energy higher than the bandgap of the semiconductor forming the junction and when the strong light is irradiated are detected. The stored information can be rewritten by the change, and the stored information can be read depending on the presence or absence of a collector current when a positive voltage is applied to the collector electrode.

In this case, the tunnel diode having the np junction and the p-type layer or the n-type layer of the bipolar transistor having the npn junction or the pnp matching, which is the load, can be shared.

In these cases, it is possible to rewrite the stored information by irradiating the common p-type layer or n-type layer with light.

Further, in this case, a base same conductivity type layer having a high impurity concentration of the same conductivity type as the base layer is formed on the emitter layer of the multi-emitter heterojunction bipolar transistor, and the base same conductivity type layer is formed. The emitter electrode may be formed on the top.

Further, in this case, by irradiating two or more emitter layers with light independently, it is possible to write random information.

Further, in this case, in the multi-emitter heterojunction bipolar transistor, a base same conductivity type layer having a high impurity concentration of the same conductivity type as the base layer is formed on one emitter layer, and the other emitter layer is formed. The base may have the same conductivity type layer not formed on the layer.

Further, in these cases, whether a positive bias voltage is applied between the collector layer and the emitter layer, or the base layer is irradiated with light having an energy larger than the band gap of the semiconductor forming the base layer. Alternatively, the stored information can be read by applying the bias voltage and light at the same time.

It is also possible to arrange a plurality of semiconductor memory devices having the above-mentioned configuration in an array and write and read information by an optical signal.

Further, in the semiconductor logic circuit device according to the present invention, a base same conductivity type layer having the same conductivity type as the base layer and having a high impurity concentration is formed on one emitter layer, and the other emitter layer is formed. A multi-emitter heterojunction bipolar transistor having no base same conductivity type layer is used above, one emitter electrode is grounded, and a positive voltage is applied to the other emitter electrode to form a bistable state.
A positive power source is connected to the collector electrode through a load resistor, and an output terminal is connected to a connection point between the collector and the load resistor.
The stable state is controlled by irradiating the emitter layer, to which the emitter electrode is connected, with light having an energy larger than the band gap of the semiconductor forming the emitter layer, and the stable state is read by the voltage generated at the output terminal. Adopted the configuration to do.

In another semiconductor memory device according to the present invention, a semiconductor element having a negative resistance characteristic in which the impurity concentration of each semiconductor of the pnp junction or the npn junction is equal to or higher than the effective state density, a tunnel diode, and an ohmic property. Resistance element, Schottky diode, npn junction or pn
Irradiating a bistable state formed by a circuit having a p-junction bipolar transistor, a constant current source, or the like as a load, to the semiconductor element with light having energy higher than the band gap of the semiconductor forming the semiconductor element. A semiconductor memory device controlled by the array is arranged in an array, and a semiconductor device having the negative resistance characteristic or a band gap forming a bipolar transistor which is a load is provided in each semiconductor memory device in each direction of the X axis and the Y axis. We adopted a configuration to control the bistable state by irradiating an optical signal with the energy of.

Further, in another semiconductor memory device according to the present invention, a semiconductor element having a negative resistance characteristic in which the impurity concentration of each semiconductor of the pnp junction or the npn junction is equal to or higher than the effective state density, and a tunnel diode, When a bistable state formed by a circuit using an ohmic resistance element, a Schottky diode, a bipolar transistor having an npn junction or a pnp junction, or a constant current source as a load is applied to the semiconductor element, Arrange semiconductor memory devices to be controlled by irradiating light having energy above the band gap in an array,
Each semiconductor memory device is irradiated with an optical signal having energy higher than a bandgap forming a semiconductor element having the negative resistance characteristic or a bipolar transistor which is a load in the X-axis direction, and an electric signal is applied in the Y-axis direction. The bistable state can be controlled accordingly.

[0025]

In the semiconductor memory device and the semiconductor logic circuit device of the present invention, basically, a pn junction (tunnel diode, Esaki diode) whose impurity concentration is equal to or higher than the effective state density, or a pnp junction or npn whose impurity concentration is equal to or higher than the effective state density. A circuit consisting of a junction and a load is used. here,
The voltage-current characteristics of the tunnel diode will be reviewed.

FIGS. 1 and 2 are explanatory diagrams of the voltage-current characteristic of the tunnel diode, where (A) to (E) show the energy band and (G) shows the voltage-current characteristic. The flow of electrons and holes when the bias voltage of the pn junction in which the impurity concentrations of the p-type region and the n-type region are equal to or higher than the effective state density is changed will be described below.

Zero-bias state (see FIG. 1A) In the state where no bias voltage is applied, the Fermi levels of the p-type region and the n-type region match, and in this state, electrons and holes passing through the junction surface Since the numbers are statistically balanced, the current becomes 0 as a whole, and no current flows in the external circuit.

A state in which a low forward voltage is applied (see FIG. 1B) When a low positive voltage is applied to the p-type region and a low negative voltage is applied to the n-type region, the energy level of the n-type region Is higher than the energy level of the p-type region, and the electrons in the conduction band of the n-type region move to the empty valence band of the p-type region. Flow towards the mold area. This tunnel current increases with voltage until the forward voltage reaches a certain value.

A state in which a fairly high forward voltage is applied (see FIG. 1C) When a fairly high positive voltage is applied to the p-type region and a considerably high negative voltage is applied to the n-type region, the n-type region Conduction band is p
It faces the forbidden band of the type region, and in this state, electrons cannot move from the n-type region to the p-type region by the tunnel. Therefore, the tunnel current gradually decreases after reaching a certain maximum value.

A state in which a remarkably high forward voltage is applied (see FIG. 2D) When a remarkably high positive voltage is applied to the p-type region and a remarkably high negative voltage is applied to the n-type region, the p-type region Since the potential difference of the barrier between the n-type region and the n-type region becomes low, the electrons excited in the n-type region move to the conduction band of the p-type region with few electrons,
Further, in the valence band of the n-type region in which holes generated in the valence band of the p-type region have few holes, a diffusion phenomenon of majority carriers moving over the potential barrier occurs and a large forward current flows.

A state in which a reverse bias is applied (see FIG. 2E) When a voltage that makes the p-type region negative and the n-type region positive is applied to the pn junction, the valence band of the p-type region is changed. Full level is n
Since it faces the empty conduction band of the type region, a large tunnel current (zener current) flows from the p-type region to the n-type region. This Zener current increases rapidly with the voltage.

FIG. 2 (F) shows the voltage-current characteristics of the tunnel diode which change through the above-mentioned bias states. In this figure, the solid line a shows the voltage-current characteristic without light irradiation, and the broken line b shows the voltage-current characteristic with light irradiation. Thus, in the pn junction, when the impurity concentration of both is equal to or higher than the effective state density,
When a positive bias voltage is applied to the p-side and gradually rises, electrons in the conduction band on the n-side first tunnel through the depletion layer and tunnel to the valence band on the p-side (Esaki tunnel). In order to do so, a current flows, then the current decreases and the current increases, which is a so-called negative resistance characteristic.

When the pn junction is irradiated with light having an energy larger than the band gap of the semiconductor forming the pn junction, an electron-hole pair is formed, the electron moves to the n-type layer, and the hole is p. Since it is accumulated in the mold layer, the current at the same applied voltage decreases as compared with the case where no light is irradiated. That is, the current when light is applied is a value obtained by subtracting the photocurrent carried by electrons and holes formed by light irradiation from the current when light is not applied. Note that ,,,, in this figure are respectively FIG. 1 (A), (B), (C), FIG. 2 (D), (E).
Shows the state of.

FIGS. 3 and 4 are voltage-current characteristic diagrams of the tunnel diode when the load is changed, and are (A) to (E).
Indicates the voltage-current characteristics of each load. The load is a reverse tunnel diode, a resistor, a Schottky diode, a FET, and a forward tunnel diode, each of which has a low voltage side stable point S ₁ and a high voltage side stable point S ₂ as described below. ing.

When the load is a reverse tunnel diode (see FIG. 2A) When the load is a resistor (see FIG. 2B) When the load is a Schottky diode (FIG. 2)
(See (C)) When the load is an FET (see FIG. 3D) When the load is a forward tunnel diode (see FIG. 3E)

FIG. 5 is a voltage-current characteristic diagram when the applied voltage of the tunnel diode is changed. (A) shows the voltage-current characteristic when the applied voltage is low, and (B) shows the voltage-current characteristic when the applied voltage is high. There is. This example shows the voltage-current characteristics when the load is a tunnel diode in the reverse direction and the applied voltage is changed. When the applied voltage is low, there is a low-voltage side stable point S _1, but there is a high point. There is no voltage side stable point S ₂ , and when the applied voltage is high, there is a high voltage side stable point S ₂ but no low voltage side stable point S ₁ .

As described above, a tunnel diode having a negative resistance characteristic, a forward or backward tunnel diode connected in series, an ohmic resistance element, a Schottky diode, a constant current source for a channel layer of an FET, etc. A bistable state is formed in the voltage-current characteristic of the circuit with the load as. In this bistable state, the stable point can be moved between the low voltage side (low voltage side stable point S ₁ ) and the high voltage side (high voltage side stable point S ₂ ) by changing the applied voltage. The memory information can be written in the circuit having the bistable state according to the stable state. Further, by utilizing this phenomenon, the bistable state of the circuit composed of the tunnel diode and the load can be changed by irradiating light having energy larger than the band gap of the semiconductor constituting the circuit.

[0038]

EXAMPLES Examples of the present invention will be described below along with their principles. (First Embodiment) FIG. 6 is an explanatory diagram of a semiconductor memory device of the first embodiment. This figure shows the voltage-current characteristics when the tunnel diode is irradiated with light having energy higher than the band gap of the semiconductor forming the tunnel diode. In the semiconductor memory device of this embodiment, a change in the stable state of a circuit having a bistable state composed of a tunnel diode and an ohmic resistance is utilized. A solid line a is a voltage-current characteristic when light is not irradiated, and has a low voltage side stable point S ₁ and a high voltage side stable point S ₂ . The broken line b is the voltage-current characteristic when light is irradiated, and there is a high voltage side stable point S ₂ , but there is no low voltage side stable point S ₁ .

This figure shows that the stable point can be controlled to the low voltage side stable point S ₁ or the high voltage side stable point S ₂ by changing the applied voltage. Further, it is shown that, by irradiating with light, the current of the tunnel diode decreases, the bistable state is broken, the stable point moves to the high voltage side stable point S ₂ , and information is written. Further, the stored information can be electrically changed by changing the applied voltage, and the stored information can be collectively reset by irradiating light.

The memory state of this semiconductor memory device can be read by applying a positive voltage to the collector electrode. That is, when the stable point is at the high-voltage side stable point S ₂ , the collector current flows, and when it is at the low-voltage side stable point S ₁ , the collector current does not flow. Can be read nondestructively.

(Second Embodiment) FIGS. 7A and 7B are explanatory views of a semiconductor memory device of the second embodiment. FIG. 7A shows an energy band and FIG. 7B shows voltage-current characteristics. This figure shows the voltage-current characteristics of an npn junction in which the n-type layer and the p-type layer all have an impurity concentration higher than the effective state density.
The high-impurity-concentration npn junction corresponds to a series connection of a tunnel diode composed of an n-type region on the left side and a p-type region and a tunnel diode composed of a p-type region and an n-type region on the right side, and a p-type region on the right side Since the tunnel diode composed of the n-type region is reverse-biased and has low resistance,
Since the characteristics of the tunnel diode composed of the p-type region and the p-type region become dominant, as shown in FIG. 7B, the voltage-current characteristics similar to those of the tunnel diode composed of the n-type region and the p-type region on the left side are almost the same. Shows.

FIG. 8 is a voltage-current characteristic diagram when light is emitted to the semiconductor memory device of the second embodiment. When not irradiating light (see curve a) Without irradiating the high impurity concentration npn junction with light, a negative voltage is applied to the n-type region on the left side of the high impurity concentration npn junction,
When a positive voltage is applied to the right n-type region, the energy level of the left n-type region becomes higher than that of the p-type region, and electrons that become the conduction band of the left n-type region are tunneled to the p-type region. It passes through the empty conduction band and moves to the n-type region on the right side by the Zener tunnel.

When the voltage is further increased, the tunnel current is out of the condition for flowing, and the current is decreased. When the voltage is further increased, the electrons pass through the conduction band of the p-type region and move to the n-type region on the right side by diffusion, so that the current flows again. This voltage-current characteristic can be obtained even when light having an intermediate intensity (light intensity intermediate between weak light and strong light described later) is applied. The voltage-current characteristic in this case has a low-voltage side stable point S ₁ and a high-voltage side stable point S ₂ .
2 shows a stable state.

When Weak Light is Irradiated (Refer to Curve b) The high impurity concentration npn junction is irradiated with weak light, a negative voltage is applied to the left n-type region, and a positive voltage is applied to the right n-type region. Then, the holes generated by the irradiation of the weak light are accumulated in the p-type region and the potential of the floating p-type region is lowered, so that the conduction band of the left n-type region faces the forbidden band of the p-type region. Therefore, it becomes difficult for electrons to move from the n-type region on the left side to the p-type region by tunneling, and the peak current and the valley current decrease. The voltage-current characteristic in this case has only the stable point S ₂ on the high voltage side, which indicates a monostable state.

When Strong Light is Irradiated (Refer to Curve c) The high impurity concentration npn junction is irradiated with strong light, a negative voltage is applied to the left n-type region, and a positive voltage is applied to the right n-type region. Then, a large amount of holes generated by the irradiation of this intense light are accumulated in the p-type region, and the level of the floating p-type region is significantly lowered, so that the electrons in the left n-type region are in the conduction band of the p-type region. Negative resistance is weakened because more electrons move to the right n-type region over the top, the current increases overall, the peak current increases, and the valley current further increases. In the voltage-current characteristic in this case, there is only the low-voltage side stable point S ₁ , which indicates a monostable state.

It should be noted that even when the light having an intermediate intensity between the weak light and the strong light is applied, the same characteristics as those in the case where the light is not applied are exhibited. The variation of the voltage-current characteristic due to the light irradiation is caused even when the applied voltage of the tunnel diode composed of the n-type region and the p-type region on the left side is a considerably high forward voltage.
There are cases where the forward voltage is extremely high and cases where the reverse bias is applied.

FIG. 8A shows a voltage-current characteristic (curve a) when the high impurity concentration npn junction is not irradiated with light, a voltage-current characteristic when the weak light is irradiated (curve b), and a strong light. The voltage-current characteristics (curve c) when irradiated are shown, but the voltage-current characteristics when light is not irradiated on the high impurity concentration npn junction show low-voltage side stable point S ₁ and high-voltage side stable point S _2. However, the voltage-current characteristics when the n-type region and the p-type region on the left side of the high-impurity concentration npn junction are irradiated with weak light only have a high-voltage side stable point S _2. There is only a low-voltage side stable point S _{1 in} the voltage-current characteristics when strong light is irradiated to the n-type region and the p-type region on the left side of.

Therefore, when the bistable state is formed without irradiating light to the high impurity concentration npn junction and weak light is irradiated to the n-type region and the p-type region on the left side of the high impurity concentration npn junction, Since the peak current of the npn junction decreases, as shown in the curve b, the high voltage side stable point S
₂ can be obtained, and when the n-type region and the p-type region on the left side of the high impurity concentration npn junction are irradiated with strong light, the peak current of the npn junction increases, so that the low voltage side stability as shown by the curve c is obtained. The point S ₁ can be obtained.

Further, n on the left side of the high impurity concentration npn junction
Even when the mold region and the p-type region are irradiated with light having an intermediate intensity between the weak light and the strong light, a bistable state can be formed. Therefore, the stable point can be moved between the low voltage side stable point S ₁ and the high voltage side stable point S ₂ by changing the light irradiation intensity, and only the optical signal is used without using an electrical signal. Allows the bistable state (memorized information) to be changed. Further, since the irradiation intensity of light has an addition effect, it is possible to move the stable point by optical signals from two directions (for example, the X direction and the Y direction).

(Third Embodiment) FIGS. 9A and 9B are explanatory views of a semiconductor memory device according to the third embodiment. FIG. 9A shows voltage-current characteristics and FIG. 9B shows a circuit diagram. In the semiconductor memory device of this embodiment, as shown in FIG. 9B, a tunnel diode (TD) having an impurity concentration higher than the effective state density and a p layer of a pnp structure or an n layer of an npn structure are formed. On the one hand, the impurity concentration is below the effective state density,
A heterojunction phototransistor (HPT) having a high emitter impurity concentration is connected in series, an outer end of the tunnel diode is grounded, an outer end of the heterojunction phototransistor is connected to Vcc, and a connection point between the tunnel diode and the heterojunction phototransistor. Is provided with an output terminal.

In this semiconductor memory device, the tunnel diode is not irradiated with light (see curve a in FIG. 9A), but the heterojunction phototransistor is irradiated with light to change the load line. That is, since the collector current of the BPT does not flow when the heterojunction phototransistor is not irradiated with light, the low voltage side stable point S ₁ where the load line and the rising line of the voltage-current characteristic of the tunnel diode intersect with each other.
(See curve b), the collector current flows when the intermediate layer of the heterojunction phototransistor is irradiated with weak light, so that the load line (see curve c) intersects with the rising line of the voltage-current characteristic of the tunnel diode. Low voltage side stable point S
_{In the} bistable state having ₁ and the stable point S ₂ on the high voltage side, when irradiating the intermediate layer of the heterojunction phototransistor with stronger light, the load line (see the curve d) and the rising line of the voltage-current characteristic of the tunnel diode are increased. Has only the high-voltage side stable point S ₂ intersecting.

Therefore, when the heterojunction phototransistor is not irradiated with light, the low voltage side stable point S ₁ is obtained, and when the heterojunction phototransistor is irradiated with weak light, the low voltage side stable point S ₁ and the high voltage side stable point are obtained. The point S ₂ can be obtained, and when the heterojunction phototransistor is irradiated with strong light, the high-voltage side stable point S ₂ can be obtained. Information can be stored. By irradiating both the tunnel diode having the negative resistance characteristic and the heterojunction phototransistor, which is the load, with light,
It is also possible to control the bistable state of this circuit.

(Fourth Embodiment) In the semiconductor memory device of this embodiment, two emitter layers, a common base layer,
A characteristic is that a multi-emitter heterojunction bipolar transistor (ME-HBT) having a common collector layer and having an impurity concentration of the emitter layer and the base layer equal to or higher than the effective state density is used.

FIG. 10 is an explanatory view of a semiconductor memory device of the fourth embodiment, (A) shows the structure of the semiconductor memory device,
(B) shows the voltage-current characteristic. In this figure, 1 is an InP semi-insulating substrate, 2 is a collector contact layer, 3 is a collector layer, 4 is a base layer, 5 ₁ is a first emitter layer,
5 ₂ is a second emitter layer, 6 ₁ is a first emitter contact layer, 6 ₂ is a second emitter contact layer, 7 ₁ is a first emitter electrode, 7 ₂ is a second emitter electrode, and 8 is a collector. It is an electrode.

This multi-emitter type heterojunction bipolar
In La-transistor (ME-HBT), InP half
On the insulating substrate 1, the thickness is 300 nm, the impurity concentration is 5 ×
10 ¹⁸cm^-3N-InGaAs collector controller
A tact layer 2 is formed, and a thickness of 300 nm, impure
Material concentration 3 × 10¹⁶cm^-3Of n-InGaAs
Lector layer 3 is formed, 100 nm thick, impure
Material concentration 5 × 10¹⁹cm ^-3Of p-InGaAs
A base layer 4 is formed, and a thickness of 200 nm and impurities are formed on the base layer 4.
Concentration 1 × 10¹⁹cm^-3First made of n-InAlAs
Emitter layer 5 ₁And the second emitter layer 5₂Is formed,
On top of that, a thickness of 150 nm and an impurity concentration of 5 × 10¹⁹cm^-3
First emitter contact made of n-InGaAs
Layer 6₁And the second emitter contact layer 6₂Is formed,
On top of that, the first emitter electrode 7₁And the second emitter electrode
7₂Is formed and collects on the collector contact layer 2.
The electrode 8 is formed.

FIG. 10B shows voltage-current characteristics in a bistable state of a circuit in which a forward tunnel diode having a negative resistance characteristic and a reverse tunnel diode (curve c) are loads. If a constant voltage of about 1 V is applied between the two emitter electrodes, the low voltage side stable point S
₁ and a bistable state having a high-voltage side stable point S ₂ (curve a), when the base layer is irradiated with light having an energy larger than the energy gap of the semiconductor material, the current of the tunnel diode in the forward direction is changed. It can be reduced as a whole (curve b), and the stable point can be uniformly moved to the high voltage side to have only the high voltage side stable point S ₂ . That is, it can be reset by irradiation of light. The stored information of the semiconductor memory device of this embodiment can be changed by changing the voltage between the two emitter electrodes.

(Fifth Embodiment) FIGS. 11A and 11B are explanatory views of a semiconductor memory device of the fifth embodiment. FIG. 11A shows the structure of the semiconductor memory device, and FIG. 11B shows its voltage-current characteristic. There is. In this figure, 11 is an InP semi-insulating substrate, 12 is a collector contact layer, 13 is a collector layer, 14 is a base layer,
15 ₁ is a first emitter layer, 15 ₂ is a second emitter layer, 16 ₁ is a first optical wiring layer, 16 ₂ is a second optical wiring layer, 17 ₁ is a first base same conductivity type layer, 17 ₂ is a second base same conductivity type layer, 18 ₁ is a first emitter electrode, 18
₂ is a second emitter electrode and 19 is a collector electrode.

This multi-emitter type heterojunction bipolar
In La-transistor (ME-HBT), InP half
A thickness of 300 nm and an impurity concentration of 5 are formed on the insulating substrate 11.
× 10¹⁸cm^-3Collector collector made of n-InGaAs
Contact layer 12 is formed, and a thickness of 300 nm is formed on the contact layer 12.
Impurity concentration 3 × 10¹⁶cm^-3From n-InGaAs
A collector layer 13 having a thickness of 100 n is formed on the collector layer 13.
m, impurity concentration 5 × 10 ¹⁹cm^-3P-InGaAs
A base layer 14 made of
m, impurity concentration 1 × 10¹⁹cm^-3N-InAlAs
First emitter layer 15 consisting of₁And the second emitter layer 15
₂Is formed, and the thickness is 150 nm and the impurity concentration is 5
× 10¹⁹cm^-3First light distribution consisting of n-InGaAs of
Line layer 16₁And the second optical wiring layer 16₂Is formed on it
Thickness 100 nm, impurity concentration 5 × 10¹⁹cm^-3P-I
First base same conductivity type layer 17 made of nGaAs₁And the
Second base same conductivity type layer 17₂Is formed and the first on it
Emitter electrode 18₁And the second emitter electrode 18₂Shape
And a collector electrode formed on the collector contact layer 12.
19 is formed.

When the first emitter electrode 18 ₁ to the second emitter electrode 18 ₂ of the semiconductor memory device of this embodiment are traced, the first emitter electrode 18 ₁ -first base same conductivity type layer 17 ₁ -first Optical interconnection layer 16 ₁ -first emitter layer 1
5 ₁ -base layer 14-second emitter layer 15 ₂ -second wiring layer 16 ₂ -second base same conductivity type layer 17 ₂ -second emitter electrode 18 _{2 and} becomes the input direction on the first emitter side. Is connected to (p ⁺ -n ⁺ -n-p ⁺ ), and (p ⁺ -n-n ⁺ -p ⁺ ) is connected to the output direction on the second emitter side.

Neglecting the reverse direction (n ⁺ -p ⁺ ) with low resistance, the forward tunnel diode (p ⁺ -n ⁺ ) on the first emitter side and the forward tunnel diode (p on the second emitter side). ⁺ −n ⁺ ) are connected in series.

FIG. 11 (B) shows a forward tunnel diode.
Mode (curve a) and forward tunnel diode (curve
The voltage-current characteristic of the circuit which makes d) a load is shown. First
1 emitter electrode 18₁Is positive and the second emitter electrode
18₂Apply a constant voltage of about 1V, which is negative
And the low voltage side stable point S₁And the high voltage side stable point S ₂Have
Showing the bistable state (curve a), the first optical wiring layer 16
₁Through the first emitter layer 15₁And the base layer 14
Energy above the energy gap of semiconductor materials
When it is irradiated with weak light, it has a forward tunnel diode.
Current is reduced overall and the stable point is uniformly set to the high voltage side.
Move it to the high voltage side stable point S₂With only (curve
b).

[0062] The first through the first optical wiring layer 16 ₁
When the emitter layer 15 ₁ and the base layer 14 are irradiated with strong light having an energy equal to or larger than the energy gap of the semiconductor material, the current of the tunnel diode in the forward direction generally increases, and the stable point is uniformly set to the low voltage side. It can be moved to a state having only the low voltage side stable point S ₁ (curve c).

In this way, by changing the intensity of the light irradiating the first emitter layer 15 ₁ and the base layer 14 through the first optical wiring layer 16 ₁ , the low voltage side stable point S ₁ and
A bistable state (curve a) having a high voltage side stable point S ₂ , and
It is possible to control between a state having only the high voltage side stable point S ₂ (curve b) and a state having only the low voltage side stable point S ₁ (curve c), and this state is made to correspond to 1 and 0. As a result, a semiconductor memory device can be realized.

In order to further maintain symmetry, the same layer as the emitter layer is formed on the first optical wiring layer 16 ₁ and the second optical wiring layer 16 ₁ .
₂ and the first base same conductivity type layer 17 _1, it is also effective to interpose between the second base same conductivity type layer 17 _2. Also, the first
Since an optical signal can be applied through the optical wiring layer 16 ₁ and the second optical wiring layer 16 _{2 of} the first emitter electrode 18
_The stored information can be independently rewritten by an optical signal while a certain voltage is always applied between ₁ and the second emitter electrode 18 ₂ . This indicates that, in the case of high integration, it is possible to avoid a decrease in yield and an increase in chip area due to an increase in electrical wiring density.

(Sixth Embodiment) FIGS. 12A and 12B are explanatory views of a semiconductor memory device of the sixth embodiment. FIG. 12A shows the structure of the semiconductor memory device and FIG. 12B shows its circuit. In the figure, 21 is an InP semi-insulating substrate, 22 is a collector layer, and 23.
Is a base layer, 24 ₁ is a first emitter layer, and 24 ₂ is a _second emitter layer.
Emitter layer, 24 ₃ is a third emitter layer, 24 ₄ is a fourth emitter layer, 25 ₁ is a first emitter contact layer, 25 ₂ is a second emitter contact layer, and 25 ₃ is a third emitter contact. Layer, 25 ₄ is a fourth emitter contact layer, 26 ₁ is a first emitter electrode, 26 ₂ is a second emitter electrode, 26 ₃ is a third emitter electrode, 26
Reference numeral ₄ is a fourth emitter electrode, 27 is a base electrode, and 28 is a collector electrode.

This multi-emitter type heterojunction bipolar
In a transistor memory device, an InP semi-insulating group is used.
On the plate 21, a thickness of 300 nm and an impurity concentration of 5 × 10¹⁸
cm ^-3The collector layer 22 made of n-InGaAs of
Formed on top of it with a thickness of 100 nm and an impurity concentration of 5 × 10
¹⁹cm^-3Of the p-InGaAs base layer 23 of
Formed on top of it with a thickness of 200 nm and an impurity concentration of 1 × 10
¹⁹cm^-3First emitter layer made of n-InAlAs
24₁, The second emitter layer 24₂, The third emitter layer 2
4₃, The fourth emitter layer 24_FourIs formed and thick on it
150 nm, impurity concentration 5 × 10¹⁹cm^-3N-In
First emitter contact layer 25 made of GaAs₁,
Second emitter contact layer 25₂, The third emitter
Contact layer 25₃, Fourth emitter contact layer 25_Four
Is formed on the first emitter electrode 26.₁, Second
Emitter electrode 26₂, The third emitter electrode 26₃, First
4 emitter electrode 26_FourAre formed on the base layer 23.
A base electrode 27 is formed on the collector layer 22, and a base electrode 27 is formed on the collector layer 22.
The collector electrode 28 is formed.

The first emitter electrode 26 ₁ -first
Emitter contact layer 25 ₁ -first emitter layer 24
₁ -base layer 23-second emitter layer 24 _2- second emitter contact layer 25 _2- second emitter electrode 26 ₂
One semiconductor memory device is formed in this order, and the third emitter electrode 26 ₃ -third emitter contact layer 25 ₃ -third emitter layer 24 ₃ -base layer 23 -fourth emitter layer 24 ₄ -third Another semiconductor memory device is formed in the order of _4th emitter contact layer 25 ₄ -fourth emitter electrode 26 ₄ , and this circuit is shown in FIG.

In the semiconductor memory device of this embodiment,
By using a plurality of multi-emitter heterojunction bipolar transistors and the p-type layer of the pn tunnel diode or the base layer of the bipolar transistor in common, the manufacturing process and structure can be simplified. In this case, by irradiating the common base layer with light,
The semiconductor memory device can be effectively operated.

(Seventh Embodiment) FIGS. 13A and 13B are explanatory views of a semiconductor memory device of the seventh embodiment. FIG. 13A shows the configuration of the semiconductor memory device, and FIG. 13B shows its voltage-current characteristic. There is. In this figure, 31 is an InP semi-insulating substrate, 32 is a collector contact layer, 33 is a collector layer, 34 is a base layer,
35 ₁ is a first emitter layer, 35 ₂ is a second emitter layer, 36 ₁ is a first optical wiring layer, 36 ₂ is a second optical wiring layer, 37 ₁ is a base same conductivity type layer, 38 ₁ is The first emitter electrode, 38 ₂ is the second emitter electrode, and 39 is the collector electrode.

In this multi-emitter heterojunction bipolar transistor, a collector contact layer 32 of n-InGaAs having a thickness of 300 nm and an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ is formed on an InP semi-insulating substrate 31. , With a thickness of 300 nm and an impurity concentration of 3 × 1
0 ¹⁶ cm ⁻³ n-InGaAs collector layer 33
Is formed, and the thickness is 100 nm and the impurity concentration is 5 ×.
Base layer 34 made of 10 ¹⁹ cm ⁻³ of p-InGaAs
Is formed, and the thickness is 200 nm and the impurity concentration is 1 ×.
A first emitter layer 35 ₁ and a second emitter layer 35 ₂ made of 10 ¹⁹ cm ⁻³ of n-InAlAs are formed, and an n layer having a thickness of 150 nm and an impurity concentration of 5 × 10 ¹⁹ cm ⁻³ is formed thereon.
A first optical wiring layer 36 ₁ and a second optical wiring layer 36 ₂ made of InGaAs are formed, a base same conductivity type layer 37 ₁ is formed on the first optical wiring layer 36 ₁ , and the base same conductivity type layer 37 ₁ is formed. A first emitter electrode 38 ₁ and a second emitter electrode 38 ₂ are formed on the mold layer 37 ₁ and the second optical wiring layer 36 ₂ , and a collector electrode 39 is formed on the collector contact layer 32. .

The second emitter of the semiconductor memory device of this embodiment
Electrode 38₂To the first emitter electrode 38₁Follow up
Then, the second emitter electrode 38₂-Second optical wiring layer 36
₂-Second emitter layer 35₂-Base layer 34-First layer
Mitter layer 35₁-First optical wiring layer 36₁-Base same conductivity
Mold layer 37₁-First emitter electrode 38₁Next, second
On the mitter side (p⁺-N-p⁺), On the first emitter side
(P⁺-N-n⁺-P ⁺) Is connected.

FIG. 13B shows a tunnel diode in the forward direction.
Of the forward zener diode (curve a)
Voltage-current characteristics of circuit with load on line d) (bistable state)
Is shown. First emitter electrode 38₁Ground to the first
2 emitter electrode 38₂Connected to Vcc
When a potential difference is applied, the low voltage side stable point S₁And high voltage side
Fixed point S ₂Shows a bistable state with (curve a), the first
Optical wiring layer 36₁Through the first emitter layer 35₁And
The energy gap of the semiconductor material in the source layer 34
When irradiated with weak light having the energy of
The current in the tunnel diode is reduced as a whole,
The high voltage side stable point S₂Have only
The state (curve b) can be set.

[0073] The first through the first optical wiring layer 36 ₁
When the emitter layer 35 ₁ and the base layer 34 are irradiated with strong light having an energy larger than the energy gap of the semiconductor material, the current in the forward tunnel diode increases overall, and the stable point is uniformly set to the low voltage side. It can be moved to a state having only the low voltage side stable point S ₁ (curve c).

As described above, by changing the intensity of the light irradiating the first emitter layer 35 ₁ and the base layer 34 through the first optical wiring layer 36 ₁ , the low voltage side stable point S ₁ and
A bistable state (curve a) having a high voltage side stable point S ₂ , and
It is possible to control between a state having only the high voltage side stable point S ₂ (curve b) and a state having only the low voltage side stable point S ₁ (curve c), and this state is made to correspond to 1 and 0. As a result, a semiconductor memory device can be realized.

In the semiconductor memory device of this embodiment, 2
The feature is that a high-concentration layer having the same conductivity type as the base layer is formed on only one of the two emitter layers. The feature is that the base same conductivity type layer having the same conductivity type as the base layer. It is an object of the present invention to realize a relatively small semiconductor memory device capable of changing the bistable state by irradiating an emitter layer (n-type layer) having a light signal with an optical signal.
Even if an optical signal is applied to an emitter layer (n-type layer) that does not have the base conductivity type layer, the negative positive resistance characteristic is hardly affected.

(Eighth Embodiment) FIG. 14 is an explanatory view of a semiconductor memory device of an eighth embodiment, (A) and (B) showing energy bands, and (C) showing arrangement of memory cells. ing. In a semiconductor memory device using a multi-emitter heterojunction bipolar transistor, the stored information can be read out by detecting the presence or absence of a collector current when a positive bias voltage is applied to the collector electrode.

That is, as shown in FIG. 14A, in a semiconductor memory device using a multi-emitter type heterojunction bipolar transistor, if the voltage difference between two emitters is large, a large collector bias voltage is applied. When applied, electrons are injected from the emitter and a collector current flows, but if the voltage difference between the two emitters is small, no current flows, so that stored information can be read.

Further, as shown in FIG. 14B, in the semiconductor memory device using the multi-emitter heterojunction bipolar transistor, the collector current also changes by irradiating the base layer with light. Therefore, the stored information can be read by irradiating the base layer with light.

Since it is possible to read out only the storage information of the storage cell to which both the optical signal and the electric signal are input, the storage cell of the designated storage cell among the plurality of storage information arranged in a matrix. The stored information can be selectively read.

That is, as shown in FIG. 14C, the memory cells M ₁₁ , M ₁₂ , M ₁₃ , M ₂₁ , M ₂₂ , M ₂₃ ,
M ₃₁ , M ₃₂ , M ₃₃ are regularly arranged on the X and Y axes, and memory cells M ₁₁ , M ₁₂ , M ₁₃ or M arranged in the X axis direction.
₂₁ and M ₂₂ , M ₂₃ , or M ₃₁ , M ₃₂ , and M ₃₃ receive an optical signal hν.
₁ , hν ₂ , hν ₃ are applied, and electrical signals ES ₁ , ES ₂ , ES are applied to M ₁₁ , M ₂₁ , M ₃₁ , or M ₁₂ , M ₂₂ , M ₃₂ , or M ₁₃ , M ₂₃ , M _33. By applying ₃ ,
The stored information of the storage cell at the intersection can be selectively read.

In this case, the optical signal can be applied not only to the base layer but also to the collector layer of the heterojunction bipolar transistor. This figure shows hν ₂ and E
A state in which S ₂ is applied and the memory cell M ₂₂ is selectively read is shown.

Furthermore, a high concentration pnp junction or npn
A semiconductor memory device in which a large number of devices having a bistable state, in which a junction and a resistance layer are connected in series, are arranged in an array, irradiates an n-type layer with an optical signal from the X direction and the Y direction to store information in a memory cell. Can be changed.

Further, the stored information can be changed by applying both the optical signal and the electric signal to the semiconductor memory device. In other words, when this structure is used, the stored information changes only when both the optical signal and the electrical signal match, so it is possible to add the optical signals to each other and to add the optical signals to the electrical signals, and selectively. The stored information can be rewritten.

(Ninth Embodiment) FIG. 15 is an explanatory view of a semiconductor logic circuit device of a ninth embodiment, (A) shows the structure of the semiconductor logic circuit device, and (B) shows its circuit.
(C) shows voltage-current characteristics, and (D) shows a truth table. In the figure, 31 is an InP semi-insulating substrate, 32 is a collector contact layer, 33 is a collector layer, 34 is a base layer, 35 ₁ is a first emitter layer, 35 ₂ is a second emitter layer, and 36 ₁ is a _first emitter layer. Optical interconnection layer, 36 ₂ is a second optical interconnection layer, 37 ₁ is a base same conductivity type layer, 38 ₁ is a first emitter electrode, 38 ₂ is a second emitter electrode, and 39 is a collector electrode.

In the semiconductor logic circuit device of this embodiment, a thickness of 300 nm is formed on the InP semi-insulating substrate 31.
A collector contact layer 32 made of n-InGaAs having an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ is formed, and an n-InG having a thickness of 300 nm and an impurity concentration of 3 × 10 ¹⁶ cm ⁻³ is formed thereon.
A collector layer 33 made of aAs is formed on the p-In layer having a thickness of 100 nm and an impurity concentration of 5 × 10 ¹⁹ cm ^−3.
A base layer 34 made of GaAs is formed, on which n-In having a thickness of 200 nm and an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ is formed.
A first emitter layer 35 ₁ and a second emitter layer 35 ₂ made of AlAs are formed, and a first optical wiring layer made of n-InGaAs having a thickness of 150 nm and an impurity concentration of 5 × 10 ¹⁹ cm ⁻³ is formed thereon. 36 ₁ and the second optical wiring layer 36 ₂ are formed, and the base same conductivity type layer 37 is formed on the first optical wiring layer 36 _1.
1 is formed, the first emitter electrode 38 ₁ and the second emitter electrode 38 ₂ are formed on the base same conductivity type layer 37 ₁ and the second optical wiring layer 36 ₂ , and the collector contact layer 32 is formed.
A collector electrode 39 is formed on.

If the second emitter electrode 38 ₂ to the first emitter electrode 38 ₁ of the semiconductor logic circuit device of this embodiment are traced, (p ⁺ -n-p ⁺ ) is present on the second emitter side. (P ⁺ -n-n ⁺ -p ⁺ ) is connected to the side. FIG. 15B shows a circuit of this semiconductor logic circuit device.

FIG. 15C shows a voltage-current characteristic (bistable state) of a circuit having a forward tunnel diode (curve a) and a forward Zener diode (curve d) as a load.
Is shown. When the first emitter electrode 38 ₁ is grounded and the second emitter electrode 38 ₂ is connected to Vcc, a bistable state having a low voltage side stable point S ₁ and a high voltage side stable point S ₂ is shown (curve a), when the first emitter layer 35 ₁ and the base layer 34 are irradiated with weak light having an energy larger than the energy gap of the semiconductor material through the first optical wiring layer 36 ₁ , the forward tunnel diode current is entirely And the stable point is uniformly moved to the high voltage side, and the state has only the high voltage side stable point S ₂ (curve b).

[0088] The first through the first optical wiring layer 36 ₁
When the emitter layer 35 ₁ and the base layer 34 are irradiated with strong light having an energy larger than the energy gap of the semiconductor material, the current in the forward tunnel diode increases overall, and the stable point is uniformly set to the low voltage side. It moves and becomes a state having only the low voltage side stable point S ₁ (curve c).

Thus, the first optical wiring layer 36₁Through
The first emitter layer 35₁And the light that irradiates the base layer 34
By changing the strength of the stable point, stable on the low voltage side
Point S ₁And high voltage side stable point S₂A bistable state (curve
a) and stable point S on the high voltage side₂With only (curve
b) and the low voltage side stable point S₁With only (curve
It can be controlled between c) and this state is paired with 1 and 0.
To realize a semiconductor logic circuit device.
You can

FIG. 15D shows the truth table of the semiconductor logic circuit device of this embodiment. The first optical wiring layer 36 is shown in FIG.
The strong light is irradiated with a first energy gap than the energy of the semiconductor material in the emitter layer 35 ₁ and the base layer 34 throughout _the

[0] At the same time, the second emitter layer 35 ₂ and the base layer 34 are passed through the second optical wiring layer 36 ₂ .
Illuminate the

When [0], the output voltage becomes [1].

Further, the first emitter layer 35 ₁ and the base layer 34 are irradiated with strong light.

[0], second emitter layer 35 ₂
When the base layer 34 is not irradiated with light [1], its output voltage is held.

In addition, the strong light is not applied to the first emitter layer 35 ₁ and the base layer 34 [1], and at the same time, the light is not applied to the second emitter layer 35 ₂ and the base layer 34 [1]. 1].

In the semiconductor logic circuit device of this embodiment, the first emitter electrode 38 ₁ is grounded, the positive voltage Vcc is connected to the second emitter electrode to form a bistable state, and the collector has a load resistance. A sequential circuit can be formed by connecting a positive power supply with the pin in between and extracting an output signal from between the collector electrode 39 and the load resistor R.

In this case, p ⁺ n on the side of the first emitter electrode
Two optical signals hν ₁ and hν on the n layer and the n ⁺ layer of ⁺ np ⁺
By applying ₂ and adjusting the voltage between the two emitter electrodes so that the output changes only when both of the two optical signals are on or off, a state holding circuit for the optical signal can be formed. .

Further, in this semiconductor logic circuit device, if the optical signal is applied to the base layer or the collector layer, the output signal can be taken out only when the optical clock is input to the base layer.

[0096]

As described above, according to the semiconductor memory device of the present invention, the semiconductor memory device has a relatively simple structure and a relatively simple structure, and information can be written and read by an optical signal or an electrical signal. It is possible to provide a semiconductor memory device capable of
Since parallel processing of information by an optical signal becomes possible, access time can be significantly shortened as compared with a conventional semiconductor memory device by an electric signal, and as a result, a large information processing capability can be provided.

Further, according to the semiconductor logic circuit device of the present invention, the stable point can be controlled between the low voltage side stable point and the high voltage side stable point by changing the intensities of the two optical signals to be applied. It is possible to realize a semiconductor logic circuit device by making this state correspond to 1 and 0.

[Brief description of drawings]

FIG. 1 is a voltage-current characteristic explanatory diagram (1) of a tunnel diode, and (A) to (C) show energy bands.

FIG. 2 is a diagram (2) illustrating a voltage-current characteristic of a tunnel diode, in which (D) and (E) show an energy band, and (F) shows a voltage-current characteristic.

FIG. 3 is a voltage-current characteristic diagram (1) of the tunnel diode when the load is changed, and (A) to (C) show the voltage-current characteristic of each load.

FIG. 4 is a voltage-current characteristic diagram (2) of the tunnel diode when the load is changed, and (D) and (E) show the voltage-current characteristic of each load.

FIG. 5 is a voltage-current characteristic diagram when the applied voltage of the tunnel diode is changed, and FIG.
(B) shows the voltage-current characteristics when the applied voltage is high.

FIG. 6 is an explanatory diagram of a semiconductor memory device according to a first embodiment.

FIG. 7 is an explanatory diagram of a semiconductor memory device according to a second embodiment,
(A) shows an energy band, and (B) shows a voltage-current characteristic.

FIG. 8 is a voltage-current characteristic diagram when the semiconductor memory device of the second embodiment is irradiated with light.

FIG. 9 is an explanatory diagram of a semiconductor memory device according to a third embodiment,
(A) shows voltage-current characteristics, and (B) shows a circuit diagram.

FIG. 10 is an explanatory diagram of a semiconductor memory device according to a fourth embodiment, where (A) shows the configuration of the semiconductor memory device and (B) shows its voltage-current characteristics.

FIG. 11 is an explanatory diagram of a semiconductor memory device according to a fifth embodiment, where (A) shows the configuration of the semiconductor memory device and (B) shows its voltage-current characteristics.

FIG. 12 is an explanatory diagram of a semiconductor memory device according to a sixth embodiment, where (A) shows the configuration of the semiconductor memory device and (B) shows its circuit.

FIG. 13 is an explanatory diagram of a semiconductor memory device according to a seventh embodiment, where (A) shows the configuration of the semiconductor memory device and (B) shows its voltage-current characteristics.

FIG. 14 is an explanatory diagram of a semiconductor memory device according to an eighth embodiment, in which (A) and (B) show energy bands, and (C).
Indicates the arrangement of memory cells.

FIG. 15 is an explanatory diagram of a semiconductor logic circuit device of a ninth embodiment, showing the structure of (A) semiconductor logic circuit device,
(B) shows the circuit, (C) shows the voltage-current characteristic, and (D) shows the truth table.

[Explanation of symbols]

1 InP Semi-insulating Substrate 2 Collector Contact Layer 3 Collector Layer 4 Base Layer 5 ₁ First Emitter Layer 5 ₂ Second Emitter Layer 6 ₁ First Emitter Contact Layer 6 ₂ Second Emitter Contact Layer 7 ₁ 1st Emitter electrode 7 ₂ second emitter electrode 8 collector electrode 11 InP semi-insulating substrate 12 collector contact layer 13 collector layer 14 base layer 15 ₁ first emitter layer 15 ₂ second emitter layer 16 ₁ first optical wiring Layer 16 ₂ Second wiring layer 17 ₁ First base conductivity type layer 17 ₂ Second base conductivity type layer 18 ₁ First emitter electrode 18 ₂ Second emitter electrode 19 Collector electrode 21 InP semi-insulating substrate 22 Collector layer 23 Base layer 24 ₁ First emitter layer 24 ₂ Second emitter layer 24 ₃ Third emitter layer 24 ₄ Fourth emitter layer 25 ₁ First emitter layer Ntakuto layer 25 ₂ second emitter contact layer 25 ₃ third emitter contact layer 25 ₄ fourth emitter contact layer 26 ₁ first emitter electrode 26 ₂ second emitter electrode 26 ₃ third emitter electrode 26 ₄ second 4 emitter electrode 27 base electrode 28 collector electrode 31 InP semi-insulating substrate 32 collector contact layer 33 collector layer 34 base layer 35 ₁ first emitter layer 35 ₂ second emitter layer 36 ₁ first optical wiring layer 36 ₂ Second optical wiring layer 37 ₁ Base same conductivity type layer 38 ₁ First emitter electrode 38 ₂ Second emitter electrode 39 Collector electrode

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display area H01L 27/082

Claims (21)

[Claims] 1. A tunnel diode having a negative resistance characteristic in which an impurity concentration of each semiconductor forming a pn junction is equal to or higher than an effective state density, and a load such as a tunnel diode, an ohmic resistance element, a Schottky diode, and a constant current source. The semiconductor storage device is characterized in that the bistable state formed by the circuit is controlled by irradiating the pn junction with light having energy higher than the band gap of the semiconductor forming the pn junction. 2. A semiconductor device having a negative resistance characteristic in which an impurity concentration of each semiconductor of a pnp junction or an npn junction is equal to or higher than an effective state density, a tunnel diode, an ohmic resistance element, a Schottky diode, a constant current source, and the like. A semiconductor memory device, wherein a bistable state formed by a circuit serving as a load is controlled by irradiating the semiconductor element with light having energy higher than a band gap of a semiconductor forming the semiconductor element. 3. A dual diode formed by a tunnel diode having a negative resistance characteristic in which an impurity concentration of each semiconductor forming a pn junction is equal to or higher than an effective state density, and a circuit using an npn-type or pnp-type bipolar transistor as a load. A semiconductor memory device, wherein a stable state is controlled by irradiating the pn junction with light having energy higher than a band gap of a semiconductor forming the pn junction. 4. A semiconductor device having a negative resistance characteristic in which an impurity concentration of each semiconductor of a pnp junction or an npn junction is equal to or higher than an effective state density, and a circuit which uses a bipolar transistor having an npn junction or a pnp junction as a load. A semiconductor memory device, wherein the bistable state is controlled by irradiating the semiconductor element with light having energy higher than a band gap of a semiconductor forming the semiconductor element. 5. A tunnel diode having a negative resistance characteristic in which an impurity concentration of each semiconductor forming a pn junction is equal to or higher than an effective state density, and a circuit using a bipolar transistor having an npn junction or a pnp junction as a load. A bistable state in the bipolar transistor,
A semiconductor memory device, which is controlled by irradiating light having energy higher than a band gap of a semiconductor forming the bipolar transistor. 6. A semiconductor element having a negative resistance characteristic in which an impurity concentration of each semiconductor of a pnp junction or an npn junction is equal to or higher than an effective state density, and a circuit which uses a bipolar transistor having an npn junction or a pnp junction as a load A semiconductor memory device characterized in that the bistable state is controlled by irradiating the bipolar transistor with light having an energy larger than a band gap of a semiconductor forming the bipolar transistor. 7. A semiconductor memory according to claim 1, wherein a semiconductor element having a negative characteristic and a load are irradiated with light to control a bistable state. apparatus. 8. The semiconductor memory according to claim 1, wherein a stable point in a bistable state is moved by the irradiation intensity of light to change stored information. apparatus. 9. Two or more emitter layers of the first conductivity type,
A multi-emitter heterojunction bipolar transistor having a common base layer of the second conductivity type and a common collector layer of the first conductivity type, and the impurity concentration of the emitter layer and the base layer is equal to or higher than the effective state density is used. 7. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. 10. A pnp or npn junction is memorized by a change in peak current and valley current when weak light having energy higher than a band gap of a semiconductor forming the junction is irradiated and when strong light is irradiated. 7. The semiconductor memory according to claim 2, wherein the stored information is read out depending on the presence or absence of a collector current when the information is rewritten and a positive voltage is applied to the collector electrode. apparatus. 11. A tunnel diode having a pn junction and a p-type layer or an n-type layer of a bipolar transistor having an npn junction or pnp matching, which is a load, are commonly used. The semiconductor memory device described in. 12. The semiconductor memory device according to claim 10, wherein stored information is rewritten by irradiating the common p-type layer or n-type layer with light. 13. A base same conductivity type layer having a high impurity concentration of the same conductivity type as the base layer is formed on an emitter layer of a multi-emitter heterojunction bipolar transistor, and the emitter is formed on the base same conductivity type layer. The semiconductor memory device according to claim 8, wherein an electrode is formed. 14. The semiconductor memory device according to claim 12, wherein random information can be written by independently irradiating two or more emitter layers with light. 15. In a multi-emitter heterojunction bipolar transistor, a base same conductivity type layer having the same conductivity type as the base layer and having a high impurity concentration is formed on one emitter layer, and on the other emitter layer. The base of the same conductivity type layer is formed on the substrate.
The semiconductor memory device described in. 16. A positive bias voltage is applied between the collector layer and the emitter layer, the base layer is irradiated with light having an energy larger than the band gap of a semiconductor forming the base layer, or 15. The semiconductor memory device according to claim 1, wherein stored information is read by applying a bias voltage and light at the same time. 17. A semiconductor characterized in that a plurality of semiconductor memory devices according to any one of claims 1 to 15 are arranged in an array, and information is written and read by an optical signal. Storage device. 18. The semiconductor memory device according to claim 14, wherein one emitter electrode is grounded, a positive voltage is applied to the other emitter electrode to form a bistable state, and a load resistance is applied to the collector electrode. A positive power source is connected via an output terminal to the connection point between the collector and the load resistor, and the emitter layer to which the first emitter electrode is connected has an energy larger than the band gap of the semiconductor forming the emitter layer. The semiconductor logic circuit device is characterized in that the stable state is controlled by irradiating light having a constant value, and the stable state is read by the voltage generated at the output terminal. 19. The semiconductor logic circuit device according to claim 17, wherein an output signal is taken out in synchronization with an optical clock applied to the base layer. 20. A semiconductor element having a negative resistance characteristic in which the impurity concentration of each semiconductor of the pnp junction or the npn junction is equal to or higher than the effective state density, and a tunnel diode, an ohmic resistance element, a Schottky diode, an npn junction or a pnp junction. A bistable state formed by a circuit having a bipolar transistor having a constant current source as a load,
Semiconductor memory devices that are controlled by irradiating the semiconductor elements with light having an energy larger than the band gap of a semiconductor forming the semiconductor elements are arranged in an array, and each semiconductor memory device has an X-axis and a Y-axis. A semiconductor memory device, characterized in that a bistable state is controlled by irradiating an optical signal having an energy larger than a bandgap which constitutes a semiconductor element having a negative resistance characteristic or a bipolar transistor which is a load from each direction. 21. A semiconductor element having a negative resistance characteristic in which the impurity concentration of each semiconductor of the pnp junction or the npn junction is equal to or higher than the effective state density, and a tunnel diode, an ohmic resistance element, a Schottky diode, an npn junction or a pnp junction. A bistable state formed by a circuit having a bipolar transistor having a constant current source as a load,
Semiconductor memory devices that are controlled by irradiating the semiconductor elements with light having energy higher than the band gap of a semiconductor forming the semiconductor elements are arranged in an array, and the semiconductor memory devices are arranged in the negative direction from the X-axis direction. Characterized in that a bistable state is controlled by irradiating an optical signal having an energy larger than a bandgap forming a semiconductor element having a resistance characteristic or a bipolar transistor as a load, and applying an electrical signal from the Y-axis direction. Semiconductor memory device.