JPH08264522A - Ferroelectric memory element - Google Patents
Ferroelectric memory elementInfo
- Publication number
- JPH08264522A JPH08264522A JP7064019A JP6401995A JPH08264522A JP H08264522 A JPH08264522 A JP H08264522A JP 7064019 A JP7064019 A JP 7064019A JP 6401995 A JP6401995 A JP 6401995A JP H08264522 A JPH08264522 A JP H08264522A
- Authority
- JP
- Japan
- Prior art keywords
- ferroelectric
- memory element
- resin
- film
- protective film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は強誘電体記憶素子に関
し、特に強誘電体を用いた不揮発性メモリに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device, and more particularly to a non-volatile memory using a ferroelectric substance.
【０００２】[0002]
【従来の技術】最近開発が進められている強誘電体記憶
素子、すなわちＦＲＡＭ（Ｆｅｒｒｏｅｌｅｃｔｒｉｃ
Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）の多く
は、ＤＲＡＭのキャパシタを強誘電体キャパシタに置き
換えた構成をしており（特開平２−１１３４９６号公
報）、その保護膜として、多くは窒化シリコン被膜を用
いており、その形成には原料ガスとしてシラン、ジクロ
ルシラン、アンモニアなどを用いてプラズマＣＶＤなど
の方法で形成されている。2. Description of the Related Art A ferroelectric memory device, which has been recently developed, that is, an FRAM (Ferroelectric)
Many of the Random Access Memories) have a structure in which the DRAM capacitor is replaced with a ferroelectric capacitor (Japanese Patent Laid-Open No. 2-113496), and a silicon nitride film is mostly used as a protective film thereof. It is formed by a method such as plasma CVD using silane, dichlorosilane, ammonia or the like as a raw material gas.
【０００３】また、配線と素子を分離する層間絶縁膜も
同様に、原料ガスとしてシラン、酸化窒素、酸素などを
用いてプラズマＣＶＤなどの方法で形成されている。Similarly, the interlayer insulating film for separating the wiring from the element is also formed by a method such as plasma CVD using silane, nitrogen oxide, oxygen or the like as a source gas.
【０００４】[0004]
【発明が解決しようとする課題】しかし、これらのガス
はいずれも水素元素を多量に含み、これが強誘電体の劣
化をもたらしていると考えられ、保護膜、層間絶縁膜形
成後に強誘電体の自発分極が大きく低下する現象がみら
れる。従って、この問題を解決することは、強誘電体記
憶素子製造上の大きな課題であった。However, all of these gases contain a large amount of hydrogen element, which is considered to cause the deterioration of the ferroelectric substance. There is a phenomenon that the spontaneous polarization is significantly reduced. Therefore, solving this problem has been a major problem in manufacturing the ferroelectric memory element.
【０００５】本発明は、このような従来の未解決の課題
を解決するべく行われたものであり、強誘電体の劣化を
伴わずに保護膜、層間絶縁膜を形成し、再現性、安定性
に優れ、かつ生産上の収率向上に優れた強誘電体記憶素
子を提供することを課題とする。The present invention has been made in order to solve the above-mentioned unsolved problems of the related art, and a protective film and an interlayer insulating film are formed without deterioration of the ferroelectric substance, and the reproducibility and stability are improved. An object of the present invention is to provide a ferroelectric memory element which is excellent in productivity and is improved in yield in production.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に、請求項１に係る発明は、ＭＯＳトランジスタおよび
強誘電体を用いたキャパシタからなる記憶素子、または
ゲート絶縁膜部分に強誘電体を有するＭＯＳトランジス
タからなる記憶素子がＳｉ単結晶基板上に形成された強
誘電体記憶素子において、前記記憶素子を保護するかま
たは配線と分離する絶縁膜が樹脂被膜であることを特徴
とする。In order to solve the above-mentioned problems, the invention according to claim 1 provides a memory element comprising a MOS transistor and a capacitor using a ferroelectric substance, or a ferroelectric substance in a gate insulating film portion. In a ferroelectric memory element in which a memory element including a MOS transistor included therein is formed on a Si single crystal substrate, an insulating film that protects the memory element or separates it from wiring is a resin film.
【０００７】また、請求項２に係る発明は、前記強誘電
体がＰｂＴｉＯ3 、ＰｂＺｒＴｉＯ 3 またはＰｂＬａＺ
ｒＴｉＯ3 からなることを特徴とする。さらに、請求項
３に係る発明は、前記樹脂被膜がポリイミド構造を有す
る樹脂であることを特徴とする。さらに、請求項４に係
る発明は、前記ポリイミド構造を有する樹脂は感光性で
あることを特徴とする。According to a second aspect of the present invention, the ferroelectric
Body is PbTiO3, PbZrTiO 3Or PbLaZ
rTiO3It is characterized by consisting of. Further claims
In the invention according to 3, the resin coating has a polyimide structure
The resin is a resin. Further, according to claim 4,
According to the invention, the resin having the polyimide structure is photosensitive.
It is characterized by being.
【０００８】本発明において、強誘電体を用いたキャパ
シタとは、導電体により強誘電体層をはさんだ構造をも
つキャパシタのことである。また、ゲート絶縁膜部分に
強誘電体を有するトランジスタとは、ゲート絶縁膜とし
て直接強誘電体をＳｉ基板上に形成した構造またはゲー
ト酸化膜として常誘電体膜、強誘電体膜の積層膜をＳｉ
基板上に形成した構造等のことである。In the present invention, a capacitor using a ferroelectric substance is a capacitor having a structure in which a ferroelectric layer is sandwiched by a conductor. Further, a transistor having a ferroelectric substance in the gate insulating film portion means a structure in which a ferroelectric substance is directly formed on a Si substrate as a gate insulating film or a laminated film of a paraelectric film and a ferroelectric film as a gate oxide film. Si
A structure formed on a substrate.
【０００９】本発明における樹脂被膜としては、炭素、
水素、酸素等を構成元素とした様々なものがあるが、そ
の中でもポリイミド構造をもつ樹脂が最も好ましい。ポ
リイミド構造を有する樹脂とは、ＣＯＮＨＣＯイミド結
合をもつ樹脂であり、活性水素を発生することなく膜形
成が可能である。また、感光性のポリイミド構造を有す
る樹脂とは、主に紫外線によりポリイミド構造を完成
し、固化する特性などの感光性を有する樹脂である。The resin coating used in the present invention is carbon,
Although there are various substances having hydrogen, oxygen and the like as constituent elements, a resin having a polyimide structure is most preferable. The resin having a polyimide structure is a resin having a CONHCO imide bond, and can form a film without generating active hydrogen. The resin having a photosensitive polyimide structure is a resin having photosensitivity such as a property of completing the polyimide structure mainly by ultraviolet rays and solidifying.
【００１０】樹脂被膜は、スピンコートによって塗布さ
れることが可能であり、回転するプレートに基板を固定
したうえで回転し、樹脂溶剤を表面に滴下することによ
って膜を塗布することができる。また、樹脂成分を霧上
に基板に吹き付けて塗布することもでき、ノズルから樹
脂成分を基板表面に吹き付けながら乾燥さてゆくことが
できる。この場合、ごく表面部分だけを乾燥させること
により、乾燥時の樹脂の収縮による応力の蓄積を最小限
にとどめることができる。The resin film can be applied by spin coating, and the film can be applied by fixing the substrate on a rotating plate and then rotating and dropping a resin solvent on the surface. Alternatively, the resin component can be sprayed onto the substrate to be sprayed, and the resin component can be dried while being sprayed onto the substrate surface from the nozzle. In this case, by only drying the surface portion, the accumulation of stress due to the shrinkage of the resin during drying can be minimized.
【００１１】[0011]
【作用】従来酸化シリコン、窒化シリコン保護膜形成後
に、強誘電体の自発分極低下などの劣化現象が見られた
のに対し、本発明によれば、保護膜形成時に水素が発生
することが少なく強誘電体の劣化も最小限にとどめるこ
とができる。In contrast to the conventional deterioration phenomenon such as a decrease in spontaneous polarization of the ferroelectric substance, which was observed after the formation of the protective film of silicon oxide or silicon nitride, according to the present invention, hydrogen is less likely to be generated during the formation of the protective film. The deterioration of the ferroelectric can be minimized.
【００１２】[0012]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。Embodiments of the present invention will be described below with reference to the drawings.
【００１３】[0013]
【実施例１】まず、図１に示すように、Ｓｉ単結晶基板
１上に、ＭＯＳ−ＦＥＴ６が形成され、白金電極３およ
びＰｂＺｒＴｉＯ3 強誘電体薄膜４からなるキャパシタ
が形成される。これに、図２に示すように窒化Ｓｉの保
護膜７をコーティングしたものと、ポリイミド保護膜８
をコーティングしたものを作成した。Example 1 First, as shown in FIG. 1, a MOS-FET 6 is formed on a Si single crystal substrate 1, and a capacitor composed of a platinum electrode 3 and a PbZrTiO 3 ferroelectric thin film 4 is formed. This is coated with a Si nitride protective film 7 as shown in FIG. 2 and a polyimide protective film 8
Was coated.
【００１４】窒化Ｓｉ膜は、基板温度約３００度、ソー
スガスにアンモニア、モノシラン、窒素を用い、圧力約
１ＴｏｒｒにおいてプラズマＣＶＤにより成膜した。こ
れらにコンタクトホールを開けるために、フォトリソグ
ラフィーとドライエッチにより加工した。ポリイミド樹
脂としてエステルボンドタイプの樹脂を塗布し、紫外線
照射によりコンタクトホール以外の部分を固化させ、現
像、３５０度のキュアリングにより仕上げた。The Si nitride film was formed by plasma CVD at a substrate temperature of about 300 ° C., using ammonia, monosilane, and nitrogen as a source gas at a pressure of about 1 Torr. In order to open contact holes in these, processing was performed by photolithography and dry etching. An ester bond type resin was applied as the polyimide resin, the portions other than the contact holes were solidified by irradiation with ultraviolet rays, and development and curing at 350 degrees were performed.
【００１５】このサンプルのキャパシタ部分を用い、強
誘電体の自発分極をプロービングにより測定した。窒化
Ｓｉによる保護膜を形成したものは、自発分極約５マイ
クロクーロン／ｃｍ2 であるが、ポリイミド樹脂による
保護膜を形成したものは自発分極約２０マイクロクーロ
ン／ｃｍ2 となり、ポリイミド樹脂を保護膜に用いたも
のは、明らかに強誘電体の劣化を抑制した。Using the capacitor portion of this sample, the spontaneous polarization of the ferroelectric substance was measured by probing. A protective film formed of Si nitride has a spontaneous polarization of about 5 microcoulombs / cm 2 , whereas a protective film formed of a polyimide resin has a spontaneous polarization of about 20 microcoulombs / cm 2 , and the polyimide resin is a protective film. The material used in Example 1 clearly suppressed the deterioration of the ferroelectric substance.
【００１６】[0016]
【実施例２】まず、図３に示すように、Ｓｉ単結晶基板
９上に強誘電体ＰｂＺｒＴｉＯ3 とＣｅＯ2 バッファ膜
からなるゲート１２を形成し、導電層１３を形成し、ソ
ース１０とドレイン１１を形成して、ＭＦＩＳ−ＦＥＴ
を備えたサンプルを用意した。Example 2 First, as shown in FIG. 3, a gate 12 made of a ferroelectric PbZrTiO 3 and CeO 2 buffer film is formed on a Si single crystal substrate 9, a conductive layer 13 is formed, and a source 10 and a drain are formed. 11 to form MFIS-FET
A sample provided with was prepared.
【００１７】これに、図４に示すように窒化Ｓｉ層間絶
縁膜１４を形成したものとポリイミド樹脂層間絶縁膜１
５をコーティングしたものを作成した。窒化Ｓｉ膜は、
基板温度約３００度、ソースガスにアンモニア、モノシ
ラン、窒素を用い、圧力約１Ｔｏｒｒにおいてプラズマ
ＣＶＤにより成膜した。これにコンタクトホールを開け
るため、フォトリソグラフィーとドライエッチにより加
工した。ポリイミド樹脂としてエステルボンドタイプの
樹脂を塗布し、紫外線照射によりコンタクトホール以外
の部分を固化させ、現像、３５０度のキュアリングによ
り仕上げた。On this, a silicon nitride interlayer insulating film 14 is formed as shown in FIG.
5 was coated. The Si nitride film is
A film was formed by plasma CVD at a substrate temperature of about 300 ° C., using ammonia, monosilane, and nitrogen as a source gas at a pressure of about 1 Torr. In order to open a contact hole in this, processing was performed by photolithography and dry etching. An ester bond type resin was applied as the polyimide resin, the portions other than the contact holes were solidified by irradiation with ultraviolet rays, and development and curing at 350 degrees were performed.
【００１８】このサンプルに図５に示すような配線を行
い、ドレイン電圧の経時変化を測定した。窒化Ｓｉによ
る保護膜を形成したサンプルは、５ボルトの電圧が約６
分で４ボルトに低下したのに対し、ポリイミド樹脂によ
る保護膜を形成したサンプルは、１週間経っても全く電
圧の低下は観測できなかった。ポリイミド樹脂を保護膜
に用いたものは、明らかに強誘電体の劣化を抑制したこ
とが分かった。Wiring as shown in FIG. 5 was conducted on this sample, and the change with time of the drain voltage was measured. The sample with the protective film made of Si nitride has a voltage of 5 V of about 6
While the voltage dropped to 4 volts in a minute, in the sample having the protective film formed of the polyimide resin, no voltage drop was observed even after 1 week. It was found that the one using the polyimide resin as the protective film obviously suppressed the deterioration of the ferroelectric substance.
【００１９】[0019]
【発明の効果】本発明によれば、保護膜形成時に水素が
発生することが少ないため強誘電体の劣化が少ないとい
う効果を有する。According to the present invention, since hydrogen is less likely to be generated when the protective film is formed, the ferroelectric substance is less deteriorated.
【図１】ＭＯＳ−ＦＥＴと強誘電体を用いたキャパシタ
とからなる記憶素子の断面図である。FIG. 1 is a cross-sectional view of a memory element including a MOS-FET and a capacitor using a ferroelectric substance.
【図２】図１の記憶素子に窒化Ｓｉの保護膜を施したも
のと、ポリイミド保護膜を施したものを示す断面図であ
る。。FIG. 2 is a cross-sectional view showing the memory element of FIG. 1 provided with a protective film of Si nitride and the one provided with a polyimide protective film. .
【図３】ゲート部分に強誘電体とバッファ膜を備えたＭ
ＯＳ−ＦＥＴからなる記憶素子の断面図である。FIG. 3 is an M having a ferroelectric film and a buffer film in the gate portion.
It is sectional drawing of the memory element which consists of OS-FET.
【図４】図４の記憶素子に窒化Ｓｉの保護膜を施したも
のと、ポリイミド保護膜を施したものを示す断面図であ
る。FIG. 4 is a cross-sectional view showing a memory element of FIG. 4 provided with a protective film of Si nitride and a memory element of FIG. 4 provided with a polyimide protective film.
【図５】記憶保持時間測定回路を示す。FIG. 5 shows a memory retention time measurement circuit.
１ ｎ型Ｓｉ単結晶基板 ２ Ｓｉ酸化物薄膜 ３ 白金電極 ４ ＰｂＺｒＴｉＯ3 薄膜 ５ 多結晶Ｓｉゲート電極 ６ ゲート酸化膜 ７ 窒化Ｓｉ層間絶縁膜 ８ ポリイミド樹脂層間絶縁膜 ９ ｎ型Ｓｉ単結晶基板 １０ ソース １１ ドレイン １２ ＣｅＯ2 バッファ膜 １３ ＰｂＴｉＯ3 薄膜 １４ 窒化Ｓｉ層間絶縁膜 １５ ポリイミド樹脂層間絶縁膜 １６ アルミニウム電極1 n-type Si single crystal substrate 2 Si oxide thin film 3 platinum electrode 4 PbZrTiO 3 thin film 5 polycrystalline Si gate electrode 6 gate oxide film 7 nitrided Si interlayer insulating film 8 polyimide resin interlayer insulating film 9 n-type Si single crystal substrate 10 source 11 Drain 12 CeO 2 buffer film 13 PbTiO 3 thin film 14 Si nitride interlayer insulating film 15 Polyimide resin interlayer insulating film 16 Aluminum electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/788 29/792 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 29/788 29/792
Claims (4)
いたキャパシタからなる記憶素子、またはゲート絶縁膜
部分に強誘電体を有するＭＯＳトランジスタからなる記
憶素子がＳｉ単結晶基板上に形成された強誘電体記憶素
子において、前記記憶素子を保護するかまたは配線と分
離する絶縁膜が樹脂被膜であることを特徴とする強誘電
体記憶素子。1. A ferroelectric material in which a memory element including a MOS transistor and a capacitor using a ferroelectric substance, or a memory element including a MOS transistor having a ferroelectric substance in a gate insulating film portion is formed on a Si single crystal substrate. A ferroelectric memory element, wherein in the memory element, an insulating film that protects the memory element or separates from the wiring is a resin film.
ＴｉＯ3 またはＰｂＬａＺｒＴｉＯ3 からなることを特
徴とする請求項１に記載の強誘電体記憶素子。2. The ferroelectric material is PbTiO 3 or PbZr.
The ferroelectric memory element according to claim 1, which is made of TiO 3 or PbLaZrTiO 3 .
樹脂であることを特徴とする請求項１または２に記載の
強誘電体記憶素子。3. The ferroelectric memory element according to claim 1, wherein the resin film is a resin having a polyimide structure.
性であることを特徴とする請求項３に記載の強誘電体記
憶素子。4. The ferroelectric memory element according to claim 3, wherein the resin having a polyimide structure is photosensitive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7064019A JPH08264522A (en) | 1995-03-23 | 1995-03-23 | Ferroelectric memory element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7064019A JPH08264522A (en) | 1995-03-23 | 1995-03-23 | Ferroelectric memory element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08264522A true JPH08264522A (en) | 1996-10-11 |
Family
ID=13246039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7064019A Withdrawn JPH08264522A (en) | 1995-03-23 | 1995-03-23 | Ferroelectric memory element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08264522A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6709991B1 (en) | 1997-05-23 | 2004-03-23 | Nec Corporation | Method of fabricating semiconductor device with capacitor |
| US6812083B2 (en) * | 2002-12-18 | 2004-11-02 | Ememory Technology Inc. | Fabrication method for non-volatile memory |
| US9647200B1 (en) | 2015-12-07 | 2017-05-09 | International Business Machines Corporation | Encapsulation of magnetic tunnel junction structures in organic photopatternable dielectric material |
-
1995
- 1995-03-23 JP JP7064019A patent/JPH08264522A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6709991B1 (en) | 1997-05-23 | 2004-03-23 | Nec Corporation | Method of fabricating semiconductor device with capacitor |
| US6812083B2 (en) * | 2002-12-18 | 2004-11-02 | Ememory Technology Inc. | Fabrication method for non-volatile memory |
| US9647200B1 (en) | 2015-12-07 | 2017-05-09 | International Business Machines Corporation | Encapsulation of magnetic tunnel junction structures in organic photopatternable dielectric material |
| US10002904B2 (en) | 2015-12-07 | 2018-06-19 | International Business Machines Corporation | Encapsulation of magnetic tunnel junction structures in organic photopatternable dielectric material |
| US10008536B2 (en) | 2015-12-07 | 2018-06-26 | International Business Machines Corporation | Encapsulation of magnetic tunnel junction structures in organic photopatternable dielectric material |
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