JPH08263995A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To shorten a test time and to enable performing more severe test by operating externally an internal signal of a DRAM in the case of testing writing margin of a memory cell and the like. CONSTITUTION: A writing control signal-W, strobe signals-RAS,-CAS of a row address and a column address are given to a-TE generator externally, and a test mode signal-TE is generated. The signal-TE is inputted to a data input buffer 8A, an internal writing control signal WDE is generated, writing data is taken from a terminal DQ1-4 , and the signal is written in a memory cell 4 through an I/O equalizing circuit 11 and an input/output control circuit 5. In a normal mode, a signal WDE having the prescribed pulse width is generated by a signal-WE, but in a test mode, a signal WDE having a short pulse width corresponding to an external signal-W is generated. Thereby, a test time can be shortened and a severe test can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, for example, when performing a test for rejecting a DRAM having a small write margin, the DR
The present invention relates to a circuit for externally operating an internal signal of AM.

[0002]

2. Description of the Related Art FIG. 10 is a schematic block diagram showing a signal flow in an example of a conventional dynamic random access memory (hereinafter referred to as DRAM). In FIG. 10, signals designating addresses inputted from a plurality of address input terminals A0 to A9 are respectively inputted to the address buffer 1, and the address buffer 1 has the column decoder 2
And the address input terminals A0 to the row decoder 3
Signals indicating the word line and bit line of the address of the memory cell 4 are output from the A0 to A9 signals input from A9 to A9.

Row decoder 3 is an internal clock signal α (hereinafter referred to as α signal) which is a signal for controlling the timing of activating the word line and bit line of memory cell 4.
Is input from the clock generation circuit 6, the word line WL indicated by the signal input from the address buffer 1 is activated. Further, the column decoder 2 activates the bit line BL indicated by the signal input from the address buffer 1 via the sense refresh amplifier input / output control circuit 5 when the α signal is input from the clock generation circuit 6. The column decoder 2 and the row decoder 3 activate the bit line and the word line of the memory cell 4 when the α signal is “H”.

The clock generation circuit 6 is a signal for activating the α signal, and is a row address strobe signal sent from an external circuit at the timing when the write operation to the memory cell 4 is to be started. / RAS
External input terminal / RAS (hereinafter, / RA
S terminal), and an external input terminal / CAS (hereinafter, / CAS) to which an external / CAS signal which is a column address strobe signal sent from an external circuit is input at the timing when the write operation to the memory cell 4 is desired to start. Called terminals) are connected respectively.

Further, the clock generation circuit 6 is connected to the / WE generation circuit 7, and the / WE generation circuit 7 writes a write signal (hereinafter referred to as a write signal) for setting a write operation for writing to a memory cell at a specified address. External / W signal)
Is connected to an external input terminal / W (hereinafter, referred to as / W terminal). It should be noted that the external / W signal becomes "L" when it is set in the write operation, and becomes "H" otherwise.

The / WE generating circuit 7 is further connected to the data input buffer 8 and to the memory cell 4 of the signal data input from the external input / output terminals DQ1, DQ2, DQ3, DQ4 connected to the data input buffer 8. Controls writing of the / WE signal. The clock generation circuit 6 further includes an address buffer 1 and an ATD generation circuit 1.
0, and the ATD generation circuit 10 is further connected to the address buffer 1 and the I / O equalization circuit 11. The data input buffer 8 is connected to the data output buffer 9 by an I / O composed of a pair of I / O lines, an I / O line and an / I / O line.
The I / O is connected to the sense refresh amplifier input / output control circuit 5 through the O equalizer circuit 11. The acronym / of the above-mentioned / I / O line means the inversion of the signal level.

When the ATD generation circuit 10 detects a change in an address designated by the A0 to A9 signals input from the address buffer 1, it generates an ATD signal (not shown) which is a pulse signal generated internally. Let the AT
The / IOEQ signal which is a signal for controlling the execution of equalization is output to the I / O equalize circuit 11 by using the D signal. The I / O equalizer circuit 11 is
It is a circuit for equalizing the I / O line and the / I / O line by the OEQ signal.

FIG. 11 shows the I / O equalizer circuit 11 described above.
FIG. 12 is a diagram showing an example of the circuit of FIG. 11. In FIG. 11, the I / O equalizer circuit 11 is composed of one transfer gate 15 and one inverter circuit 16, and the I / O line is output by both outputs of the transfer gate 15. And / I / O line are connected, and one control input 15a of the transfer gate 15 and the input of the inverter circuit 16 are connected to the ATD generation circuit 1
0, and the output of the inverter circuit 16 is connected to the other control input 15b of the transfer gate 15.

When the / IOEQ signal of "L" is input from the ATD generating circuit 10 to the control input 15a of the transfer gate 15 and the input of the inverter circuit 16, the output of the transfer gate 15 becomes conductive and I / I / O
Lines and / I / O lines are equalized. Similarly, ATD
When the generation circuit 10 outputs the "H" / IOEQ signal, the output of the transfer gate 15 is cut off, and the I / O line and the / I / O line are not equalized.

Next, referring to FIG. 10, when the data output buffer 9 is further connected to the external input terminal / OE and an output enable signal (hereinafter referred to as "/ OE signal") is inputted from the terminal, the data output buffer 9 is outputted. The signal data stored in the memory cell 4 is read from the external input / output terminals DQ1 to DQ4 connected to 9. As described above, signals such as row address designation data input / output, column address designation data input / output, and equalization control are all input / output by the α signal which is the internal clock signal from the clock generation circuit 6.

The / RAS terminal, the / CAS terminal, and the / W terminal are connected to the / TE generating circuit 12, and the / TE generating circuit 12 outputs the external / CAS signal and the external / W signal. When each is “L”, external /
DR at the timing of WCBR when the RAS signal falls
The / TE signal of "L"("H" in the normal mode) which is a signal for setting the AM 13 in the test mode is output to a predetermined location.

In the DRAM 13 having the above structure, the "L" external / RAS signal and the "L" external / CA signal are output.
When the S signal is input to the clock generating circuit 6, the clock generating circuit 6 outputs the α signal to the column decoder 2 and the row decoder 3. The column decoder 2 activates the bit line BL of the address of the memory cell 4 indicated by the signal input from the address buffer 1 via the sense refresh amplifier input / output control circuit 5, and the row decoder 3 operates as an address buffer. The word line WL of the address of the memory cell 4 indicated by the signal input from 1 is activated.

Further, the "H" α signal output from the clock generation circuit 6 is input to the / WE generation circuit 7, and the binary level of the external / W signal is output from the output of the / WE generation circuit 7. The signal of the same level as is output. Here, when the external / W signal of "L" for setting the write operation is input to the / WE generation circuit 7, the / WE signal of "L" is input to the data input buffer 8 and the data input The buffer 8 starts a write operation. As a result, the signal data input from the external input / output terminals DQ1 to DQ4 is transferred from the data input buffer 8 to the column decoder 2 and the row decoder 3 via the I / O equalizer circuit 11 and the sense refresh amplifier input / output control circuit 5. It is written in the memory cell 4 of the activated address.

Now, the operation of the data input buffer 8 during the write operation will be described in more detail. FIG. 12 is a schematic block diagram showing a conventional example of the data input buffer 8. In FIG. 12, the data input buffer 8 is a WDE which is an internal WE signal from the / WE signal from the / WE generation circuit 7. WD that generates and outputs signals
An E generation circuit 17, a data input buffer section 18 which takes in signal data inputted from the external input / output terminals DQ1 to DQ4, converts the signal data into a WD signal which can be written in the memory cell 4 and outputs the WD signal, and the WDE signal. Write driver 19 for controlling the output of the WD signal to the sense refresh amplifier input / output control circuit 5 according to the binary level of
Consists of

The WDE generating circuit 17 and the data input buffer section 18 are connected to the / WE generating circuit 7, the write driver 19 is connected to the WDE generating circuit 17 and the data input buffer section 18, and further the I / O equalizing circuit. 1
1 through the sense refresh amplifier input / output control circuit 5
It is connected to the. When the "H" signal is input from the / WE generation circuit 7, the WDE generation circuit 17 outputs the corresponding WDE signal to the write driver 19, and the data input buffer section 18 causes the external input / output terminals DQ1 to DQ4.
The signal data is taken in from and the WD signal is output to the write driver 19. When the WDE signal from the WDE generation circuit 17 indicates write permission, the write driver 19 passes the WD signal through the I / O equalization circuit 11 through the I / O to the sense refresh amplifier input / output control circuit 5 Output to.

FIG. 13 is a circuit diagram showing an example of the circuit of the write driver 19 described above. In FIG. 13, the write driver 19 includes two n-channel type MOS transistors (hereinafter referred to as nMOS transistors) 20 and 21. 1
The nMOS transistors 20 and 21 are connected to each other at their gates, and the connection is connected to the WDE generation circuit 17. Also, nMO
The drain of the S transistor 20 is connected to the data input buffer unit 18, the drain of the nMOS transistor 21 is connected to the output of the inverter circuit 22, and the input of the inverter circuit 22 is connected to the drain of the nMOS transistor 20. Further, the source of the nMOS transistor 20 is connected to the I / O line of I / O, and the source of the nMOS transistor 21 is connected to the / I / O line of I / O.

In the write driver 19, when a WDE signal of "H" is input from the WDE generating circuit 17 to both gates of the nMOS transistors 20 and 21 during the write operation, both nMOS transistors 20 and 21 are turned on,
The WD signal input from the data input buffer unit 18 is
to the I / O line of the I / O via the nMOS transistor 20
It outputs to the / I / O line of I / O via the inverter circuit 22 and the nMOS transistor 21.

FIG. 14 is a circuit diagram showing a circuit example of the WDE generating circuit 17, and in FIG. 14, the WDE generating circuit 17 includes twelve inverter circuits 30, 31, 32,
33, 34, 35, 36, 37, 38, 39, 40, 4
One and two NAND circuits 42 and 43 and one delay circuit 4
4 and the inverter circuit 30 has an inverter circuit 3
1 are connected in series in the same direction, the input of the inverter circuit 30 forming the series circuit is connected to the output of the NAND circuit 42, and the output of the inverter circuit 31 is NAN.
It is connected to one input of the D circuit 43.

The inverter circuit 32 is provided with an inverter circuit 33, and the inverter circuit 33 is provided with an inverter circuit 34.
However, an inverter circuit 35 is connected to the inverter circuit 34, an inverter circuit 36 is connected to the inverter circuit 35 in series in the same direction, and an input of an inverter circuit 32 forming the series circuit is connected to an output of the NAND circuit 43. ,
The output of the inverter circuit 36 is the write driver 1
9 is connected.

Further, the inverter circuit 37 is provided with an inverter circuit 38, the inverter circuit 38 is provided with an inverter circuit 39, and the inverter circuit 39 is provided with an inverter circuit 40.
Is connected in series to the inverter circuit 40 in the same direction, the input of the inverter circuit 37 forming the series circuit is connected to the connection portion of the inverter circuits 32 and 33, and the output of the inverter circuit 41. Is connected to one input of the NAND circuit 42. The other input of the NAND circuit 42 is connected to the / WE generating circuit 7.

Further, the input of the delay circuit 44 is connected to the connection portion of the inverter circuits 35 and 36, and the output of the delay circuit 44 is further connected to the other input of the NAND circuit 43. Here, the connection between the output of the inverter circuit 41 and the input of the NAND circuit 42 is a node A, the connection between the delay circuit 44 and the input of the NAND circuit 43 is a node B, and the output of the inverter circuit 31 and the NA are
The above-mentioned connection with the input of the ND circuit 43 is referred to as a node C.

FIG. 15 is a timing chart of the circuit shown in FIG. A in FIG.
B and C show timing charts of signals at the nodes A, B, and C in FIG. In FIG. 15, when the node A is "H" and the / WE signal is switched from "H" to "L", the NAND circuit 42,
The node C switches from “L” to “H” with a delay of a delay time obtained by adding the delay times respectively generated by the inverter circuit 30 and the inverter circuit 31. Further, if the node B is "H" at this time, the node A is delayed by a delay time obtained by adding the delay times respectively generated by the NAND circuit 43 and the inverter circuits 32, 37, 38, 39, 40, 41. Changes from "L" to NA
ND circuit 43 and inverter circuits 32, 33, 34, 3
The WDE signal is switched from "L" to "H" with a delay of a delay time obtained by adding the delay times caused by 5 and 36.

When the node B is "H", the node C
Is switched from "L" to "H", the NAND circuit 4
3, the node B switches from “H” to “L” with a delay time that is the sum of the delay times generated by the inverter circuits 32, 33, 34, 35 and the delay circuit 44, whereby the node A is connected to the NAND circuit. 43 and the inverter circuits 32, 37, 38, 39, 40, 41 are switched from "L" to "H" with a delay time caused by the delay time, and the WDE signal changes the NAND circuit 43 and the inverter circuits 32, 33, 34, 35, Switching from “H” to “L” is delayed by the delay time caused by 36.

As can be seen from FIGS. 14 and 15, WD
The E signal is generated only when the / WE signal from the / WE generation circuit 7 and the binary level of the external / W signal are switched.
The binary level is switched with a delay of a predetermined delay time set by the WE generation circuit 7. In this way, when tRWL is sufficiently long, the pulse width of the WDE signal is set to the WDE generation circuit 1
Made inside the 7 device.

FIG. 16 is a circuit diagram showing a circuit example of the ATD generating circuit 10. In FIG. 16, the ATD generating circuit 10 has three NAND circuits 70, 71, 72 and 7.
Two inverter circuits 73, 74, 75, 76, 77, 7
8, 79, one nMOS transistor 81, and one p-channel type MOS transistor (hereinafter referred to as pMOS
82) and two capacitors 83,
And 84. The NAND circuits 70 and 71 form an RS flip-flop circuit, the output of the NAND circuit 70 is connected to one input of the NAND circuit 72, and the capacitor 83 is connected between the connection portion and the ground. Furthermore, NAN
The output of the D circuit 71 is connected to the other input of the NAND circuit 72, and the capacitor 84 is connected between the connection and the ground.

The output of the NAND circuit 72 is connected to the input of the inverter circuit 73, and the output of the inverter circuit 73 is connected to the gate of the nMOS transistor 81. The source of the nMOS transistor 81 is grounded, the drain of the nMOS transistor 81 is connected to the drain of the pMOS transistor 82, and the source of the pMOS transistor 82 is connected to the VCC terminal. The output of the inverter circuit 74 is input to the inverter circuit 75, and the output of the inverter circuit 75 is the inverter circuit 76.
To form a series circuit, the input of the inverter circuit 74 is connected to the connection of both drains of the nMOS transistor 81 and the pMOS transistor 82, and the ATD signal is output from the output of the inverter circuit 76.

Further, the output of the inverter circuit 77 is connected to the input of the inverter circuit 78 and the output of the inverter circuit 78 is connected to the input of the inverter circuit 79 to form a series circuit, and the input of the inverter circuit 77 is the inverter circuit. The output of the inverter circuit 79 is connected to the connection between the output of the inverter circuit 74 and the input of the inverter circuit 75.
It is connected to the gate of the OS transistor 82.

The ATD generation circuit 10 is the same as the NAN.
There are D circuits 70, 71, 72, inverter circuits 73, and capacitors 83, 84 in a number corresponding to the number of address input terminals, and each output signal from the inverter circuit 73 of each circuit is predetermined. Process n
It is inputted to the input of the MOS transistor 81, but here, for simplification of explanation, one An (n is 0 to n corresponding to any one terminal from the address input terminals A0 to A9 in this example) is inputted. An explanation will be given only for the case of a circuit for signals (integer up to 9). An signal from the address buffer 1 is applied to one input of the NAND circuit 70 as the NAN signal.
An inverted signal / An signal obtained by inverting the signal level of the An signal is input to one input of the D circuit 71.

FIG. 17 is a timing chart of the circuit shown in FIG. Φ in FIG. 17 is
FIG. 17 shows a timing chart of signals at a node φ which is a connecting portion between the output of the inverter circuit 73 and the gate of the nMOS transistor 81 in FIG. In FIG. 17, when the An signal is switched from “H” to “L”, / An
The signal switches from "L" to "H". Here, while the potential charged in the capacitor 83 is discharged by the potential, both inputs of the NAND circuit 72 become “H”, and the node φ has a delay time generated by the NAND circuits 70, 71, 72 and the inverter circuit 73. The pulse signal of "H" is generated with a delay. Furthermore, nMOS transistors 81, p
MOS transistor 82 and inverter circuits 74, 7
The ATD signal of the pulse signal of "H" is output with a delay of the delay time caused by 5, 76, 77, 78, 79.

Conventionally, in a semiconductor device such as a DRAM as described above, one of the most important tests for rejecting a semiconductor integrated circuit having a small write margin is a timing at which a write or read operation to a memory cell is started. "L" in the external / RAS signal of the down edge sent from the external circuit to
TRAS, which is the time that indicates the width of the
(g tRAS) together with shortening tRWL, which is the time from the fall of the external / W signal to the rise of the external / RAS signal for setting the memory cell at the specified address for the write operation (hereinafter, short tRWL).
There is a test.

FIG. 18 is a circuit diagram showing a structural example of the memory cell 4 of the DRAM 13 shown in FIG. 10. In FIG. 18, the gate of the transfer gate 100 is connected to the word line WL. The drain of 100 is connected to the bit line BL, and the source of the transfer gate 100 is connected to the memory cell capacitance C. If the signal flowing through the word line WL is the WL signal,
When the external / W signal is "L" and the WL signal is "H", data is written in the memory cell.

Here, for example, when the word line WL has a defect of high resistance and is short-circuited to the ground (VSS), the signal level of the WL signal is gradually lowered by setting Long tRAS. As a result, the transfer gate 100
Gate voltage drops. Further, when Short tRWL is set, the pulse width of the WDE signal shown in FIG. 15 becomes narrower,
Since the time for applying the data signal to the bit line BL in FIG. 18 becomes short, the above Long tRAS and Short
Due to the two effects of tRWL, the charge stored in the memory cell capacitance C is reduced to reject a memory cell with a small write margin.

The ATD generating circuit 10 in the DRAM 13 is different from the I / O equalizing circuit 11 in the I / O.
Is attempted to speed up the operation before the operation. However, if the equalization is not sufficient, invalid data is generated and access is slowed down. Further, the series of operations in which the ATD signal width is narrowed and equalization is insufficient and invalid data is generated. Address noise in which wrong data is output unless the α signal from the clock generation circuit 6 is matched. Occurs.
Therefore, as a method for testing the access speed of the DRAM 13 and the generation of address noise, the pulse width of the ATD signal is narrowed to reject those with a low access speed and those with address noise.

[0034]

FIG. 19 shows the DR shown in FIG. 10, FIG. 11, FIG. 12, FIG. 13, FIG. 14 and FIG.
FIG. 9 is a timing chart of each signal during a write operation of AM13. As shown in FIG. 19, since the above-mentioned write operation is writing of 1-bit signal data in one cycle, in order to shorten the pulse width of the WDE signal as described above, in order to shorten the pulse width of the WDE signal, one bit at a time is set for each tRWL. There is a problem that the external / RAS signal must be raised from "L" to "H" and the test must be performed bit by bit in the long cycle as described above, resulting in a very long test time. .

Therefore, in the state where the external / RAS signal is kept low from "H" to "L", the external / CAS signal is input as a clock to set the page mode for accessing the data on the same row address. Use the above Long
A method for shortening the test time has been considered by conducting a test of tRAS and the above Short tRWL. However, FIG. 20 shows FIG. 10, FIG. 11, FIG. 12, FIG.
20 is a timing chart of each signal during the write operation in the page mode of the DRAM 13 shown in FIG. 4 and FIG. 15, but as shown in FIG. 20, tRWL becomes longer in the page mode and the WDE signal becomes the WDE generating circuit. Since the pulse width is automatically determined at 17, Sh
There was a problem that it was not a test of ort tRWL.

The pulse width of the ATD signal generated by the conventional ATD generation circuit 10 is set by the ATD generation circuit 10, and the width of the ATD signal is narrowed to test the access speed of the DRAM. In this case, even in a normal operation other than the test, the width of the ATD signal remains thin, and the ATD signal width is narrowed and equalization is insufficient, and a series of operations such that invalid data is generated. There is a problem that wrong data is output unless the α signal from the clock generation circuit 6 is matched. Conversely, when the ATD signal width is widened, the cell data is destroyed by connecting to the bit line while being equalized. There was a problem.

The present invention has been made in order to solve the above problems, and obtains a semiconductor integrated circuit capable of shortening the test time and conducting more rigorous tests in testing semiconductor devices. Is.

[0038]

According to the present invention, a first internal signal generating and outputting a predetermined first internal signal in response to a state change of a binary first external signal input from a first external terminal. In a semiconductor integrated circuit having signal output means, when a predetermined signal is input to a second external terminal including at least one external terminal, the binary state is changed to indicate that the predetermined signal has been input. A semiconductor integrated circuit comprising a second internal signal output means for generating a second internal signal and outputting the second internal signal to the first internal signal output means.

In the invention according to claim 2 of the present application, the second internal signal output means according to claim 1 is set to the test mode when a predetermined signal is input to the second external terminal. It is characterized in that it is a test mode signal output means for generating a test mode signal for changing a binary state for starting and outputting it to the first internal signal output means.

The invention according to claim 3 of the present application corresponds to the change of the state of the write enable signal for changing the binary state so as to start the write operation inputted from the first external terminal. In the semiconductor integrated circuit in the DRAM which operates in the page mode, the second external terminal including at least one external terminal is provided with a predetermined first internal signal output means for generating and outputting a predetermined first internal signal. When a signal is input, a test mode signal output means for generating a test mode signal for changing a binary state to start the test mode and outputting it to the first internal signal output means is provided. A semiconductor integrated circuit in a DRAM is provided.

The invention according to claim 4 of the present application generates a predetermined first internal signal in response to a state change of a binary first external signal input from a first external terminal. In a semiconductor integrated circuit having a first internal signal output means for outputting as a predetermined signal, when a predetermined signal is input to a second external terminal including at least one external terminal, the binary state is changed and the predetermined signal is changed. A second internal signal output means for generating a second internal signal indicating that it has been input and outputting it to the first internal signal output means, and a third external signal input to the first internal signal output means are input. A semiconductor integrated circuit having a third external terminal is provided.

In the invention described in claim 5 of the present application, the second internal signal output means of claim 4 is set to the test mode when a predetermined signal is input to the second external terminal. It is characterized in that it is a test mode signal output means for generating a test mode signal for changing a binary state for starting and outputting it to the first internal signal output means.

According to a sixth aspect of the present invention, a predetermined first number corresponding to a binary state change of an address designation signal input from a first external terminal including at least one external terminal is provided. In a semiconductor integrated circuit in a DRAM including a first internal signal output means for generating and outputting one internal signal, a test mode is started when a predetermined signal is input to a second external terminal including at least one external terminal. A test mode signal output means for generating a test mode signal for changing the binary state and outputting it to the first internal signal output means, and a third external signal input to the first internal signal output means are input. The present invention provides a semiconductor integrated circuit in a DRAM, which is provided with a third external terminal.

[0044]

According to the semiconductor integrated circuit of the present invention, when the predetermined signal is input to the second external terminal composed of at least one external terminal by the second internal signal output means, a binary signal is output. State is changed to generate a second internal signal indicating that the predetermined signal is input and output to the first internal signal output means, and the first internal signal output means outputs the second internal signal.
When the second internal signal input from the internal signal output means undergoes a predetermined state change, a first internal signal for performing a binary state change corresponding to the state change of the first external signal is generated and output. To do.

According to another aspect of the semiconductor integrated circuit of the present invention, when a predetermined signal is input to the second external terminal composed of at least one external terminal by the test mode signal output means, the test mode is output. A test mode signal for changing the binary state is generated and output to the first internal signal output means, and the first internal signal output means outputs the test input from the test mode signal output means. When the state is changed so that the mode signal starts the test mode, the first internal signal for changing the binary state corresponding to the state change of the first external signal is generated and output.

DRA according to claim 3 of the claims
The semiconductor integrated circuit in M is a test mode signal output means for changing a binary state in order to start a test mode when a predetermined signal is input to a second external terminal including at least one external terminal. A mode signal is generated and output to the first internal signal output means, and in the page mode operation, the test mode signal input from the test mode signal output means starts the test mode in the first internal signal output means. When the state is changed so as to be changed, the first internal signal for changing the binary state corresponding to the state change of the first external signal is generated and output using the same path as in the normal operation.

In the semiconductor integrated circuit according to claim 4 of the invention, the second internal signal output means outputs a binary signal when a predetermined signal is input to the second external terminal which is at least one external terminal. State is changed to generate a second internal signal indicating that the predetermined signal is input and output to the first internal signal output means, and a third external signal is output from the third external terminal to the first internal signal. When the second internal signal input from the second internal signal output means is input to the signal output means and the second internal signal input from the second internal signal output means changes a predetermined state, the third internal signal is output.
It generates and outputs a first internal signal for performing a binary state change corresponding to a state change of the external signal.

According to another aspect of the semiconductor integrated circuit of the present invention, in order to start the test mode when a predetermined signal is input to the second external terminal by the test mode signal output means, 2 A test mode signal for changing the state of the value is generated and output to the first internal signal output means, and the first internal signal output means outputs the test mode signal input from the test mode signal output means to the test mode. When the state is changed so as to be started, the first internal signal for changing the binary state is generated and output corresponding to the state change of the third external signal.

DRA according to claim 6 of the claims
The semiconductor integrated circuit in M is a test mode signal output means for changing a binary state in order to start a test mode when a predetermined signal is input to a second external terminal including at least one external terminal. A mode signal is generated and output to the first internal signal output means, a third external signal is input to the first internal signal output means from a third external terminal, and the test is performed by the first internal signal output means. When the test mode signal input from the mode signal output means changes the state so as to start the test mode, the first internal signal for changing the binary state corresponding to the change of the state of the third external signal is changed to the first internal signal. Generate and output.

[0050]

The present invention will now be described in detail with reference to the embodiments shown in the drawings. Example 1. 1 is a schematic block diagram of a DRAM using a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a schematic block diagram of the data input buffer shown in FIG. 1. 1 and 2, the same parts as those in the above-mentioned conventional example shown in FIGS. 10 and 12 are denoted by the same reference numerals, and here, the difference from FIGS. 10 and 12 will be described.

First, the difference from FIG. 10 in FIG. 1 is that the / TE generation circuit 12 in FIG. 10 is connected to the data input buffer 8 and accordingly the data input buffer 8A is formed. The difference between FIG. 2 and FIG. 12 is that the WDE generation circuit 17 in FIG.
The generating circuit 12 is connected, and the WDE generating circuit 1 is connected accordingly.
7 as the WDE generating circuit 17A, and the DRAM 13 as the DRA
M13A.

The WDE generating circuit 17A constitutes the first internal signal output means in claims 1 to 3, and the WD
The E signal forms the first internal signal, the / W terminal forms the first external terminal, and the external / W signal forms the first external signal or write enable signal. Further, the / TE generation circuit 12 constitutes the second internal signal output means or the test mode signal output means in claims 1 to 3, the / TE signal constitutes the second internal signal or the test mode signal, and the / RAS terminal and / CAS
The terminal and the / W terminal form the second external terminal.

In FIG. 1, the / WE generating circuit 7 is
External input / output terminals DQ1, DQ2, DQ connected to the data input buffer 8A and connected to the data input buffer 8A
3, outputs a / WE signal that controls writing of signal data input from DQ4 to the memory cell 4. The data input buffer 8A is added to the data output buffer 9 as I.
They are connected by an I / O composed of a pair of I / O lines of / O line and / I / O line, and further from the connection portion to the sense refresh amplifier input / output control circuit 5 via the I / O equalize circuit 11. It is connected by the above I / O.

The / RAS terminal, the / CAS terminal and the / W terminal are further connected to the / TE generating circuit 12, which is connected to the data input buffer 8A. When the external / CAS signal and the external / W signal are "L", the DRAM 13 is operated at the timing of WCBR when the external / RAS signal falls.
"L" which is a signal to set A to the test mode
The / TE signal ("H" in the normal mode) is output to the data input buffer 8A.

Here, the operation of the data input buffer 8A during the write operation will be described in a little more detail.
FIG. 2 is a schematic block diagram showing an example of the data input buffer 8A. In FIG. 2, the data input buffer 8A has a WDE signal which is an internal WE signal rather than the / WE signal from the / WE generation circuit 7. To generate and output
An E generation circuit 17A, a data input buffer unit 18 that takes in signal data input from the external input / output terminals DQ1 to DQ4, converts the signal data into a WD signal that can be written in the memory cell 4, and outputs the WD signal, and the WDE signal. Write driver 1 for controlling the output of the WD signal to the sense refresh amplifier input / output control circuit 5 in accordance with the binary level of
9 and 9.

The WDE generating circuit 17A and the data input buffer section 18 are connected to the / WE generating circuit 7, the write driver 19 is connected to the WDE generating circuit 17A and the data input buffer section 18, and further the I / O equalizing circuit. It is connected to the sense refresh amplifier input / output control circuit 5 via 11. When a signal of "H" is input from the / WE generation circuit 7, the WDE generation circuit 17A outputs a corresponding WDE signal to the write driver 19, and the data input buffer section 18 causes the external input / output terminal DQ1.
The signal data is taken in from DQ4 to DQ4 and the WD signal is output to the write driver 19. The write driver 19 is
When the WDE signal from the DE generation circuit 17A indicates write permission, the WD signal is output to the sense refresh amplifier input / output control circuit 5 through the I / O equalization circuit 11 and the I / O.

Next, FIG. 3 is a circuit diagram showing a circuit example of the WDE generating circuit 17A in FIG. Incidentally, in FIG. 3, the same parts as those of FIG. 14 showing the conventional example are denoted by the same reference numerals. The difference between FIG. 3 and FIG. 14 is that the inverter circuit 41 in FIG.
This is because the ND circuits 60 and 62 and one inverter circuit 61 are added.

That is, the NAND circuit 43 is connected without connecting the input on the node B side of the NAND circuit 43 and the delay circuit 44.
The output of the NAND circuit 60 is connected to the input on the node B side of the above, the output of the inverter circuit 61 is connected to one input of the NAND circuit 60, and the input of the inverter circuit 61 is connected to the delay circuit 44. , The NAND circuit 60
Is connected to the / TE generating circuit 12, the output of the inverter circuit 40 is connected to one input of the NAND circuit 62, and the output of the NAND circuit 62 is connected to the NAND circuit 42.
Connected to the input on the node A side of
The other input of is connected to the connection between the input of the NAND circuit 60 and the / TE generating circuit 12.

In FIG. 3, the WDE generating circuit 17A is
12 inverter circuits 30, 31, 32, 33, 34,
35, 36, 37, 38, 39, 40, 61 and 4 Ns
AND circuits 42, 43, 60, 62 and one delay circuit 4
4 and the inverter circuit 30 has an inverter circuit 3
1 are connected in series in the same direction, the input of the inverter circuit 30 forming the series circuit is connected to the output of the NAND circuit 42, and the output of the inverter circuit 31 is NAN.
It is connected to one input of the D circuit 43.

Further, the inverter circuit 32 is provided with an inverter circuit 33, and the inverter circuit 33 is provided with an inverter circuit 34.
However, an inverter circuit 35 is connected to the inverter circuit 34, an inverter circuit 36 is connected to the inverter circuit 35 in series in the same direction, and an input of an inverter circuit 32 forming the series circuit is connected to an output of the NAND circuit 43. ,
The output of the inverter circuit 36 is the write driver 1
9 is connected.

Further, an inverter circuit 38 is connected to the inverter circuit 37, an inverter circuit 39 is connected to the inverter circuit 38, and an inverter circuit 40 is connected to the inverter circuit 39 in series in the same direction to form the series circuit. The input of 37 is the inverter circuits 32 and 3 described above.
3, the output of the inverter circuit 40 is connected to one input of the NAND circuit 62. The other input of the NAND circuit 62 is connected to the / TE generating circuit 12, and the output of the NAND circuit 62 is NA.
It is connected to one input of the ND circuit 42, and the other input of the NAND circuit 42 is connected to the / WE generating circuit 7.

Further, the input of the delay circuit 44 is connected to the connection of the inverter circuits 35 and 36, and the output of the delay circuit 44 is connected to the input of the inverter circuit 61.
Further, the output of the inverter circuit 61 is connected to one input of the NAND circuit 60. The other input of the NAND circuit 60 is the / TE generation circuit 12 in the NAND circuit 62.
The output of the NAND circuit 60 is connected to the other input of the NAND circuit 43.
Here, the connection between the output of the NAND circuit 62 and the input of the NAND circuit 42 is referred to as a node A, and the NAND circuit 60
Is connected to the output of the NAND circuit 43 as a node B, and the output of the inverter circuit 31 and the NAND circuit 4 are connected.
The above connection with the input of 3 is designated as node C.

FIG. 4 is a timing chart in the normal mode for performing the normal operation in the circuit shown in FIG. 3, and FIG. 5 is a timing chart in the test mode for performing the test in the circuit shown in FIG. It is a figure. FIG.
5A and 5B show timing charts of signals at the node A, the node B, and the node C in FIG. 3, and first, the WDE generating circuit 1 in the normal mode is shown.
The operation of 7A will be described with reference to FIGS. 3 and 4.

In FIGS. 3 and 4, the node A is "H".
At this time, when the / WE signal is switched from "H" to "L", the node C is delayed from the "L" by a delay time obtained by adding the delay times respectively generated by the NAND circuit 42, the inverter circuit 30, and the inverter circuit 31. Switch to "H". Further, if the node B is "H" at this time, N
AND circuit 43 and inverter circuits 32, 37, 38,
When one input of the NAND circuit 62 becomes "H" and the / TE signal is set to "H" to set the normal mode, the NAND circuit 62 is delayed by a delay time obtained by adding the delay times respectively generated by 39 and 40. Both inputs are "H"
And node A switches to "L", and NAN
D circuit 43 and inverter circuits 32, 33, 34, 3
The WDE signal is switched from "L" to "H" with a delay of a delay time obtained by adding the delay times caused by 5 and 36.

When the node B is "H", the node C
Is switched from "L" to "H", the NAND circuit 60
One of the inputs is switched from "L" to "H" via the output of the inverter circuit 61, and the / TE signal is "H", the output of the NAND circuit 60 becomes "L", and the NAND circuit 43, Inverter circuits 32, 33, 3
4, 35, delay circuit 44, inverter circuit 61 and NA
The node B switches from “H” to “L” with a delay of a delay time obtained by adding the delay times generated by the ND circuit 60. As a result, the node A is connected to the NAND circuit 43,
Inverter circuits 32, 37, 38, 39, 40 and NA
“L” is delayed by the delay time generated by the ND circuit 62.
Changes to "H" and the WDE signal is NAND
Circuit 43 and inverter circuits 32, 33, 34, 35,
Switching from “H” to “L” is delayed by the delay time caused by 36.

Next, the operation of the WDE generating circuit 17A in the test mode will be described with reference to FIGS. FIG.
Further, in FIG. 5, when the / TE signal is set to "L" to enter the test mode, both the nodes A and B become "H", and when the / WE signal is switched from "H" to "L", the NAND Circuit 42, inverter circuits 30, 3
1, NAND circuit 43 and inverter circuits 32, 33,
When the WDE signal changes from “L” to “H” and the / WE signal switches from “L” to “H” with a delay of the sum of the delay times caused by 34, 35, and 36, N
AND circuit 42, inverter circuits 30, 31, NAND
Circuit 43 and inverter circuits 32, 33, 34, 35,
The WDE signal switches from "H" to "L" with a delay of the sum of the delay times caused by 36.

As described above, according to the first embodiment of the present invention, when the / TE signal is set to "H" and the normal mode is set, the WDE signal is the / WE signal from the / WE generating circuit 7.
Signal, and also when the external / W signal is switched from "H" to "L" / switched from "L" to "H" with a delay of a predetermined delay time set by the WE generation circuit 7, and further WDE generation After a predetermined time set in the circuit 17A, "H" is automatically switched to "L".

In contrast to the normal mode, FIG. 6 is a timing chart in the page mode of each signal of the DRAM 13A shown in FIG. 1 in the test mode.
When the E signal is set to “L” and the test mode is set, the WDE signal can be switched between binary levels in accordance with the binary level switching of the / WE signal.
Using the same circuit path in normal mode in two circuits, as shown in FIG. 6, Long tRAS and Short
Testing of tRWL can be done in page mode.

As is clear from the above description, in the semiconductor integrated circuit of the present invention, the WDE generating circuit in the first embodiment normally provides a predetermined pulse when there is a predetermined binary state change of the / WE signal. Outputs a pulse signal of width,
By changing the binary state of the / TE signal output from the TE generation circuit, the WDE signal having the pulse width corresponding to the pulse width of the / WE signal, that is, the pulse width of the external / W signal is WDE.
It can be output through the same path of the generation circuit. From this fact, when a semiconductor integrated circuit is tested, the internal signal of the semiconductor integrated circuit can be manipulated by a signal from the outside, so that, for example, the test time in a series of tests of Long tRAS and Short tRWL in DRAM can be reduced. It can be shortened and the test can be performed under severe conditions.

Further, as described above, the WDE generating circuit is
The WDE signal is externally / externally changed by the binary state change of the TE signal.
Since a pulse signal corresponding to the pulse width of the W signal can be obtained, a series of tests such as Long tRAS and Short tRWL in the high-speed operation mode called page mode in DRAM can be performed, and the test can be performed under severe conditions. The time can be further shortened.

Example 2. FIG. 7 is a schematic block diagram of a DRAM using the semiconductor integrated circuit of the second embodiment of the present invention. In FIG. 7, the same parts as those of FIG. Now, differences from FIG. 10 will be described. First, the difference between FIG. 7 and FIG. 10 is that the / TE generation circuit 12 in FIG.
Connected to the generation circuit, and accordingly, the ATD generation circuit 10B
Further, an external input terminal / MT (hereinafter, referred to as / MT terminal) is newly provided, and therefore, the DRAM 13 is the DRAM 13B.

The ATD generating circuit 10B constitutes the first internal signal output means in claims 4 to 6, and
The signal forms a first internal signal, the input terminals A0 to A9 form a first external terminal, and the signal designating an address input from the input terminals A0 to A9 forms a first external signal. Further above /
The TE generation circuit 12 constitutes the second internal signal output means or the test mode signal output means in claims 4 to 6, and / T
The E signal is the second internal signal or the test mode signal,
The / RAS terminal, the / CAS terminal, and the / W terminal form a second external terminal, the / MT terminal forms a third external terminal, and the / MT signal forms a third external signal.

In FIG. 7, the ATD generation circuit 10B is
It is connected to the address buffer 1, the clock generation circuit 6 and the I / O equalization circuit 11, and further has an external input terminal / M.
It is connected to the T terminal. The ATD generation circuit 10B
Detects an address change designated by the A0 to A9 signals input from the address buffer 1, generates an ATD signal (not shown) which is a pulse signal generated internally, and uses the ATD signal. The / IOEQ signal, which is a signal for controlling the execution of equalization, is output to the I / O equalizer circuit 11. The I / O equalize circuit 11 is a circuit for equalizing the I / O line and the / I / O line by the / IOEQ signal.

The I / O equalizer circuit 11 according to the second embodiment is different from the I / O equalizer circuit 11 shown in FIG. 11 in that the control input 15a of the transfer gate 15 and the input of the inverter circuit 16 are different from each other. Is ATD
It is connected to the generation circuit 10B. When the / IOEQ signal of "L" is input from the ATD generation circuit 10B to the control input 15a of the transfer gate 15 and the input of the inverter circuit 16, the output of the transfer gate 15 becomes conductive and the I / O line and / I / The O line is equalized. Similarly, when the / IOEQ signal of "H" is output from the ATD generation circuit 10B, the output of the transfer gate 15 is cut off and the I / O line and the / I / O line are not equalized.

The / RAS terminal, the / CAS terminal and the / W terminal are further connected to the / TE generating circuit 12, which is connected to the ATD generating circuit 10B. When the external / CAS signal and the external / W signal are "L", the DRAM 13B is at the timing of WCBR when the external / RAS signal falls.
"L" which is a signal to set the test mode to the test mode
AT signal (/ H in normal mode)
Output to the D generation circuit 10B.

Next, FIG. 8 is a circuit diagram showing a circuit example of the ATD generation circuit 10B in FIG. In FIG. 8, the same parts as those in FIG. 16 showing the conventional example are denoted by the same reference numerals. The difference between FIG. 8 and FIG. 16 is that four inverter circuits 90, 91, 92, and
93 and three nMOS transistors 94, 95, 96
In addition, one capacitor 97 is added.

In FIG. 8, NAND circuits 70 and 71 form an RS flip-flop circuit, and the NAND circuit 7
The output of 0 is connected to one input of the NAND circuit 72,
A capacitor 83 is connected between the connection and ground. Further, the output of the NAND circuit 71 is connected to the other input of the NAND circuit 72, and the capacitor 8 is connected between the connection portion and the ground.
4 is connected.

The output of the NAND circuit 72 is connected to the input of the inverter circuit 73, the output of the inverter circuit 73 is connected to the drain of the nMOS transistor 94, and the gate of the nMOS transistor 94 is connected to the / TE generating circuit 12. Further, the source of the nMOS transistor 94 is connected to the gate of the nMOS transistor 81. The source of the nMOS transistor 81 is grounded, the drain of the nMOS transistor 81 is connected to the drain of the pMOS transistor 82, and the source of the pMOS transistor 82 is connected to the VCC terminal.

The output of the inverter circuit 90 is connected to the input of the inverter circuit 91, the output of the inverter circuit 91 is connected to the input of the inverter circuit 92 to form a series circuit, and the input of the inverter circuit 90 is connected to the / MT terminal. ing. Further, the output of the inverter circuit 92 is connected to the drain of the nMOS transistor 95, the gate of the nMOS transistor 95 is connected to the input of the inverter circuit 93, and the input of the inverter circuit 93 is the / TE generating circuit 12.
Connected to. A capacitor 97 is provided between the connection between the output of the inverter circuit 90 and the input of the inverter circuit 91 and the ground.
And the source of the nMOS transistor 95 is connected to the connection between the gate of the nMOS transistor 81 and the source of the nMOS transistor 94, and pM
It is connected to the gate of the OS transistor 82.

The output of the inverter circuit 74 is connected to the input of the inverter circuit 75 and the output of the inverter circuit 75 is connected to the input of the inverter circuit 76 to form a series circuit, and the input of the inverter circuit 74 is connected to the nMOS transistor 81. And the drain of the pMOS transistor 82 are connected to each other, and the ATD signal is output from the output of the inverter circuit 76.

Further, the output of the inverter circuit 77 is connected to the input of the inverter circuit 78 and the output of the inverter circuit 78 is connected to the input of the inverter circuit 79 to form a series circuit, and the input of the inverter circuit 77 is the inverter circuit. It is connected to the connection between the output of 74 and the input of the inverter circuit 75. The output of the inverter circuit 79 is nMO.
It is connected to the source of the S transistor 96, and the drain of the nMOS transistor 96 is connected to the gate of the pMOS transistor 82.

In the ATD generation circuit 10B as well,
There are as many circuits as the NAND circuits 70, 71, 72, the inverter circuit 73, and the capacitors 83, 84 corresponding to the number of address input terminals, and the respective output signals from the inverter circuits 73 of the respective circuits are output. It is input to the input of the nMOS transistor 81 after performing a predetermined process, but here, in order to simplify the explanation, it corresponds to any one terminal from the address input terminals A0 to A9 in this embodiment. Only the circuit for one An (n is an integer from 0 to 9) signal will be described. NAND circuit 7
An signal from the address buffer 1 is input to one input of 0, and an inverted signal / An signal obtained by inverting the signal level of the An signal is input to one input of the NAND circuit 71.

FIG. 9 is a timing chart of the circuit shown in FIG. 8 in the test mode. Φ in FIG. 17 is the output of the inverter circuit 73 in FIG.
7 shows a timing chart of signals at a node φ which is a connection portion with the drain of the S transistor 94. In FIG. 9, when the / TE signal is set to "L" to enter the test mode, the nMOS transistor 94 of FIG.
And 96 turn off, and the nMOS transistor 95 turns on.

Therefore, regardless of the change in the binary state of the An signal and the / An signal, / M from the / MT terminal
When the T signal is switched from “H” to “L”, the nMOS transistor 81 is turned on and the pMOS transistor 82 is turned off, so that the ATD signal is switched from “L” to “H”, and When the MT signal switches from “L” to “H”, the nMOS transistor 81 turns off and the pMOS transistor 82 turns on, so that the ATD signal switches from “H” to “L”.

The timing chart of each signal in the circuit of FIG. 8 when the / TE signal is set to "H" to set the normal operation mode is shown in the nMOS transistors 94 and 96.
Is turned on and the nMOS transistor 95 is turned off, which is the same as the timing chart shown in FIG. 17 and is omitted here.

As described above, according to the second embodiment of the present invention, when the / TE signal is set to "H" and the normal mode is set, the pulse width of the ATD signal is determined by the capacitances of the capacitors 83 and 84. The delay time generated by the circuits of the nMOS transistors 94, 81 and the inverter circuits 74, 75, 76 with respect to the pulse signal of the node φ,
Alternatively, the nMOS transistors 94, 96, the pMOS transistor 82 and the inverter circuits 74, 75, 76, 7
The binary state is switched with a delay of the delay time generated by the circuits 7, 78 and 79. That is, the ATD generation circuit 10 responds to the switching of the binary state of the An signal.
The ATD signal having the pulse width set in B is automatically output.

In contrast to the normal mode, when the / TE signal is set to "L" and the test mode is set, the ATD signal is an external signal as shown in FIG.
The binary level can be switched according to the binary level switching of the MT signal, the ATD signal which is an internal signal can be manipulated using an external signal, and the setting of the ATD generation circuit in the normal mode can be performed. DRAM without change
Access speed and generation of address noise can be tested.

As described above, the ATD generating circuit in the second embodiment normally outputs a pulse signal of a predetermined pulse width when there is a predetermined binary state change of the An signal, but / T
By changing the binary state of the / TE signal output from the E generation circuit, it is possible to output an ATD signal having a pulse width corresponding to the pulse width of the / MT signal, which is an external signal. Therefore, when a test of the semiconductor integrated circuit is performed, an internal signal of the semiconductor integrated circuit can be manipulated by a signal from the outside.
The pulse width of the signal can be narrowed to perform a test for rejecting a signal with a low access speed and a signal with address noise, and the test can be performed under severe conditions.

The data input buffer, the / TE generating circuit, the ATD generating circuit, the / MT terminal and the like shown in the first and second embodiments may be used in one DRAM semiconductor integrated circuit. The present invention can be modified in various ways and is not limited to the above-mentioned embodiments. It goes without saying that the scope of the present invention should be defined by the scope of the claims. In the present specification,
/ Other than / described as I / O indicates the inversion of the signal level.

[0090]

As is apparent from the above description, according to the semiconductor integrated circuit of the present invention, the first internal signal output means is
Normally, when there is a predetermined binary state change of the first external signal, a pulse signal with a predetermined pulse width is output, but the second internal signal output means (or the test mode signal output means) outputs the second pulse signal. By changing the binary state of the internal signal (or the test mode signal), the first internal signal having the pulse width corresponding to the pulse width of the first external signal can be output through the same path of the first internal signal output means. Therefore, when the semiconductor integrated circuit is tested, the internal signal of the semiconductor integrated circuit can be manipulated by a signal from the outside, and therefore, for example, Long RAS and Short in the DRAM.
It is possible to shorten the test time in a series of tests called tRWL and perform the test under severe conditions.

Further, as described above, the first internal signal output means can change the first internal signal into a pulse signal corresponding to the pulse width of the write enable signal by changing the binary state of the test mode signal. , A series of tests such as Long tRAS and Short tRWL in the high-speed operation mode called page mode in DRAM can be performed, and the time can be further shortened while performing the tests under severe conditions.

The first internal signal output means is normally
When there is a predetermined binary state change of the first external signal (or address designation signal), the first internal signal having a predetermined pulse width is output, but the second internal signal output means (or test mode signal output means) outputs the first internal signal. By changing the binary state of the output second internal signal (or test mode signal), the first internal signal having a pulse width corresponding to the pulse width of the third external signal can be output. Therefore, when the semiconductor integrated circuit is tested, the internal signal of the semiconductor integrated circuit can be manipulated by a signal from the outside. For example, in a DRAM, the pulse width of the ATD signal can be narrowed to access the semiconductor integrated circuit. It is possible to perform a test for rejecting a slow one and an address noise, and the test can be performed under severe conditions.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a DRAM using a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram of a data input buffer 8A shown in FIG.

3 is a circuit diagram showing a circuit example of a WDE generating circuit 17A shown in FIG.

FIG. 4 is a timing chart in a normal mode in which the circuit shown in FIG. 3 performs a normal operation.

5 is a timing chart diagram in a test mode in which a test in the circuit shown in FIG. 3 is performed.

FIG. 6 is a DRA shown in FIG. 1 in a test mode.
It is a timing chart figure in page mode of each signal of M13A.

FIG. 7 is a schematic block diagram of a DRAM using a semiconductor integrated circuit according to a second embodiment of the present invention.

8 is a circuit diagram showing a circuit example of the ATD generation circuit 10B shown in FIG.

9 is a timing chart diagram in a test mode in which a test in the circuit shown in FIG. 8 is performed.

FIG. 10 is a DRA using a conventional semiconductor integrated circuit.
It is a schematic block diagram of M.

11 is an I / O equalizer circuit 11 shown in FIG.
3 is a schematic block diagram showing an example of FIG.

12 is a schematic block diagram showing an example of the data input buffer 8 shown in FIG.

13 is a circuit diagram showing a circuit example of the write driver 19 shown in FIG.

14 is a circuit diagram showing a circuit example of the WDE generating circuit 17 shown in FIG.

FIG. 15 is a timing chart of the circuit shown in FIG.

16 is a circuit diagram showing a circuit example of the ATD generation circuit 10 shown in FIG.

FIG. 17 is a timing chart of the circuit shown in FIG.

18 is a circuit diagram showing a structural example of the memory cell 4 of the DRAM 13 shown in FIG.

FIG. 19 is a plan view of FIG. 10, FIG. 11, FIG. 12, FIG.
16 is a timing chart of each signal during a write operation of the DRAM 13 shown in FIG.

FIG. 20: FIG. 10, FIG. 11, FIG. 12, FIG.
FIG. 16 is a timing chart of signals in the write operation of the DRAM 13 shown in FIG. 15 in the page mode.

[Explanation of symbols]

1 address buffer, 7 / WE generation circuit, 8, 8A
Data input buffer, 10, 10B ATD generation circuit, 12 / TE generation circuit, 13, 13A, 13B D
RAM, 17, 17A WDE generation circuit, 18 data input buffer section, 19 write driver, / RAS, /
CAS, / W, / MT, A0 to A9 External input terminals

Claims (6)

[Claims] 1. A binary first input from a first external terminal
In a semiconductor integrated circuit including first internal signal output means for generating and outputting a predetermined first internal signal in response to a change in the state of an external signal, a predetermined signal is applied to a second external terminal including at least one external terminal. And a second internal signal output means for changing the binary state to generate a second internal signal indicating that the predetermined signal has been input and outputting the second internal signal to the first internal signal output means. When the second internal signal input from the second internal signal output means changes a predetermined state, the first internal signal output means outputs a binary value corresponding to the state change of the first external signal. A semiconductor integrated circuit characterized by generating and outputting a first internal signal for changing a state. 2. The semiconductor integrated circuit according to claim 1, wherein the second internal signal output means is binary for starting a test mode when a predetermined signal is input to the second external terminal. Is a test mode signal output means for generating a test mode signal for changing the state of the test signal and outputting the test mode signal to the first internal signal output means, wherein the first internal signal output means is a test input from the test mode signal output means. When the state is changed so that the mode signal starts the test mode, the first internal signal for changing the binary state corresponding to the state change of the first external signal is generated and output. Integrated semiconductor circuit. 3. A first internal signal is generated and output in response to a state change of a write enable signal for changing a binary state so as to start a write operation input from a first external terminal. 1. In a semiconductor integrated circuit in a DRAM that includes an internal signal output unit and operates in a page mode, in order to start a test mode when a predetermined signal is input to a second external terminal including at least one external terminal. A test mode signal output means for generating a test mode signal for changing a binary state and outputting the test mode signal to the first internal signal output means is provided, and in the page mode operation, the first internal signal output means outputs the test mode signal. When the test mode signal input from the signal output means changes the state so as to start the test mode, the state change of the first external signal is performed. The semiconductor integrated circuit in a DRAM of the first internal signal, and generates and outputs with the same path as normal operation for state change of the binary corresponds to. 4. A binary first input from a first external terminal
In a semiconductor integrated circuit including first internal signal output means for generating and outputting a predetermined first internal signal in response to a change in the state of an external signal, a predetermined signal is applied to a second external terminal including at least one external terminal. Second internal signal output means which, when input, changes a binary state to generate a second internal signal indicating that the predetermined signal has been input and outputs the second internal signal to the first internal signal output means, A third external terminal to which a third external signal input to the first internal signal output means is input, wherein the first internal signal output means is a second internal signal input from the second internal signal output means. When the predetermined state change is performed, the semiconductor integrated circuit is configured to generate and output a first internal signal for performing a binary state change corresponding to the state change of the third external signal. 5. The semiconductor integrated circuit according to claim 4, wherein the second internal signal output means is a binary signal for starting a test mode when a predetermined signal is input to the second external terminal. Is a test mode signal output means for generating a test mode signal for changing the state of the test signal and outputting the test mode signal to the first internal signal output means, the first internal signal output means being the test input from the test mode signal output means When the state is changed so that the mode signal starts the test mode, the first internal signal for changing the binary state corresponding to the state change of the third external signal is generated and output. Integrated semiconductor circuit. 6. A first device comprising at least one external terminal
At least one semiconductor integrated circuit in a DRAM including a first internal signal output means for generating and outputting a predetermined first internal signal in response to a binary state change of an address designation signal input from an external terminal. When a predetermined signal is input to the second external terminal, which is an external terminal, a test mode signal for changing the binary state to start the test mode is generated and output to the first internal signal output means. A mode signal output unit and a third external terminal to which a third external signal input to the first internal signal output unit is input are provided, and the first internal signal output unit is input from the test mode signal output unit. When the state change is performed so that the test mode signal starts the test mode, the binary state change is performed corresponding to the state change of the third external signal.
DRAM characterized by generating and outputting an internal signal
Integrated circuit in.