JPH08263628A - Picture processor and picture processing system using same - Google Patents

Abstract

PURPOSE: To miniaturize a picture processing system and to facilitate construction by forming respective indispensable function modules including a picture input/output control part and a picture memory control part into one chip. CONSTITUTION: A video picture input/output part 2, the picture memory control part 3, a picture processing part 4 processing picture data, a feature extraction part 5 accumulating feature quantity from a picture processing result, a picture output part displaying picture data and a system control part 6 for designating the operation of the picture processing processor 1, all of which are functions indispensable for the picture processing system, are formed into one chip in a picture processing processor. The picture input/output part 2, the picture memory control part 3, the picture processing part 4, the feature extraction part 5 and the system control part 6 transfer control signals and data through a signal line 7. In such a case, the picture processing processor 1 can input a picture processing clock IPCLK18 in addition to a video clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processor and an image processing system using the same, and various image data processing such as filtering and feature extraction for image data taken by an image pickup device such as a TV camera. More specifically, the present invention relates to an image processing processor for improving processing capacity by operating each component independently, and an image processing system for performing parallel processing and pipeline processing using the image processing processor.

[0002]

2. Description of the Related Art A conventional image processor for performing image data processing is disclosed in, for example, Japanese Patent Laid-Open No. 63-5226.
Japanese Patent Laid-Open No. 9 discloses a technology provided as an LSI.

[0003]

The above-mentioned conventional techniques are described with respect to a technique for providing image processing by integrating it in a single chip. However, the above-mentioned conventional technology and general image processing processors only modularize one or more of basic image processing functions such as filtering and feature extraction, and by incorporating them into an image processing system. In addition to these image processing module groups, an image memory control unit that controls the input / output of image data and an image input / output control unit that controls the input / output of image data to / from the image pickup device and the display device are required for construction. there were.

Therefore, when an image processing system is constructed using the image processing processor according to the above-mentioned prior art,
The following problems may occur.

First, the image processing system has essential functions such as capturing image data from an image pickup device such as a TV camera, reading and writing image data between an image processing processor and an image memory, and displaying the image processing result. is there. For that purpose, an image input / output control unit and an image memory control unit that perform two-dimensional address generation of an image and control of image data flow are necessary, but these control units have a problem that the circuit scale and the number of wirings increase. It was

Further, since a video signal of a TV camera or the like for photographing image data has a world standard signal regulation such as NTSC or PAL, the cycle and sampling time for producing digital image data from these signals are It will be constant. For example, a frequency of 14.3 MHz, which is four times as high as that of a subcarrier signal, is often used as a sampling time. On the other hand, advances in LSI technology have led to the development of image processors with an operating frequency of 30 MHz or higher. As described above, the operating frequencies of the video signal system and the image processing system are different, and the gap is expected to expand in the future. There is a problem that this point becomes a barrier for achieving high speed of the image processing system for processing the video signal.

Further, not only the TV camera but also a line sensor, which is different from a video signal in connection with a signal system different from the video signal, is required to be flexible and easy, and there is a problem that it is necessary to meet the requirement.

Further, since the image data flows through each image processor, there is a problem that the image data propagation delay due to the input / output buffer and the wiring capacity of the image processor impedes the speeding up of the image processing. there were.

The present invention has been made in order to solve the above-mentioned problems of the prior art, and its object is to include an image input / output control unit and an image memory control unit in an image processing processor for performing image processing. It is to reduce the size of an image processing system and facilitate its construction by integrating each of the following functional modules into a single chip.

Another object of the present invention is to improve the processing capability of the image processing processor by making the input and output of video images and the image processing independently operable.

Another object is to speed up image recognition by enabling access to the image memory in parallel.

Further, the present invention is to improve the throughput of the system by performing parallel processing and pipeline processing in the image processing system using the above image processor.

[0013]

In order to solve the above problems, the configuration of the invention relating to the image processing processor of the present invention is such that an image processing processor for fetching image data and processing the image data inputs the image data. And an image input / output unit that performs output, an image memory control unit that controls reading or writing of image data from / to the image memory, and image data input from the image input / output unit or the image memory control unit. An image processing unit that processes and outputs the result to an image memory control unit, a feature extraction unit that extracts a feature amount from the processing result of the image processing unit, operation specification of this image processing processor, and image data from the system processor A system control unit that mediates access is integrated into a single chip and configured.

More specifically, in the image processor, the image processing unit processes the image data and outputs the result to the image memory, and at the same time, independently of this, input / output of the image to / from the image memory, feature extraction, Each of the image input / output unit, the feature extraction unit, and the system control unit is provided with means for activating and controlling itself so that the image memories of the system processor can be accessed in parallel.

More specifically, in the above image processing processor, when the image data is fetched from the image pickup device and a display device for displaying the image data processed by the image processing processor is connected, these images are connected. Operation of imaging device and display device 1
There are more than one kind of video signal timings and video clocks, and there is an image processing clock that operates independently of this video clock, and these video clocks and image processing clocks are used as operation clocks. It was done.

In more detail, in the image processor, the image data is taken in from the image pickup device, and the image input / output unit is set to the time interval of the two image data taken in from the image pickup device. A field operation unit for performing measurement and fetching fields constituting image data at predetermined field intervals is provided.

More specifically, in the image processor, a video memory or an image memory is connected, and the image input / output unit synchronizes with a video signal timing of an image pickup device or a display device, and the video memory or the image memory is connected. When transferring image data from the image memory,
This means is provided with a means for setting information to be repeatedly transferred and a means for controlling the repeated transfer based on this information.

More specifically, in the above image processing processor, when an image memory is connected and the image processing section is executing image processing, the image memory control section is
The image memory control unit has a queue for registering a refresh request from the image memory, the image memory control unit registers the refresh request from the image memory in this queue, and after the image processing unit finishes the processing of one raster, The refresh operation is executed as many times as the number of refresh requests registered in this queue.

Next, in order to solve the above problems, the structure of the invention relating to the image processing system of the present invention has a video memory for storing the image data from the image pickup device and an image to be displayed on the display device. A display memory that stores data, one or more image memories that store an input image of image processing and an image processing result, the video memory, the display memory, and the image memory are connected to and stored in these memories. The image processing processor according to any one of claims 1 to 7, which performs image data processing, data transfer, etc., and image data is written in the video memory from an image pickup device in accordance with a first video clock. And the image from the image pickup device according to an image processing clock that operates independently of the first video clock. Image data read out from the display memory, the image data is read out from the display memory in accordance with the second video clock, the image is displayed on the display device, and the image processing operates independently of the second video clock. The image data is written according to the clock for use.

Another configuration of the image processor of the present invention is the image processor, which is a constituent element of the image processing system, wherein the image input / output unit has the video memory and the display memory built therein. It was made to exist.

According to another configuration, in the image processor, a video memory is connected, and the image input / output unit prohibits or permits writing of image data from the image pickup device to the video memory. It is the one.

Further, in the image processing system of the present invention, more specifically, the image input / output unit in the image processing processor as the constituent element writes image data from the image pickup device to the video memory. It is forbidden or allowed.

Another configuration of the image processing system of the present invention is to use any one of a plurality of image processing systems to connect the external port of the i-th image processing system and the external port of the j-th image processing system. A means for selecting whether to input image data from the image pickup device or image data from the external port is provided in the image processor in each image processing system, and the i-th image is connected. By allowing the output data from the display memory of the processing system to be input to the j-th (j> i) image processing system and switching the selecting means, each image processing system can be supplied from the image pickup device. Inputting image data, performing parallel processing of image data from different image pickup devices in a plurality of image processing systems, and By switching the selecting means, the image data from the image pickup device is input in the first image processing system, but the image data from the external port is input in the kth (k ≧ 2) image processing system. In the j-th (j> i) image processing system, the output data from the display memory of the i-th image processing system is input and pipeline processing is performed.

More specifically, regarding the configuration of the image processor of the present invention, when an image pickup device is connected and a color video signal is received from the image pickup device, the image input / output unit causes the image pickup device to pick up the image pickup image. An encoder that separates a color signal and a luminance signal from a color video signal from the device, a decoder that synthesizes a color video signal from the color signal and the luminance signal, and stores all or part of the image data output from the encoder. The video memory and the display memory for storing all or part of the image data stored in the image memory are formed.

[0025]

In the image processing system according to the present invention, a video image input / output unit, an image memory control unit, an image processing unit for processing image data, which is an essential function of the image processing system, and a feature amount are accumulated from the image processing result. The feature extraction unit, the image output unit that displays image data, and the system control unit that specifies the operation of the image processing processor are all integrated into one chip in the image processing processor, so you only need to connect a memory to this image processing processor. The image processing system can be configured with, and it can contribute to the miniaturization of the image processing system.

Since the video clock for inputting / outputting the video image and the image processing clock can be independently input, the image processing can be executed at the limit speed of the image memory or the image processing arithmetic unit.

Further, during image processing, video image input, image display, or image memory access from the system processor can be executed in parallel as long as the target image memory numbers do not overlap, which contributes to faster image recognition. be able to.

Further, in the image processing system using the above image processing processor, the image timings on the input side of the video memory 8 and the output side of the display memory 9 are matched, so that parallel image processing and pipeline image processing are performed. It can be easily achieved.

[0029]

Embodiments of the present invention will be described below with reference to FIGS. 1 to 15. [Embodiment 1] Hereinafter, a first embodiment according to the present invention will be described with reference to FIG.
It will be described with reference to FIGS. 11 and 15. (I) Configuration of Image Processing Processor and Image Processing System Using It First, the configuration of an image processing processor according to an embodiment of the present invention and an image processing system using the same will be described with reference to FIGS. 1 and 2. Try. FIG. 1 is a block diagram showing the arrangement of an image processor according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of an image processing system using the image processing processor shown in FIG.

As shown in FIG. 1, the image input / output unit 2,
The image memory control unit 3, the image processing unit 4, the feature extraction unit 5, and the system control unit 6 exchange control signals and data via the signal line 7. The function and detailed configuration of each part shall be explained in (II).

The external image processor 16 shown in FIG.
Is a processor for executing an image processing function that cannot be executed by the image processing processor 1. The video memory 8 and the display memory 9 have two ports, an input port and an output port, and these two ports can be controlled asynchronously with each other. That is, these memories can execute the data input operation and the data output operation asynchronously.

The reason why the memories such as the video memory 8 and the display memory 9 are provided is as follows. That is, the TV camera 12 and the CRT display 13 operate in synchronization with the video clock, which is normally 12 to 15 MHz.
The z one is often used. On the other hand, in image processing, it is more effective to speed up the entire image recognition if the image data is once stored in the image memory and then processed at the limit speed of the image memory or the image processing calculator. Therefore, as shown in FIG. 2, the image processor of the present invention uses the image processing clock IPCLK1 in addition to the video clock.
You can enter 8. Therefore, in order to absorb the difference between the clocks of these video clock and image processing clock, the input port and the output port are separated,
A video memory 8 and a display memory 9 are provided so that both ports can perform input / output asynchronously.

According to the configuration of FIG. 2, the synchronizing signal for video timing and the video clock VCLK are supplied to the video memory 8.
Is supplied to the display memory 9 and the video memory 8
The fetching of the image data into and the display of the image data from the display memory 9 are at the same timing.

(II) Operation of Image Processing Device The operation of the image processing processor according to the present invention will be described below with reference to FIG.
It will be outlined according to the flow of image recognition using. here,
The “image recognition” is a series of processes for fetching image data from the outside, performing image processing, extracting the feature amount, and using the extracted feature amount to determine what the object is.

First, the image to be processed from the TV camera 12 is loaded into the image memories 14-1 to 14-n. next,
The image is subjected to filtering, binarization, labeling, and other processing to extract characteristic quantities such as density frequency distribution, area, and number of objects. Finally, the object is recognized using these feature quantities. At this time, if necessary, TV camera 1
It is also possible to display the image of 9 and the image such as the recognition result on the CRT 13. Of the series of processes, only the recognition of the object using the feature amount cannot be executed by the image processing processor 1 of the present invention, but other processes required for image recognition are:
It can be executed by the image processor 1 of the present invention.

In the image processing system of FIG. 2, the TV camera 1
The image of 2 is the A / D converter 10 in synchronization with the video clock.
It is digitized and the whole screen is written in the video memory. After the writing is completed, the image input / output unit 2 reads the image data of the video memory 8 in synchronization with the image clock and supplies it to the image processing unit 4 and the image memory control unit 3. Then, the image memory control unit 3 writes the received image data in the image memories 14-1 to 14-n.

Next, the image processing unit 4 receives the image data from the image input / output unit 2 or the image data read from the image memories 14-1 to 14-n by the image memory control unit 3 and performs a predetermined process. Perform. After that, the processing result is stored in the image memories 14-1 to 14-n via the image input / output unit 2, the feature extraction unit 5, or the image memory control unit 3.
When executing an image processing function that cannot be performed by the image processing unit 4, the external image processing processor 16 is added to the image processing processor 1 and the processing is entrusted to be executed here.

The feature extraction unit 5 has a processing result in the image processing unit 4 and the image memory control unit 3 has image memories 14-1 to 14-.
It has a function of receiving the image data read from n and extracting the feature amount.

Processing result in the image processing unit 4 and the image memory 1
The display of the image data read from 4-1 to 14-n is performed by displaying the image data via the image input / output unit 2.
The image data is read from the display memory in synchronization with the video clock and is output to the CRT display 13 via the D / A converter 11. The writing of the A / D conversion result to the video memory 8 and the output of the image data of the display memory 9 to the D / A converter 11 are performed in synchronization with the video clock VCLK17, and otherwise, in synchronization with the image processing clock IPCLK18. It is done.

The system processor 15 executes the input / output of image data, the setting of the image processing function and the feature extraction function, the access of the image memory, the reading of the feature extraction result and the recognition process.

Next, the operation of the image processor according to the present invention will be described in accordance with the flow of the image recognition described above with reference to FIG. 2 and FIGS. Let's explain. The operation of fetching the image data from the TV camera 12 and the method of displaying the image data on the CRT display 13 will be described later while following the operation of each block.

(1) Image Input / Output Unit 2 FIG. 3 is a block diagram showing the arrangement of the image input / output unit 2 according to the first embodiment of the present invention. FIG. 4 is a diagram schematically showing an effective screen area.

The image input / output unit 2 is roughly composed of a video screen timing control unit 200, an input control unit 210, and an output control unit 220. The image input / output unit 2
A video memory 8 for storing the image data from the TV camera 12 and a display memory 9 for storing the image data to be displayed on the CRT 13 are connected to each other, and data and signals shown in FIG. Do it.

First, the operation of the video screen timing control section 200 will be described.

The video screen timing control unit 200 is composed of an effective screen defining unit 201 and a synchronizing unit 202, and
A horizontal / vertical synchronization signal (H / VSYNC) and a video clock (VCLK) that define the screen of the camera 12 or the CRT 13 are input to define an effective screen. Here, the "valid screen" means
This is an area in which a video signal exists and which has a screen size as an object of image processing and image display.

As a method of defining the valid screen, there is a method shown in FIG. 4, for example. It is assumed that the raster scan start point moves to the upper part of the screen when the vertical sync signal VSYNC pulse is input, and the raster scan is performed when the horizontal sync signal HSYNC pulse is input. At this time, the effective screen is
Starting from a point after the predetermined number of lines and advanced by the predetermined number of pixels, a predetermined number of pixels in the horizontal direction and a predetermined number of lines in the vertical direction can be defined. In the example shown in FIG. 4, the effective screen area is output as the WEN signal and the REN signal.
Then, each signal is input to the video memory and the display memory as shown in FIG. 3, and the image data of the TV camera which is A / D converted in synchronization with the video clock VCLK is the WEN signal, RE
The display data is read from the display memory 9 or written into the video memory 8 only during the period when the N signal is "Low". These are always performed in synchronization with the video signal timing. Further, in FIG. 4, a screen end pulse is output after the valid screen ends.

The horizontal / vertical synchronizing signal H / VSYNC and the effective screen defining unit 201 operate in synchronization with the video clock VCLK, while the input control unit 210 and the output control unit 220 operate in synchronization with the image processing clock IPCLK. Video clock VCL
Since K and the image processing clock IPCLK are usually asynchronous,
Screen end signal from the effective screen definition unit 201 and horizontal /
If the vertical synchronizing signal H / VSYNC is directly input to the input control unit 210 and the output control unit 220, oscillation may occur. Therefore, in this embodiment, the synchronization unit 202 synchronizes the screen end signal and the horizontal / vertical synchronization signal H / VSYNC from the valid screen definition unit 201 with the image processing clock IPCLK.

Now, referring to FIG. 6, this video clock
Let us explain the circuit configuration that synchronizes VCLK with the image processing clock IPCLK. FIG. 6 is a block diagram showing the configuration of the synchronization unit 202 according to the first exemplary embodiment of the present invention.

The synchronizing section 202 is composed of two flip-flops 2021 and 2022. The image processing clock is used as the clock (CK) of the flip-flops 2021 and 2022.
IPCLK input, flip-flop 2021 data input
Screen end signal and horizontal / vertical sync signal on (D1, D2, D3)
Input H / V SYNC. By doing this, the image processing clock is output from the outputs (Q1, Q2, Q3) of the flip-flop 2022.
The screen end signal and horizontal / vertical sync signal H / VSYNC synchronized with IPCLK are output.

Next, the operation of the input control section 210 will be described. The input control unit 210 receives the image transfer request from the system processor, reads the image data VID from the video memory 8, and transfers it to the image memory control unit 3.

First, the system processor 15 transfers the image data in the video memory 8 to the transfer start registers 1 and 211 of the input control unit 210 shown in FIG. 3 via the system control unit 6 and the signal line 7 in FIG. Request and transfer destination image memory channels (14-1, 14-2, ..., 14-n)
Write.

This image data transfer request TREQ1 is sent to SEL21.
It is transmitted to the transfer determination units 1 and 213 via 2 and also to the image memory control unit 3. The image memory channel IMCH1 of the transfer destination is also transmitted to the image memory control unit 3. Then, the transfer determination units 1 and 213 wait for the image data transfer request acceptance signal ACK1 from the image memory control unit 3 to become active. Image data transfer request acceptance signal ACK1
Is activated, next, transfer determination units 1 and 213
Waits for a screen end signal synchronized with the image processing clock from the video screen timing control unit 200, and when the screen end signal becomes active, the transfer determining units 1 and 213 cause the transfer area determining units 1 and 215 to generate the image address. Parts 1, 21
6 and the enable signal to the video memory controller 217. If the image data transfer request acceptance signal ACK1 does not become active even though the screen end signal from the video screen timing control unit 200 becomes active, the video screen timing control unit 200 is sent via a signal line (not shown). The output of the WEN signal is prohibited to the valid screen defining unit 201 in FIG. By doing this,
Prohibits updating the contents of video memory. In this way, the update of the contents of the video memory is prohibited in order to prevent the image data, which is desired to be subjected to image processing, from being rewritten before being transferred to the image memory when the image data is stored.

Next, the image address generators 1 and 216 calculate the address VX / VYAddr of the image memory of the transfer destination and give it to the image memory controller 3 via the signal line 7. And
The transfer area determination units 1 and 215 determine all or part of the effective screen area shown in FIG. 4 and notify the image memory control unit 3 as an EXEC1 signal. The transfer area determination unit 1,
To simplify the configuration of 215, the area to be transferred is defined as the effective screen definition unit 20 of the video screen timing control unit 200.
The area may be the same as the area defined by 1.

On the other hand, the video memory control section 217 reads the image data from the video memory and gives the image data to the image memory control section 3 via the signal line 7. When the image data has been transferred from the video memory 8 to the image memory, the transfer request of the transfer start registers 1 and 211 is cleared.

Here, the transfer activation registers 1 and 211 are provided with a transfer request clear prohibition bit, and this bit is controlled by the system processor. For example, if this bit is turned on to prohibit the clearing of the activation transfer request, a transfer request is always generated from the transfer activation registers 1 and 211, and the video memory 8 is synchronized with the video signal timing. The image data can be repeatedly transferred from the image memory to the image memory. Then, the system processor 15 can turn off this bit to complete the transfer of the image data.

In addition, the transfer start registers 1 and 211 and the EXEC
One signal can be monitored by the system processor 15 via the signal line 7 and the system controller 6. That is, the system processor 15 can monitor the set value of the transfer start register and the level of the EXEC2 signal. Here, the EXEC1 signal is a signal indicating that an image is being transferred from the input control unit of the image input / output unit 2 shown in FIG. 3 to the image input control unit 33 of the image memory control unit 3 shown later using FIG. Is.

In the examples shown in FIGS. 2 and 3, only one video memory is connected, but it is possible to adopt a configuration in which one of the plurality of video memories is selected.

Next, the field counter 214 in the input control section 210 will be described. When the moving image processing is performed by the image processing processor, it is necessary to perform a calculation regarding a field or a frame forming an image such as a time difference between input images and an image input at every predetermined time. The field counter 214 using the vertical synchronization signal VSYNC does this. Field counter 2
14 receives the vertical synchronizing signal VSYNC and counts up. For example, when measuring the time difference between input images, the system processor uses the transfer start registers 1 and 21.
The difference in the value of the field counter when the image capture start is written in 1 may be obtained. Further, when performing image input at every predetermined time, the selector SEL212 is set on the side of the field counter 214, and a value obtained by converting the predetermined time into the number of fields is set at the field counter 214. When the field counter 214 counts up from 0 and reaches the set number of fields, the field counter 214 is cleared to 0 and the transfer activation units 1 and 213 are activated.
Then, an image transfer request is generated and the counting operation is performed again. As a result, the transfer start registers 1 and 211
The image can be transferred from the video memory to the image memory channel of the image memory at predetermined time intervals according to the image transfer sequence.

Next, the operation of the output control section 220 will be described. The output control unit 220 uses the system processor 15
In response to the image transfer request from the image memory, the image data read from the image memory is displayed via the image memory control unit 3 as display data.
Transfer to the display memory 9 as DSD. This transfer is performed similarly to the transfer from the video memory 8 to the image memory. The transfer activation registers 2 and 221 are used to set this operation. The configuration of the transfer start register 2 will be described below with reference to FIG. FIG. 15 is a diagram schematically showing the configuration of the transfer start register 2.

As shown in FIG. 15, the transfer start register has an image data transfer request bit EX, a loop display request bit LOOP, and a display function bit DSPFU.
N, brightness control bit HTCNT, bit SOUR IMCH specifying image memory channel to display, bit SOURVM specifying video memory channel to display
CH, and a bit DEST DMCH for designating a display memory channel to which display data is written. Here, the display function bit DSPFUN is a bit for designating display of the video memory, display of the image memory, and addition display of the video memory and the image memory. The brightness control bit HTCNT is a bit for designating whether to perform full brightness display or half brightness display.

Now, let's follow the operation of the output control section 220 in order. First, the system processor 15 operates as shown in FIG.
3 via the system control unit 6 and the signal line 7 of the output control unit 220 of FIG. 3 to the transfer start registers 2 and 221 of the image data transfer request to the display memory 9 and the transfer source image memory channel (14-1, 14). -2, ..., 14-n) is written. The image data transfer request TREQ2 is transmitted to the transfer determination units 2 and 22.
2 and the image memory control unit 3. The image memory channel IMCH2 of the transfer source is also given to the image memory control unit 3.

Then, the transfer determination units 2 and 222 wait for the image data transfer request acceptance signal ACK2 from the image memory control unit 3 to become active. Image data transfer request acceptance signal
When ACK2 becomes active, next, transfer determination units 2 and 222
Waits for a screen end signal synchronized with the image processing clock from the video screen timing control unit 200, and when the screen end signal becomes active, the transfer determination units 2 and 222 determine the transfer area determination units 2 and 223 and the image address generation unit 2. , 224 and the display memory control unit 225. Here, the enable signal is a signal that enables image data transfer from the image memory to the display memory. When the image data transfer request acceptance signal ACK1 does not become active even though the screen end signal from the video screen timing control unit 200 becomes active, the transfer determination units 2 and 222 prohibit the output of the enable signal. Next, the image address generators 2 and 224 calculate the address DX / DY Addr of the transfer source image memory, and
To the image memory control unit 3 via. Then, the transfer area determination units 2 and 222 determine the whole or a part of the effective screen area of FIG. 4 and use the image memory control unit 3 as an EXEC2 signal.
Tell. Further, in order to simplify the configuration of the transfer area determination units 2 and 222, the transferred area may be the same area as the area defined by the valid screen defining unit 201 of the video screen timing control unit 200. The same as described in the transfer area determination units 1 and 215 of the input control unit 210.

On the other hand, the display memory control unit 225 writes the image data read from the image memory control unit 3 via the signal line 7 into the display memory. At this time, it is possible to select which image data VID from the video memory 8 and the synthesizing unit 226 are to be sent, or to perform modification such as density addition or halftone density transfer to the display memory. Is.

As shown in FIG. 3, since the output data VID of the video memory 8 is input to the synthesizing unit 226, the image memory is not accessed when the contents of the video memory 8 are displayed. It does not interfere with image processing.

Finally, when the transfer of the image data from the image memory to the display memory 9 is completed, the transfer start registers 2, 2
The transfer request 22 is cleared.

The transfer start registers 2 and 222 and the exec
The two signals can be monitored by the system processor 15 via the signal line 7 and the system control unit 6. That is, the system processor 15 can monitor the set value of the transfer start register and the level of the EXEC2 signal, as described in the description of the input control unit. Where EX
The EC2 signal is a signal indicating that an image is being transferred from the output control unit of the image input / output unit 2 shown in FIG. 3 to the image output control unit 34 of the image memory control unit 3 shown later using FIG.

Since it is complicated to set the transfer start processing in the transfer start registers 2 and 221 every time the display is performed, the transfer start registers 2 and 221 are set in this embodiment.
Is provided with a loop display control bit LOOP. When this bit is set, the transfer determination units 2 and 222 cause the synchronization unit 20 to
Each time the screen end signal 2 is input, the transfer area determination unit 2,
An enable signal for transferring image data from the image memory to the display memory is output to 223, the image address generation units 2 and 224, and the display memory control unit 225. Therefore, by setting this bit, it becomes possible to automatically repeat the display activation of the image data.

Although only one display memory is connected in FIGS. 2 and 3, the output control unit may be configured to connect a plurality of display memories and may select one of them. It is possible.

The operations of the input control unit and the output control unit of the image input / output unit 2 have been described above in detail, but finally,
The sequence of image data transfer related to this will be described with reference to FIG. FIG. 5 is a timing chart showing the image transfer sequence.

In this timing chart, the horizontal axis represents time, indicating that the vertical synchronizing signal is periodically issued.

Here, FIG. 5A illustrates a process of transferring image data of the video memory from the TV camera and the image data of the image memory from the video memory, and the transfer is performed at the solid line in the figure. It indicates that

Similarly, FIG. 5 (b) shows a CR from the display memory.
The transfer process of transferring from T and the image memory to the display memory is described, and this also shows that the transfer is performed at the solid line in the figure.

According to the present embodiment, like the image transfer sequence shown in FIG. 5, after the writing of the TV camera image into the video memory and the display of the display memory contents are completed, respectively, the video memory is transferred to the image memory. Since the transfer is performed from the image memory to the display memory, the operation synchronized with the video signal timing can be guaranteed.

Further, according to the configuration of the image input / output unit 200 shown in FIG. 3, since the transfer start register is provided separately for the input control unit and the output control unit, the video memory 8 is switched to the image memory. And the transfer from the image memory to the display memory 9 can be executed independently and in parallel.

(2) Image Processing Unit 7 Next, the operation of the image processing unit will be described with reference to FIG. FIG. 7 shows the image processing unit 4 according to the first embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

The video memory 8 and the image memory 14-1,
The image processing unit 4 executes predetermined image processing on the image data read from 14-n.

Here, as generally-used image processing, spatial filtering, binarization, and thinning are described in detail in Reference 1 (Makoto Nagao, "Image Recognition", published by Corona Publishing Co., Ltd.). , Labeling and the like. An example of a hardware configuration that executes these at high speed is described in Reference 2
(Hiroshi Takenaga and 6 others, "Image Processing LS for Vision System"
I ”, IEEJ Technical Committee on Industrial Power and Electricity, IEA-88-1, 198
8.7). In the example shown in FIG. 7, for the local image of 3 × 3 pixels cut out from the image,
It is a structural example which performs spatial filtering etc.

As shown in FIG. 7, the video memory 8 and the image memories 14-1, ..., 1 supplied via the signal line 7 are connected.
The image data in 4-n is delayed by the first line memory 41 and the second line memory 42, and the shift register 40
Is cut out as a local image of 3 × 3 pixels. The cut out local image of 3 × 3 pixels is applied to the multiplier array 44, and is multiplied by a coefficient preset in the weighting coefficient memory 43. After that, the output of each multiplier of the multiplier array 44 is given to the arithmetic unit array 45, and each arithmetic unit ALU performs arithmetic operations such as addition, subtraction, and size comparison. Finally, the result calculated by each arithmetic unit array ALU is input to the integration unit 46, and the integration unit 46 performs processing such as summing them, binarizing the total result, and obtaining the maximum value / minimum value. Be done. Then, the final result from the integrating unit 46 is output to the signal line 7 not shown in FIG. 7 via the signal line 48.

In addition, the coefficient of the weighting coefficient memory and the arithmetic unit ALU
If it is configured so that the arithmetic function of can be set programmable from the system processor, image noise removal,
Filtering processing such as first derivative, Laplacian, Min-Max filter, Sobel operation, etc. can be performed. Figure 7
In the configuration example shown in (1), one of the weighting factors and the image data supplied via the signal line 400 and the delay circuit 49 can be switched by the selector SEL401 and supplied to the multiplier array 44. Therefore, the signal line 4
If different image data are given to 7 and 400, inter-image calculation can be executed. Further, the binarization process can be performed by comparing with a threshold that can be set programmable by the integration unit 46.

As described above, according to the configuration of the image processing section shown in FIG. 7, the filtering processing result processed by the arithmetic unit ALU can be given to the immediate integration section 46 and binarized in a pipeline manner. It can contribute to speeding up of image processing. Further, if the binary image preprocessing processor shown in Document 2 is given to the image processing unit 4 with the image data of the built-in signal line 47, thinning processing and labeling processing can be performed. Similarly, it is also possible to make the image processing unit 4 highly functional by incorporating an image processing function effective for image recognition such as grayscale pattern matching and binary pattern matching into hardware and incorporating it into the image processing unit 4.

Furthermore, the image processing unit 4 shown in FIG. 7 can input and output image data via the signal line 402, and thus, by using the external image processing processor, the image processing function which cannot be executed by the image processing unit 4 is performed. Ready to run.

(3) Feature Extracting Unit 5 Next, the operation of the feature extracting unit will be described with reference to FIG. FIG. 8 shows the feature extraction unit 5 according to the first embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

The image data processed by the image processing unit 4 as described above, the video memory 8, the image memories 14-1, ..., 14
It is necessary to extract the feature amount necessary for the image recognition performed on the image data read from -n. The feature extracting unit 5 executes this.

The feature quantities often used for image recognition include the density frequency distribution, the projection distribution, the area of the object, the center of gravity of the object, etc., as described in detail in Reference 1. FIG.
The example shown in FIG. 4 is for obtaining these feature amounts, and the feature amount memory 52 for storing the feature amounts, the calculator 53, the screen coordinate generation unit 54, the first selector 55 and the second selector 5 are used.
It is composed of 6. Further, in the example shown in FIG. 8, a 2-port memory is used as the feature amount memory 52 so that the system processor can easily access it.

To obtain the density frequency distribution in the feature extraction unit 5 of this configuration, the system processor 15 is set to operate as follows. The value of the image data is selected by the first selector 55 and is given to the B side address B: ADR of the feature amount memory 52 via the signal line 51. On the other hand, the constant “1” is selected by the second selector 56 and given to the calculator 53,
Addition is selected as the arithmetic function of the arithmetic unit 53. After setting in this way, if the image data for one screen is given through the signal line 7 and the signal line 51, the frequency of a certain density value (address of the characteristic amount memory) is stored in the characteristic amount memory.

Further, in order to obtain the center of gravity of the numbered (labeled) objects, the first selector 55 outputs the image data, the second selector 56 outputs the output of the screen coordinate generator 54, and the calculator 53 Set to select addition as the calculation function. In this way, since the accumulated value of the coordinates of each object is stored in the feature amount memory, if the area of each object is obtained in advance, the barycentric coordinates of each object can be calculated by dividing the area. In this way, the data selection function of the first selector 55 and the second selector 56 and the arithmetic function of the arithmetic unit 53 can be set by programming them in the system processor 15, so that the above-mentioned characteristic amount can be simplified. It will be possible to ask for.
Further, in the image processor 1 of the present invention, since the processing result of the image processing unit 4 can be immediately given to the feature extraction unit 5, the image processing and the feature extraction process can be pipelined,
This can contribute to speeding up image recognition.

(4) System Control Unit 6 Next, the operation of the system control unit 9 will be described with reference to FIG. FIG. 9 is a block diagram showing the configuration of the system control unit 9 according to the first embodiment of the present invention.

The input / output of the video image, the selection of the image processing function and the feature extraction function, and the access of the extracted feature amount and the image data of the processing result are performed by the system processor via the system control unit 6.

The system control unit 6 comprises an address decoder 60, a synchronization unit 61, a DMA control unit 62, an image memory access control unit 63, and a feature amount memory address generation unit 64. The address decoder 60 selects a control register built in the image processor 1 according to the present invention.

The reason why the synchronizing section 61 is provided is as follows. That is, the image input / output unit 2 operates with the video clock VCLK and the image processing clock IPCLK,
The image processing unit 4, the feature extraction unit 5, and the image memory control unit 3 described later operate on the image processing clock IPCLK, while the system processor 15 operates asynchronously with them. Therefore, if the image processor 3 is set to perform an image processing operation or the like at the timing of the system processor 15, the image processing operation may become unstable. Therefore, in order to prevent this, the system processor 1
The signal from 5 is synchronized with the image processing clock IPCL in the synchronization unit 61.
It uses K to synchronize. The synchronization unit 61 can be realized by the same configuration as the synchronization unit 202 of the image input / output unit 2 already shown in FIG.

The image memory access control unit 63 informs the image memory control unit 3 of the number IMCH of the image memory to be accessed and the access request IMREQ, receives the response IMACK from the image memory control unit 3, and receives the image memories 14-1, …, 14-
Give address SX / SY to n. Also, the address is
It is updated after the system processor has finished reading or writing image data.

Further, the feature quantity memory address generation unit 64
Generates an address for the feature memory. The address is updated after the system processor finishes reading or writing the characteristic amount.

The system control unit 6 can access the image memory or the feature amount memory by DMA (Direct Memory Access). This is performed by the DMA control unit 62 by exchanging the request REQ and the response ACK with the system processor 15.

(5) Image Memory Control Unit 3 Next, the operation of the image memory control unit 3 will be described with reference to FIG. FIG. 10 is a block diagram showing the configuration of the image memory control unit 3 according to the first embodiment of the present invention.

As described above, the input / output of image data to / from the image pickup device or the display device, the image processing, the feature extraction process, the access to the system processor 15 and the like to the image memory are frequently performed, and these processes are performed. Need to be done at high speed and efficiently. Therefore, the management of the image memory is extremely important in the image processing system. The image memory control unit 3 executes this.

The image memory control unit 3 shown in FIG.
Using four dynamic RAMs as the image memory, video image input, image display, or image memory access from the system processor 15 can be executed in parallel during image processing as long as the target image memory numbers do not overlap.

The image memory control section includes an overall control section 30, a system processor control section 31, an image processing control section 32, an image input control section 33, an image output control section 34, an address / data selection section 35, a refresh control section 36, and Four memory access control units 37-1 to 37-4 having the same configuration
Composed of.

The system processor control unit 31 has the configuration shown in FIG.
The image memory access request IMREQ, the image memory number IMCH, and the image memory address SX / SY are input from the system control unit 6 shown in FIG. Then, the system processor control unit 31 sends the image memory access request IMREQ and the image memory number IMCH to the overall control unit 30 via the signal line 304.
Give to. As a result, when the access request permission response is received from the overall control unit 30 via the signal line 304, the system processor control unit 31 returns a response IMACK to the system control unit 6, and the system processor 15 and the image memory 14 receive the response IMACK. The input and output of image data in will start.

Next, the operation of the image processing controller 32 in the image memory controller 3 will be described. FIG. 11 is a block diagram showing the configuration of the image processing control unit 32 according to the first embodiment of the present invention.

The image processing control unit 32 has a function of inputting and outputting image data and image processing results with the image processing unit 4 and the feature extraction unit 5.

More specifically, in more detail, the function of transferring the image data of the image memory to the image processing section, the function of transferring the image processing result of the image processing section 4 to the image memory, and the feature extraction section 5 of the image data of the image memory. It has a function to transfer to. The image processing control unit 32 is composed of an activation control unit 3200, a delay circuit 3210, first read address generation units 1 and 3220, second read address generation units 2 and 3230, and a write address generation unit 3240. To be done.

The system processor 15 has the activation controller 3
The image memory number RIMCH1 in which the image to be processed is stored in 200 and the image memory number WIMC in which the processing result is written
Specify H. In addition, when performing inter-image operations such as addition and subtraction of two images, the numbers of the two image memories
RIMCH1 and RIMCH2 will be specified. After that, the system processor sends the image processing start IP to the start control unit 3200.
When REQ is written, these RIMCH1, RIMCH2, WIMCH, IP
The REQ signal is transmitted to the overall control unit 30. And
When the image memory number WIMCH is designated and the image processing start IPREQ is instructed, these signals are transmitted to the overall control unit 30. Then, the activation control unit 3200 waits for a response IPACK from the overall control unit 30.

When the response IPACK becomes active, the first read address generator 1, 3220 and the second read address generator 2, 3230 cause the image processing clock IPCLK
The image memory address is calculated in synchronization with.

Further, the response IPACK is delayed by the delay circuit 3210 by a predetermined delay, and then the write address generation unit 3240.
Conveyed to. Then, in response to this, the write address generator 3240 calculates the image memory address in synchronization with the image processing clock IPCLK. This is to absorb the delay from the image input in the image processing unit 4 to the output of the processing result. Raster scanning and enlargement / reduction can be selected as the image memory address calculation method. In addition, the processing area is a starting point for each image memory of the first reading, the second reading, and writing, and the areas X and Y.
Specify by setting the length.

Next, the image memory control 3 shown in FIG.
In the image input control unit 33 and the image output control unit 34 inside, transfer requests TREQ1 / 2 from the input control unit 210 and the output control unit 220 of the image input / output unit 2 shown in FIG. IMCH1 / 2, transfer execution EXEC1 / 2, image address VX / VY, DX / DY address are input. Then, the image input control unit 33 and the image output control unit 34 are
The transfer request TREQ1 / 2 and the image memory number IMCH1 / 2 to be transferred are given to the overall control unit 30 via the signal line 304. Next, when the image input control unit 33 and the image output control unit 34 receive the transfer request permission response from the overall control unit 30 via the signal line 304, the image input control unit 33 and the image output control unit 34 return the response ACK1 / 2 to the image input / output 2.
When receiving the transfer execution EXEC1 / 2 from the image input / output unit 2,
The image input control unit 33 inputs the image data VID from the video memory 8 to the image memory, and the image data image output control unit 34 inputs the image data DSD from the image memory to the display memory 9.
Is output.

The overall control unit 30 receives requests from the system processor control unit 31, the image processing control unit 32, the image input control unit 33, and the image output control unit 34, performs priority control, and then sends a request permission response to each unit. return. The priority control referred to here is to accept the request that arrives earliest, and if they arrive at the same time, when the image memory numbers to be used are different, a request permission response is returned to each unit to match those image memory numbers. At this time, control is such that a request permission response is returned in the order of video image input, image processing, image display, and system processor access. Therefore, image processing, video input, display, and system processor access can be processed in parallel as long as the target image memory numbers do not overlap, but if the image memory numbers conflict, other processing will be delayed until the processing ends. Become.

The image memory number associated with the received request is input to the address / data selection section 35 via the signal line 305, where the system processor control section 3
1, the image access control unit 32, the image input control unit 33, the image output control unit 34 to select the address and data, the memory access control unit 37-1 ~ 1 corresponding to the image memory number.
It is output to 37-4. Similarly, the memory access control unit 3
The image data from 7-1 to 37-4 is selected and output to the system processor control unit 31, the image processing control unit 32, the image input control unit 33, and the image output control unit 34.

Memory access control units 37-1 to 37-4
Performs access for each pixel using the input image memory address and image data, and continuous pixel access in the high speed page mode or the static column mode. Further, the image memory is refreshed in response to a request from the refresh controller 36. When the refresh request is generated during processing such as image processing, the memory access control units 37-1 to 37-4 of the present invention can control the refresh operation to temporarily wait until the processing of a predetermined pixel is completed.

That is, in a DRAM often used as an image memory, it is necessary to perform a refresh operation, but this operation is usually performed at regular time intervals. In the image processor of the present invention, for example,
The refresh request is stored until the image processing unit processes one raster, and the refresh request is issued at once when the processing for one raster is completed.

This processing can be realized by using an up-down counter, for example. That is, when a request from the refresh control unit 36 is generated, the count-up is performed, and when the refresh is performed, the count-down is performed. Then, the countdown may be prohibited during the image processing. Providing such an up / down counter to control the refresh request means to form and control a queue for the refresh request. Here, the refresh control unit 36 is a block that controls the timing of refreshing the image memory.
This is done by setting the number of cycles to generate a refresh request.

As described above, video image input, image display, or image memory access from the system processor during image processing can be executed in parallel as long as the target image memory numbers do not overlap, which contributes to faster image recognition. can do.

The input control unit 210 and the output control unit 220 of the image input / output unit 2 of FIG. 3 each have an image address generation unit. In addition, the system control unit 6 of FIG.
Image memory access control unit 63
Generates SX / SY. Although the present embodiment has such a configuration, it is easy to realize all of these image address generation processes by the image memory control unit 3.

[Second Embodiment] A second embodiment according to the present invention will be described below with reference to FIG. FIG. 12 is a block diagram showing the configuration of the image input / output unit 2 according to the second embodiment of the present invention.

In this embodiment, the configuration of the image input / output unit 2 of the first embodiment is changed.

According to the configuration of the image input / output unit shown in FIGS. 2 and 3 of the first embodiment, the video timing can be matched on the input / output sides of the video memory and the display memory, so that a general standard television can be used. John system (NTSC) TV camera, CRT
When using, there is an effect that connection can be easily performed. However, some image recognition applications require high-resolution images, and for that purpose, high-definition TV cameras or line sensors are used as TV cameras. In this case, the video timings of the TV camera and CRT are different. In order to deal with this, the image input / output unit 2 may be configured, for example, as in this embodiment.

The image input / output unit 2 shown in FIG. 12 has two video screen timing control units 200-1 and 200-2.
3, an input control unit 210 and an output control unit 220. Each of the constituent elements is the video screen control unit 20 shown in FIG.
0, the input control unit 210, and the output control unit 220 have the same configuration.

Video screen timing controller 1,200-
1 is the sync signal 1 from the TV camera 12 and the video clock VC
LK1 is input to define the effective screen of the TV camera, and the video screen timing control unit 2, 200-2 inputs the synchronization signal 2 from the CRT 13 and the video clock VCLK2 to define the effective screen of the CRT.

The input control unit 210 receives the signals from the video screen timing control units 1, 200-1 and transfers the image from the video memory 8 to the image memory according to the transfer sequence shown in FIG.

On the other hand, the output control section 220 receives the signal from the video screen timing control section 2, 200-2 and transfers the image from the image memory to the display memory 9 according to the transfer sequence shown in FIG.

[Third Embodiment] A third embodiment of the present invention will be described below with reference to FIG. FIG. 13 is a block diagram showing the configuration of the image input / output unit 2 according to the third embodiment of the present invention.

Also in this embodiment, the configuration of the image input / output unit 2 of the first embodiment is changed. In the image processing system shown in FIG. 2 of the first embodiment, the video memory 8 and the display memory 9 are externally attached, but in order to further downsize the image processing system, these memories should be built in the image processing processor. Can also be considered. In the present embodiment, the image input / output unit 2 has such a configuration example.

In the image input / output unit 2 shown in FIG. 13, in addition to the image input / output unit shown in FIG. 3, the input control unit 210 includes an encoder 218, a video memory 8, and an output control unit 220.
The decoder 227 and the display memory 9 are built in.

The encoder 218 is used when connecting a color TV camera, and has a function of separating a color signal and a luminance signal from a color video signal digitized by an A / D converter. The decoder 227 has a function opposite to that of the encoder 218, and synthesizes a color video signal from a color signal and a luminance signal. When using a monochrome TV camera, these encoder 218 and decoder 22
7 may be prohibited.

In the example shown in FIG. 13, the video memory 8 and the display memory 9 for one screen are built in. However, this may be built in with the number of gates within the range allowed by the integration degree of the LSI. It may be a screen or a partial screen. In the case of a partial screen, the transfer sequence of FIG. 5 may be transferred from the video memory 8 to the image memory or from the image memory to the display memory 9 when the writing of the partial screen is completed.

According to the configuration of this embodiment, the video memory 8
Since the display memory 8 and the display memory 8 are incorporated in the image processing processor and only the A / D converter and the D / A converter are externally attached, it is possible to contribute to downsizing of the image processing system. .

[Fourth Embodiment] A fourth embodiment according to the present invention will be described below with reference to FIG. FIG. 14 is a block diagram showing the configuration of another image processing system of the present invention.

In the image processing system of the first embodiment, it has been described in the explanation with reference to FIG. 2 that the image timings of the input side of the video memory 8 and the output side of the display memory 9 are the same.
By using this, parallel image processing and pipeline image processing can be easily realized.

Below, an example of the configuration will be explained. In the configuration shown in FIG. 14, an image processing system is configured by adding two video memories VM to the configuration shown in FIG. 2, and a plurality of these are connected as a minimum unit. That is, the output of the display memory DM9-1 is connected to the video memory VM8-21, the output of the display memory DM9-2 is connected to the video memory VM8-31, and so on, and the A / D converter 10- is connected. Before inputting 1 to 10-n, a selector (not shown) is provided so that an image of the same TV camera or an image of a different TV camera can be selected and input.

When parallel image processing is executed with this configuration, images of different TV cameras are all input as inputs of the A / D converters 10-1 to 10-n, and the image processing processors 1-1 to 1-1 of the present invention are input. It suffices that 1-n processes the images in the video memories VM8-10 to 8-n0.

On the other hand, when the pipeline image processing is executed, the image processor 1-1 of the present invention processes the image in the video memory VM8-10 and displays the result in the display memory DM.
9-1 and the image processor 1-2 processes the image in the video memory VM8-21 and displays the result in the display memory.
The same process may be performed thereafter, such as transferring to the DM 9-2.

Whether to perform the parallel processing or the pipeline processing as described above is determined by inputting the contents of the video memory for the parallel processing or the video memory for the pipeline processing from within the image processor. Should be selected.

In the second image processing system of FIG. 12, this is the video memory VM8-20 when performing parallel processing from the image processing processor 1-2, and the video memory VM8-20 when performing pipeline processing. Memory VM8-21
It can be realized by issuing an input enable signal to the.

[0133]

According to the present invention, in the image processor for performing image processing, each of the indispensable functional modules including the image input / output control unit and the image memory control unit is integrated into a single chip, thereby realizing the image processing system. Can be downsized and its construction can be facilitated.

Further, by making the video image input / output and the image processing independently operable, the processing capability of the image processing processor can be improved.

Furthermore, according to the present invention, the image memory can be accessed in parallel, and the image recognition speed can be increased.

Further, according to the present invention, in the image processing system using the above image processor, parallel processing and pipeline processing can be performed to improve the system throughput.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an image processor according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an image processing system using the image processing processor shown in FIG.

FIG. 3 is a block diagram showing a configuration of an image input / output unit 2 according to the first embodiment of the present invention.

FIG. 4 is a diagram schematically showing an effective screen area.

FIG. 5 is a timing chart showing an image transfer sequence.

FIG. 6 is a block diagram showing a configuration of a synchronization unit 202 according to the first exemplary embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of an image processing unit 4 according to the first embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a feature extraction unit 5 according to the first embodiment of the present invention.

FIG. 9 is a system control unit 9 according to the first embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 10 is a block diagram showing a configuration of an image memory control unit 3 according to the first embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of an image processing control unit 32 according to the first embodiment of the present invention.

FIG. 12 is an image input / output unit 2 according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 13 is an image input / output unit 2 according to a third embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 14 is a block diagram showing a configuration of another image processing system of the present invention.

FIG. 15 is a diagram schematically showing a configuration of a transfer start register 2.

[Explanation of symbols]

1 ... Image processor, 2 ... Video image input / output unit, 3
... image memory control unit, 4 ... image processing unit, 5 ... feature extraction unit, 6 ... system control unit, 17 ... video timing signal, 18 ... image processing clock.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuya Takahashi 7-1, 1-1 Omika-cho, Hitachi City, Ibaraki Hitachi Ltd. Hitachi Research Laboratory, Ltd. (72) Inventor Manabu Araoka 5-2-1 Omika-machi, Hitachi-shi, Ibaraki Hitachi Ltd. Omika factory

Claims (12)

[Claims] 1. An image processing processor for fetching image data and processing the image data, wherein an image input / output section for inputting and outputting the image data and a control for reading or writing the image data to and from the image memory. An image memory control unit to perform, an image processing unit that processes the image data input from the image input / output unit or the image memory control unit, and outputs the result to the image memory control unit, and a processing result of the image processing unit. Image processing characterized in that a feature extraction unit for extracting a feature amount and a system control unit for designating operation of the image processing processor and mediating access to image data from the system processor are integrated into a single chip. Processor. 2. The image processing unit processes image data,
The result is output to the image memory, and at the same time, the image input / output unit and the feature extraction unit can independently perform image input / output to / from the image memory, feature extraction, and access to the image memory of the system processor in parallel. 2. The image processing processor according to claim 1, wherein each of the unit and the system control unit is provided with means for activating and controlling itself. 3. The image pickup device and the display device operate when the image data is fetched from the image pickup device and a display device for displaying the image data processed by the image processing processor is connected. There is at least one kind of video signal timing and video clock, and there is an image processing clock that operates independently of this video clock, and these video clock and image processing clock are used as operation clocks. An image processor according to any one of claims 1 and 2, characterized in that. 4. The image data is fetched from an image pickup device, and the image input / output unit measures a time interval at which two pieces of image data fetched from the image pickup device are fetched, and a field which constitutes the image data. 4. The image processing processor according to claim 1, further comprising a field calculation unit that performs capturing at predetermined field intervals. 5. A video memory or an image memory is connected, and the image input / output unit transfers image data from the video memory or the image memory in synchronization with a video signal timing of an image pickup device or a display device. In this case, the information processing device further comprises means for setting information to be repeatedly transmitted, and means for controlling the repeated transmission based on this information. An image processor according to any of the claims. 6. An image memory is connected, and when the image processing unit is executing image processing, the image memory control unit has a queue for registering a refresh request from the image memory. The memory control unit registers the refresh request from the image memory in this queue, and after the image processing unit completes the processing of one raster, the number of times of the refresh request registered in this queue,
2. The refresh operation is executed.
The image processing processor according to claim 5. 7. A video memory for storing image data from an image pickup device, a display memory for storing image data to be displayed on a display device, and one or more for storing input images of image processing and image processing results. The image memory according to any one of claims 1 to 7, which is connected to the image memory, the video memory, the display memory, and the image memory, and performs processing and data transfer of image data stored in these memories. And an image processor that operates independently of the first video clock from the image pickup device, and image data is written to the video memory from the image pickup device according to a first video clock. The image data is read out according to the processing clock, and the display memory displays the image data according to the second video clock. The is read out, it is displayed on the display device, and an image processing system characterized by its second said image data according to the image processing clock which operates independently of the video clock is written. 8. The image processing processor as a constituent element of the image processing system according to claim 7, wherein the image input / output unit includes the video memory and the display memory. Processor. 9. A video memory is connected, and the image input / output unit prohibits or permits writing of image data from the image pickup device to the video memory. And an image processor according to any one of items 8 to 8. 10. The image input / output unit in the image processing processor, which is the constituent element, prohibits or permits writing of image data from an image pickup device to the video memory. The image processing system described. 11. An external port of the i-th image processing system and an external port of the j-th image processing system are connected by using a plurality of the image processing systems according to claim 7 or 10. And a means for selecting which of image data from the image pickup device and image data from the external port is input is provided in the image processing processor in each image processing system, and the i-th image processing system Of the image data from the image pickup device to each of the image processing systems by switching the selecting means so that the output data from the display memory can be input to the j-th (j> i) image processing system. To perform parallel processing of image data from different image pickup devices in a plurality of image processing systems, and the means for selecting. In the first image processing system, the image data from the image pickup device is input, but in the kth (k ≧ 2) image processing system, the image data from the external port is input. In the j-th (j> i) image processing system,
An image processing system characterized by inputting output data from a display memory of the second image processing system and performing pipeline processing. 12. When an image pickup device is connected and receives a color video signal from the image pickup device, the image input / output unit outputs a color signal and a luminance signal from the color video signal from the image pickup device. An encoder for separating, a decoder for synthesizing a color video signal from a color signal and a luminance signal, a video memory for storing all or part of image data output from the encoder, and an image stored in the image memory 7. A display memory for storing all or part of data, and claim 1 to claim 6 and claim 8.
And an image processor according to claim 9.