JPH08263234A - Data receiver, control method for the same and printer using the same - Google Patents

Abstract

PURPOSE: To improve the efficiency of reception processing by transferring data in a reception buffer to a memory without performing polling. CONSTITUTION: When the reception of data is started, those data are fetched into the reception buffer. When the data are received, a CPU investigates the contents in the reception buffer, namely, performs polling and when there are any data, length data at the prescribed position of received data are set to a register 26. Next, a comparator 27 is enabled and polling is stopped. Afterwards, the generation of a second interruption request is waited. During this waiting, data are successively received and when difference between a write pointer 17 and a read pointer 18, namely, the amount of received data is made equal with the register 26, a signal showing such a state is outputted from the comparator 27 and becomes the request of interruption to the CPU. When the interruption request is generated, the CPU reads data from the reception buffer and transfers them to a RAM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving device and a control method thereof when data is transmitted between a host device such as a personal computer and peripheral devices.

[0002]

2. Description of the Related Art For transmitting data between a host device such as a personal computer and a peripheral device, for example, when the peripheral device is a printer, a parallel I / F specified by Centronics (hereinafter, Centronics I / F), In the case of a modem etc., RS-232C serial I / F (hereinafter,
It is well known that RS-232C I / F) is widely used.

A configuration example of a printer is disclosed in Japanese Patent Laid-Open No. 58-1.
17036 and JP-A-5-150914. The operation of receiving the transmission data in these conventional techniques will be described with reference to FIG. In the figure, 1 is a CPU, 2 is a RO
M, 3 RAM, 4 Centronics I / F and RS-2
I / F for transmitting data in 1-byte units such as 32 CI / F
F section, 5 is a DMA controller, and 6 is a printing section. R
Areas used as a reception buffer, a print buffer, a write pointer, and a read pointer are set on the AM3. The write pointer and the read pointer (sometimes called the put pointer and the get pointer, respectively) specify the offset address of the reception buffer area.

When data is transmitted to the I / F 4 from an external host device, the I / F 4 interrupts the CPU 1. The CPU 1 reads the data from the I / F 4 in the interrupt process, stores the data in the reception buffer, and increments the write pointer by 1. On the other hand, the main program unit of the CPU 1 fetches data from the position indicated by the read pointer and increments the read pointer by 1. Since the write pointer and the read pointer are initially initialized to 0, the main program section compares the write pointer with the read pointer to determine whether or not there is unacquired data in the reception buffer.

The data fetched from the receive buffer is transferred to the print buffer after being subjected to processing such as font expansion. When all the necessary data is stored in the print buffer, the DMA controller 5 DMA-transfers the data in the print buffer to the printing unit 6 to execute printing.

For the purpose of reducing the number of times of the interrupt processing,
An example in which transmission data is temporarily stored in a FIFO memory consisting of several bytes, and when the FIFO memory is full, the CPU is interrupted and fetched in a reception buffer is disclosed in Japanese Patent Laid-Open No. 3-20.
8121.

Further, a method has been devised in which the transmission data is directly transferred to the reception buffer by DMA transfer and the above interrupt processing is eliminated.

The respective examples are the differences in fetching the transmission data into the receiving buffer, and in any case, the method using the write pointer and the read pointer described above is used for the portion fetching the data from the receiving buffer.

[0009]

In the above-mentioned prior art, it was necessary to poll the status of the receiving buffer for fetching the data stored in the receiving buffer. That is, 1) Read the read pointer and the write pointer. 2) Compare both. 3) When the value of the read pointer is not equal to the value of the write pointer, 1 byte of data is fetched from the address of the reception buffer indicated by the read pointer, and then the read pointer is incremented by 1. If the value of the read pointer is equal to the value of the write pointer, there is no data to be fetched and nothing is done.

The above process must be executed periodically.

This is not a serious problem when the amount of data to be transmitted is relatively small, but when the amount of data to be transmitted is large, such as image data, the 1-byte data as described above is used. If the polling operation is performed for each transmission data, the overhead of the CPU becomes too large, which causes a substantial decrease in communication speed.
This drawback is that, in a device in which a single CPU also performs other control processing as shown in FIG. 9, not only the actual communication speed is lowered, but also the CPU power is wasted for the time of the overhead. As a result, the operation speed of the entire apparatus is lowered.

The present invention has been made in view of the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a data receiving apparatus capable of taking in transmission data without performing a polling operation.

[0013]

[Means for Solving the Problems] and

In order to achieve the above object, the data receiving apparatus of the present invention has the following configuration. That is, the receiving means for receiving the data, the storing means for storing the data received by the receiving means, the determining means for determining that the receiving means has finished receiving the data, and the result of the determination by the determining means. Based on the above, there is provided requesting means for requesting transfer of the data stored in the storing means, and transfer means for transferring the data stored in the storing means to a predetermined storage area in response to a request from the requesting means. .

Alternatively, receiving means for receiving data,
Setting means for setting the data length to be received, storage means for storing the data received by the receiving means,
A determination unit that determines whether the data length set in the setting unit matches the amount of received data, and requests transfer of the data stored in the storage unit based on the result of the determination made by the determination unit. The data processing device further comprises requesting means and transfer means for collectively transferring the data stored in the storage means to a predetermined storage area for the data length set in the setting means in response to a request from the requesting means.

Alternatively, a control CPU, an interface for receiving data, a reception buffer for storing the received data, a first pointer and a second pointer for pointing an arbitrary position in the reception buffer, and the interface. The data read via the receiving buffer is stored in the position designated by the first pointer, and the data is read from the receiving buffer. The data storing means increases the value corresponding to the amount of data stored in the first pointer. In this case, second pointer adding means for increasing the second pointer by a value corresponding to the read data amount; and the first pointer
Remaining amount calculating means for obtaining the difference between the pointer value and the second pointer value, a data length setting register for setting a desired value, a setting value of the data length setting register and an output value of the remaining amount calculating means. And if they match, the CPU
An interrupt requesting means for requesting an interrupt to the device, and a reading means for reading data from the reception buffer and transferring the data to a predetermined storage area when triggered by the interrupt by the interrupt requesting means.

The printing apparatus of the present invention has the following structure. That is, it is provided with the data receiving device and a printing unit for printing out the data transferred to the predetermined area by the data receiving device.

The data receiving method of the present invention has the following configuration. That is, a setting step of setting the data length to be received, a storing step of storing the received data in a memory, and a determination of determining whether the data length set in the setting step and the amount of the received data match And a request step for requesting the transfer of the data stored in the memory based on the result of the determination by the step and the determination step, and the data stored in the memory is set according to the request by the request step. And a transfer step of transferring the data length set in the step to a predetermined storage area.

[0018]

[First Embodiment] An embodiment of the present invention will be described below. FIG.
FIG. 1 is a block diagram of a printer device incorporating a data receiving device embodying the present invention. Reference numeral 10 in the figure denotes a CPU, which controls the entire apparatus, and has a 16-bit (2-byte) data bus and 24-bit (16-Mbyte memory space).
Address bus. 11 is a ROM / RAM
The ROM section stores programs, font data, etc., and the RAM section is used as various work areas in addition to the print buffer. A printing unit 12 includes a motor, a print head, a circuit for driving them, and the like. Reference numeral 20 denotes a timer interval circuit which can be arbitrarily set by the CPU 10, and its output is connected to the CPU bus as a first interrupt request signal to the CPU 10. Interrupt processing corresponding to the interrupt request signal (hereinafter referred to as a timer interrupt)
Then, in addition to measurement processing such as time measurement necessary for controlling the printing unit 12, processing for monitoring the state of the reception buffer is performed. Reference numeral 13 is a parallel I / F conforming to the Centronics I / F. Reference numeral 16 denotes a RAM used as a reception buffer, which has a capacity of 64 Kbytes in this embodiment.

In FIG. 1, the RAM element is a ROM / RAM 11
It is equipped with both RAM and RAM16, but 1 unit of R
When configuring the system with only AM elements, ROM /
The RAM 11 may include only the RAM 16 without including the RAM element. In this case, a part of the RAM 16 is used as a reception buffer, and the other part is used as various work areas. Reference numeral 14 is a DMA controller, which when the transmission data arrives in the parallel IN 13, the RAM 16
The DMA transfer of the transmission data is performed. Also,
It is also used for DMA transfer of the data to the print head (not shown) of the printing unit 12 when the print buffer unit of the ROM / RAM 11 has enough data.

Reference numerals 17 and 18 are a write pointer and a read pointer, each of which is composed of a counter circuit or the like. The DMA transfer is performed at an address pointed by the write pointer 17 offset from the base address set in the DMA controller 14. Further, the DMA controller 14 is configured so that the pointer value of the write pointer 17 is incremented by 1 every time the transfer data is DMA-transferred. Reference numeral 15 is a receive buffer monitoring circuit including a data length setting register 26, and a write pointer 1
The CPU 10 is interrupted according to the result of comparison between 7 and the value of the data length setting register 26.
The reception buffer monitoring circuit 15 also includes a circuit that increments the pointer value of the read pointer 18 by 1 when reading the reception buffer. That is, the write pointer 17
The read pointer 18 constitutes a so-called ring buffer as a reception buffer.

A buffer full determination circuit 19 compares the pointer values of the write pointer 17 and the read pointer 18 in order to prevent overflow of the reception buffer, and when the difference exceeds a certain value, the parallel I / F 13 is provided. B
Assert the USY signal to prevent further data transmission from the host device. More specifically, rather than letting the BUSY signal remain asserted, 0.1 seconds to 1 second
It negates for a short time every second. This is because if the BUSY signal is left asserted for a long time, the host device causes a timer out and abandons data transmission. Therefore, the fixed value is set to a value slightly smaller than the total capacity of the reception buffer. In this embodiment, the total capacity of the receiving buffer is 64 Kbytes,
The above-mentioned fixed value may be set to, for example, 62 Kbytes = F800h. When the data acquisition from the reception buffer progresses and the difference between the two pointers becomes equal to or less than a predetermined value (for example, 14 Kbytes = 3800 h), the BUSY signal is negated. In addition to this, the BUSY signal can be arbitrarily asserted / negated by the CPU 10 by software.
Not only the BUSY signal but also all status signals from the printer device to the host device can be arbitrarily asserted / negotiated by the software from the CPU 10 in addition to being automatically set by the hardware. The write pointer 17 and the read pointer 18 are also based on an instruction from the CPU 10 when the device is started up.
Can be initialized to 0.

FIG. 2 shows a detailed block diagram of the reception buffer monitoring circuit 15. In the figure, reference numeral 31 is an address comparator, which compares the output signal of the read pointer address generation circuit 21 with the address signal on the CPU bus when there is an operation to read the memory on the CPU bus, and outputs a high signal when they match. The level is output to the AND gate 22.

The read point address generation circuit 21
The reception buffer base address setting circuit 23 and the output of the read pointer 18 are connected to generate a 24-bit address signal. When the reception buffer has a capacity of 64 Kbytes, the number of bits of the read pointer 18 (and the write pointer 17) is 16 bits. Therefore, the reception buffer base address setting circuit 23 sets the remaining upper 8 bits, Both are combined to generate a 24-bit signal. The added 8-bit address information is the same as the upper 8 bits of the base address set in the DMA controller 14 described above. Here, the address information set in the reception buffer base address setting circuit 23 may be fixed in terms of the circuit. However, the address information can be set appropriately by the CPU 10 within a range that does not overflow the address area of the RAM 16. Good. In this case, it must correspond to the base address set in the DMA controller 14.

Reference numeral 24 is a comparator for comparing whether the pointer values of the write pointer 17 and the read pointer 18 are equal, and outputs a high level to the AND gate 22 when they are not equal. The output of the AND gate 22 is connected to the read pointer 18. Read pointer 18
In the above, the pointer value is incremented by 1 in synchronization with the rising edge of the output signal of the AND gate 22. Therefore, the read pointer 18 increases by 1 at the end of the read access to the address pointed to by the read pointer in the receive buffer when there is unacquired receive data in the receive buffer, and when the receive buffer is empty. Does not move the pointer value.

Reference numeral 25 is a subtraction circuit for calculating the consumption amount of the reception buffer, and specifically, subtracts the pointer value of the read pointer 18 from the pointer value of the write pointer 17. Note that, due to the nature of the ring buffer, it does not care whether or not a borrow has occurred as a result of the operation. Reference numeral 26 is a data length setting register, which is a 16-bit write register accessible from the CPU 10. Reference numeral 27 is a comparator that compares the output values of the subtraction circuit 25 and the data length setting register 26. When the set value of the data length setting register 26 is equal to or greater than (equal to or greater than) the output value of the subtraction circuit 25, Output a high level signal. The comparator 27 is the comparator enable setting register 2
The operation can be enabled / disabled from the CPU 10 via 8, and when the operation is disabled, a low level signal is always output regardless of the comparison result. Reference numeral 29 is a flip-flop circuit which is set to a low level at the rising edge of the output of the comparator 27 and is cleared to a high level by a clear signal from the interrupt request signal clear port 30. The output of the flip-flop circuit 29 is the second output to the CPU 10.
The interrupt request signal (low active) is connected to the CPU bus. The interrupt request signal port 30 outputs a clear signal, that is, a clear pulse to the flip-flop circuit 28 once when the CPU 10 accesses the port (eg, a write operation with dummy data).

Next, the overall operation will be described with reference to the flow charts of FIGS. First, as initialization processing, the second interrupt request signal output from the flip-flop circuit 29 is masked and the comparator 27 is disabled in step S30.
When data is transmitted to the parallel I / F 13 in this state, the DMA controller 14 performs DMA transfer to a predetermined address of the RAM 16 (reception buffer). CPU10
Executes the processing after step S31 in the interrupt processing by the timer interrupt.

First, in step S31, the state of the receiving buffer is polled, and if there is data to be taken into the receiving buffer, the read pointer 1 is read in step S32.
1-byte data is read from the address indicated by the pointer value of 8. Next, in step S33, the type of the data is determined.
In the case of a byte character code or the like, another byte is read if necessary, the font of the character data is expanded in step S35, and the result is stored in ROM / RA.
Write to the print buffer 112 of M11.

On the other hand, if it is determined in step S33 that the data is not character data, the subsequent data is read in one to several bytes in step S36, and it is determined in step S37 whether it is command data or image data. If it is command data, the parameter portion of several bytes following is read in step S38, and the command is executed in step S39. The data acquired from the receive buffer is
The above process is repeated between characters and character data.

In the case of image data, the format of the data stream is, as shown in FIG. 5, a header of image data of several bytes at the beginning, then a data length (2 bytes), and finally image data of bitmap. Has become. The format of the image data stream may be a format other than the above. For example, the data length portion may be pixel number data of the image data portion. In this case, it is very easy to calculate the data length from the pixel number data.

If the fetched data is the header of the image data, the 2-byte data length that follows is read in step S40. Then, in step S40, the content of this data length is written in the data length setting register 26, and in step S42, the operation of the comparator 27 is enabled. Then, in step S43, an instruction to stop the polling operation is issued. Specifically, ROM /
Off is written in the polling operation flag 111 set in the RAM section on the RAM 11. The polling operation flag is referred to during the timer interrupt, and whether the polling operation is performed or not is determined according to its on / off. Of course, if the timer interrupt is used only for the polling operation, the first interrupt request signal itself from the timer interval circuit 20 may be masked. Finally, in step S44, the masking for the second interrupt request is released. At this point, the CPU 10 stops polling the reception buffer and concentrates on other processing.

When all the image data, that is, the data length is transmitted from the transmission source, the write pointer 17
Becomes the same as the value set in the data length setting register, the comparator 27 operates, and the second interrupt request signal is output to the CPU 10 via the flip-flop circuit 28. CPU 1 receives the interrupt request signal
0 starts an interrupt process. The procedure is shown in FIG.

First, in step S50, a dummy write is performed to the interrupt request signal clear port to clear the second interrupt request signal. Next, in step S51, the data of the data length is loaded from the reception buffer into the ROM / RAM 11 at once by an arbitrary method such as block transfer or DMA transfer. That is, the image data in the reception buffer is transferred to the print buffer unit. Then, in step S52, the comparator 27 is disabled, and in step S53, the mask of the interrupt request is set again. Finally, in step S54, the polling operation flag 111, which is set to OFF in step S43 of FIG. 3, is turned on to instruct restart of the polling operation, and the interrupt processing is ended.

By the way, the above operation flow causes no problem even if all the image data has already been transmitted and stored in the reception buffer when the masking of the second interrupt request is released in step S44. Operate. In this case, when the comparator 27 is enabled in step S42, the output of the comparator 27 becomes high level, and the flip-flop circuit 29 outputs a low level signal. That is, when the masking of the second interrupt request is released in step S44, the interrupt process from step S50 is immediately executed. Then, in the next timer interrupt, the polling operation flag 111 is turned on, so that the status of the receiving buffer is polled again in step S.
The processing from 31 is repeated.

As described above, according to this embodiment, when the data amount is large and it is possible to know the data amount in advance like the image data, the polling operation to the receiving buffer can be omitted. Therefore, the CPU overhead time can be eliminated accordingly.

[0035]

[Second Embodiment] In the first embodiment, if the capacity of the reception buffer is, for example, 64 Kbytes and the size of one block of the received data exceeds that size, the image data will not be transmitted. When it is finished, the CPU 10 cannot be notified of this by an interrupt. Of course, increase the capacity of the receive buffer, write pointer 1
7. If the number of bits of the related register group such as 7, the read pointer 18 and the data length setting register 27 is matched with the capacity of the receiving buffer, it is possible to transmit large image data by the apparatus of the above embodiment.

However, increasing the capacity of the reception buffer naturally increases the cost of the apparatus, and therefore it may not be easy to adopt. The present embodiment has been made in view of this point, and is capable of handling larger transmission data without increasing the capacity of the reception buffer.

In this embodiment, the size of the image data is expanded up to 16 Mbytes. Therefore, as shown in FIG. 8, the data length field of the image data stream is extended to 3 bytes. Now, the overall operation of this embodiment will be described with reference to the flowcharts of FIGS. 6 and 7.

FIG. 6 shows step S of FIG. 3 in the first embodiment.
It is a flowchart of the part corresponding to 37 or less. Since steps S30 to S39 are exactly the same, description thereof will be omitted.

If it is determined in step S37 that the data is image data, the data length of 3 bytes is read in step S60. Then, in step S61, the remaining amount of the image data is calculated. Since 1 byte has not yet been fetched from the reception buffer here, the remaining amount is the data length value itself. In step S62, it is determined whether the remaining amount is larger than the maximum capacity until the reception buffer becomes full, that is, F800h (= 62K). If it is less than or equal to the maximum capacity, the value of the remaining amount is set in the data length setting register 26 in step S63. On the other hand, if the maximum capacity is exceeded, the maximum capacity value, that is, F800h is set in the data length setting register 26 in step S63. Then, the comparator 27 is enabled in step S63, an instruction to stop the polling operation is issued in step S64, and finally the masking of the second interrupt request is released in step S65.

FIG. 7 is a flowchart of the interrupt processing for the second interrupt request in the second embodiment. In the interrupt processing, first, the second interrupt request signal is cleared in step S70, and the data length setting register 26 is cleared in step S71.
Data will be fetched from the receive buffer for the amount set in.
Then, in step S72, the remaining amount is updated. Specifically, a value obtained by subtracting the set amount from the current remaining amount is set as the new remaining amount.

Next, in step S73, it is determined whether or not the updated remaining amount is zero. If it is 0, the comparator 27 is disabled in step S74, and the mask of the interrupt request is set again in step S75.

Finally, in step S76, the restart of the polling operation is instructed, and the interrupt processing is ended.

On the other hand, when the updated remaining capacity is not 0, the remaining capacity in step S77 is compared with the maximum capacity. If the remaining amount is equal to or more than the maximum capacity, step S7
At 8, the value of the maximum capacity is set in the data length setting register 26, and the interrupt processing ends. If the remaining amount is smaller than the maximum capacity, the value of the remaining amount is set in the data length setting register 26 in step S79, and the interrupt process ends. In short, when the size of the image data to be transmitted is less than the maximum capacity, the data is captured by one interrupt processing as in the case of the first embodiment, but when the size exceeds the maximum capacity, the maximum capacity (= 62 Kbytes). ) Is accumulated in the reception buffer, a second interrupt is applied, and the whole is divided into several times to capture the image data.

As described above, according to the present embodiment, it is possible to omit the polling operation to the receiving buffer even when the image data exceeding the capacity of the receiving buffer provided is received.

That is, in the embodiment, if necessary, the transmission data can be fetched by omitting the polling operation to the reception buffer. Therefore, that much CP
Since the overhead time of U can be eliminated, a substantial increase in communication speed is realized as a result. Further, in a device in which a single CPU controls the entire device as in the embodiment, since the CPU can be used efficiently, it has an excellent effect that the operation speed of the entire device can be improved. Is. Although the first and second embodiments have been described by using the image data as an example, the present invention is not limited to this, and if the data length can be known, it may be the case of character data or command information. However, the effect is the same. The same effect can be expected even if the serial I / F is used instead of the parallel I / F. Furthermore, although the present invention is suitable for a printer device, it is needless to say that the present invention is not necessarily limited to this and can be applied to other peripheral devices or host devices.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0047]

As described above, the data receiving apparatus according to the present invention has an effect that it is possible to take in transmission data without performing a polling operation and realize high-speed data transmission.

[0048]

[Brief description of drawings]

FIG. 1 is a block diagram of a printer device incorporating a data receiving device according to the present invention.

FIG. 2 is a detailed block diagram of a reception buffer monitoring management unit.

FIG. 3 is a flowchart illustrating an operation in the first embodiment.

FIG. 4 is a flowchart illustrating the operation of the first embodiment.

FIG. 5 is a diagram illustrating a format of an image data stream.

FIG. 6 is a flowchart illustrating the operation of the second embodiment.

FIG. 7 is a flowchart illustrating the operation of the second embodiment.

FIG. 8 is a diagram illustrating a format of an image data stream in the second embodiment.

FIG. 9 is a diagram illustrating a conventional technique.

[Explanation of symbols]

 10 CPU 11 ROM / RAM 12 Printing Unit 13 Parallel I / F 14 DMA Controller 15 Reception Buffer Monitoring Circuit 16 RAM (Reception Buffer) 17 Write Pointer 18 Read Pointer 19 Buffer Full Judgment Circuit 20 Timer Interval Circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Sohei Tanaka, 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor, Hiroshi Uemura 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Incorporated (72) Inventor Nobuyuki Tsukada 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (20)

[Claims] 1. A receiving means for receiving data, a storing means for storing the data received by the receiving means, a determining means for determining that the receiving of the data has been completed by the receiving means, and a determination by the determining means. Requesting means for requesting the transfer of the data stored in the storing means based on the result of 1. and transfer means for transferring the data stored in the storing means to a predetermined storage area in response to the request from the requesting means. A data receiving apparatus comprising: 2. The determining means compares the data indicating the length of the data received by the receiving means with the amount of the received data to determine the end of reception. The data receiving device described. 3. A receiving means for receiving data, a setting means for setting a data length to be received, a storage means for storing the data received by the receiving means, and a data length set in the setting means. Determining means for determining a match with the amount of received data, requesting means for requesting transfer of the data stored in the storing means based on the result of the determination by the determining means, and requesting by the requesting means. Accordingly, the data receiving device is provided with a transfer unit that collectively transfers the data stored by the storage unit to a predetermined storage area for the data length set by the setting unit. 4. The transfer means is controlled by a CPU,
4. The data receiving device according to claim 1, wherein the requesting unit is an interrupt request to the CPU. 5. A determination means for determining the type of the received data, and a polling means for transferring the received data to the predetermined storage area while detecting the presence or absence of the received data when the received data is not image data. The data receiving device according to any one of claims 1 to 4, further comprising: 6. When the data length that can be set by the setting means is shorter than the data length to be received, the control means further controls to divide and transfer the data length that can be set by the setting means. The data receiving device according to any one of claims 2 to 5, wherein 7. A setting step of setting a data length to be received, a storing step of storing the received data in a memory, and a matching of the data length set in the setting step with the amount of the received data. A determination step of determining, a request step of requesting transfer of the data stored in the memory based on a result of the determination in the determination step, and a data stored in the memory in response to the request of the request step. And a transfer step of transferring the data length set in the setting step to a predetermined storage area. 8. The transfer process is controlled by a CPU,
8. The data receiving method according to claim 7, wherein the request step is an interrupt request to the CPU. 9. A determination step of determining the type of the received data, and a polling step of transferring the received data to the predetermined storage area while detecting the presence or absence of the received data when the received data is not image data. The data receiving method according to claim 7, further comprising: 10. If the data length that can be set in the setting step is shorter than the data length to be received,
10. The data receiving method according to claim 7, further comprising a control step of controlling so as to divide and transfer the data length that can be set by the setting step. 11. A printing apparatus, comprising: the data receiving apparatus according to claim 1; and a printing unit that prints out the data transferred to a predetermined area by the data receiving apparatus. 12. A control CPU, an interface for receiving data, a reception buffer for storing the received data, a first pointer and a second pointer for pointing an arbitrary position in the reception buffer, and the interface. The data received via
Data storage means for storing the data at the position indicated by the pointer and increasing the first pointer by a value corresponding to the stored data amount, and when the data is read from the reception buffer, corresponds to the read data amount. A second pointer adding means for increasing the second pointer by an amount corresponding to the value, a remaining amount calculating means for calculating a difference between the value of the first pointer and the value of the second pointer, and a data length capable of setting a desired value. The setting register, the setting value of the data length setting register and the output value of the remaining amount calculating means are compared, and if they match, an interrupt requesting means for requesting an interrupt to the CPU, and the interrupt request A data receiving device comprising: a reading unit that reads data from the reception buffer and transfers the data to a predetermined storage area when an interruption by the unit is triggered. 13. A polling means for checking the presence / absence of data in the reception buffer by comparing the first pointer and the second pointer, and if there is data, polling means for fetching transmission data from the reception buffer. 13. The data according to claim 12, further comprising polling stop means for stopping data acquisition by the polling means, and controlling the interrupt request means to read data when polling is stopped. Receiver. 14. The data receiving apparatus according to claim 12, wherein the value set in the data length setting register is a value based on length information of transmission data. 15. The data receiving apparatus according to claim 12, wherein the value set in the data length setting register is a substantially maximum capacity of the receiving buffer. 16. The method according to claim 12, further comprising DMA transfer means for controlling DMA transfer, wherein the data received via the interface is transferred to the reception buffer by the DMA transfer means. The data receiving device as described in 1. 17. The interface is parallel I /
17. The data receiving device according to claim 12, wherein the data receiving device is F. 18. The interface is a serial I / O
17. The data receiving device according to claim 12, wherein the data receiving device is F. 19. The data receiving device according to claim 12, wherein the data receiving device is built in a printer device. 20. The data receiving device is built in a host device.
8. The data receiving device according to any one of 8.