JPH08262473A - Liquid crystal display device and device having semiconductor element - Google Patents

Abstract

PURPOSE: To provide a liquid crystal display device with which the sure assurance of conduction by the anisotropic conductive materials between the wirings of a substrate and a semiconductor element is possible. CONSTITUTION: The driver LSI of the liquid crystal display element is fixed to the substrate of a liquid crystal display panel and the terminals of the driver LSI are connected to the wirings on the substrate of the liquid crystal display panel by the anisotropic conductive materials. The driver LSI contains a pull- down resistor Rdown connected to a terminal in which substantially no current flows at the time of normal use in order to prevent the incidence that the terminals are insulated by naturally oxidized films. This terminal is energized at the time of turning on a power source. The joint parts of the wirings and the anisotropic conductive materials and the joint parts of the terminals and the anisotropic conductive materials are stabilized at low resistance by this energization.

Description

Detailed Description of the Invention

[0001]

This invention relates to a chip-on-glass (C
More specifically, the present invention relates to a liquid crystal display device configured by connecting a semiconductor chip for driving a liquid crystal display element to wiring on a substrate with an anisotropic conductive material.

[0002]

2. Description of the Related Art A COG type liquid crystal element is formed by forming a wiring on one substrate which constitutes a liquid crystal display panel and connecting a driving semiconductor chip (driver LSI) to this wiring. . As the mounting method of the driver LSI, a wire bonding method, a face-down method,
A method using an anisotropic conductive material is known.

A method using an anisotropic conductive material is a driver L
Anisotropic conductivity of SI (high conductivity in the direction perpendicular to the substrate,
This is a method of fixing to the substrate with a resin material having a property of exhibiting low conductivity in the horizontal direction of the substrate) and connecting the terminals of the driver LSI to the opposing wirings. According to this method
Process of fixing driver LSI to substrate and driver LSI
It is possible to simultaneously perform the process of connecting the terminals of
The number of manufacturing steps can be reduced.

[0004]

When fixing the driver LSI to the substrate, a natural oxide film is formed on the surface of the wiring on the substrate and the terminals of the driver LSI. Therefore, the wiring and the terminal may be connected by the anisotropic conductive material while the natural oxide film remains. In addition, a natural oxide film may be formed due to aging. However, with respect to the terminal in which almost no current flows in the used state, the natural oxide film remains in the used state, and the terminal is in an electrically open state, and the voltage becomes unstable.

For example, almost no current flows through the terminal to which the reference voltage of the sampling capacitance of the driver LSI is supplied. Therefore, if the natural oxide film remains on this terminal or the corresponding wiring, the sampling capacitance may be in an electrically floating state, and sampling may not be performed accurately.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a liquid crystal display device capable of reliably ensuring electrical continuity between an interconnection of a substrate and a terminal of a semiconductor element by an anisotropic conductive material. And

[0007]

In order to achieve the above object, a liquid crystal display device according to a first aspect of the present invention includes a liquid crystal display panel including a substrate on which a plurality of wirings are formed,
A driving semiconductor element that has a plurality of terminals facing the plurality of wirings, has a built-in pull-down means that pulls down at least one of the terminals, and drives the liquid crystal display panel; and the driving semiconductor element on the substrate. An anisotropic conductive material that fixes and connects the terminal to the wiring,
The terminal is energized at least when the power is turned on.

A device according to a second aspect of the present invention comprises a substrate on which a plurality of wirings are formed and a plurality of terminals opposed to the plurality of wirings, and is substantially insulated from other terminals. Connecting a predetermined terminal to another terminal, at least a semiconductor element having a built-in energization circuit for energizing the predetermined terminal when the power is turned on, and fixing the semiconductor element to the substrate and connecting the plurality of terminals to the plurality of terminals. An anisotropic conductive material connected to the wiring, and stabilizes the joint between the wiring and the anisotropic conductive material and the joint between the terminal and the anisotropic conductive material with low resistance by the energization. It is characterized by

[0009]

According to this structure, the pull-down means or the energizing means always causes a current to flow through the terminals. When an insulating thin film such as a natural oxide film is formed on the terminal and / or the wiring, this energization causes a voltage to be applied to the insulating film and the conductive particles contained in the anisotropic conductive material to vibrate. However, the insulating film is destroyed and stabilized in a low resistance state. Therefore, even a terminal in which a current hardly flows in the normal state can be reliably connected to the wiring with low resistance.

[0010]

EXAMPLE A COG type liquid crystal display device according to an example of the present invention will be described below. This liquid crystal display device has a liquid crystal display panel 11 as shown in a plane in FIG. 1 and a cross section in FIG.
Is provided. The liquid crystal display panel 11 includes a pair of substrates 1
Sealing material 14 for bonding the substrates 2 and 13 and the substrates 12 and 13 together
And a liquid crystal 15 enclosed between both substrates 12 and 13. The substrate 12 is formed larger than the substrate 13, and includes pixel electrodes, switching elements (TFTs, etc.), address lines (gate lines) 16, data lines (X1 to X1).
X580) 17A, 17B, etc. are formed in the display area, and the scanning side driver connection wiring 18, the signal side driver connection wiring 19A, which are formed of an aluminum pattern or the like, are formed on the sides.
19B is formed. The wirings 18, 19A and 19B are connected to an external circuit via a flexible circuit board (FCB) 24 and the like. Further, a counter electrode, a color filter and the like are formed on the substrate 13.

Further, on the substrate 12, a scanning side driver (address driver LSI) 20 and two signal side drivers (data driver LSIs) 21A and 21B are arranged. The drivers 20, 21A, 21B are provided with terminals (connection pads, electrodes) 22 on the lower surface and fixed to the substrate 12 by an anisotropic conductive material (anisotropic conductive adhesive) 23, as shown in the cross section in FIG. ing. The anisotropic conductive material 23 is configured by adding conductive particles coated with a polymer or the like in a resin layer, and conducts a current in the vertical direction with respect to the substrate 12 but supplies a current in the horizontal direction. Cut off. Therefore, the terminals 2 formed on the lower surface of the driver 20, 21A, 21B
2 and wiring 18, 19A, 19B or address line 1
6, the data lines 17A and 17B facing each other are connected by the anisotropic conductive material 23.

Next, the internal structure of the driver will be described with reference to FIG. 3 by taking the signal side driver (data driver) 21A as an example.

As shown in FIG. 3, the signal side driver 21A comprises a timing generation circuit 31, a shift register 32, a level shifter 33, a sample hold circuit 34, and an output buffer 35. The timing generation circuit 31
The start signal STR and the basic clock MCLK are supplied from the outside, and each signal is output to the shift register 32 and the sample hold circuit 34.

The shift register 32 has 280 stages of registers, and when the start signal STR is input,
Start signal S every time the basic clock MCLK is input
The TR is shifted and sequentially output to the level shifter 33.
The output XOUT of the final stage register is the signal side driver 21.
B is supplied as a start signal.

The level shifter 33 includes a shift register 32.
The voltage of the signal input from is boosted and sequentially output as a sample signal for causing the sample hold circuit 34 to sample the video signal. Sample and hold circuit 3
4 is RGB video signal, sampling reference signal VDD
C is input, and the video signal is sampled and held each time a sample signal is input and output to the output buffer 35. The output buffer 35 has a clear signal CLR, an output enable signal OE, a gate signal Vg, and a power supply voltage VDD.
A, VBBA, and VBBC are supplied, and the data lines X1 to X2 are supplied in accordance with the sample value of the sample hold circuit 34.
Drive 80.

The sample and hold circuit 34 and the output buffer 35 are constructed, for example, as shown in FIG.

That is, the sample hold circuit 34 includes an analog switch ASW1 and a sampling capacitor C1. The output buffer 35 is an operational amplifier O with a gain of 1.
P, a capacitor Cp for preventing oscillation, a P-channel transistor Ta, and an N-channel transistor T as a constant current source
b1, an analog switch ASW2, a reset N-channel transistor Tb2, and the like. The sample hold circuit 34 and the output buffer 35 are provided with the circuit having the configuration shown in FIG. 4 for each of the data lines X1 to X280, and FIG. 4 shows only the configuration for the data line X1.

The analog video signal IN of RGB is input to the analog switch ASW1 and the analog switch ASW1 is input.
W1 is turned on when the high-level sample signal SWP1 from the level shifter 33 is input, and outputs the video signal IN as the video signal IN1 to the sampling capacitor C1.

The sampling capacitor C1 is used for the video signal IN1.
It is charged by and is output to the analog switch ASW2 via the operational amplifier OP and the P-channel transistor Ta.

The analog switch ASW2 is supplied with a write signal OE which is at a high level only for a predetermined period of one horizontal scanning period. When the high-level write signal OE is input, the analog switch ASW2 is turned on, and the voltage corresponding to the voltage held in the sampling capacitors C1 to C280 via the operational amplifier OP and the P-channel transistor Ta is used as data for the signal line X1. Output to.

As shown in FIG. 5, the sampling capacitors C1 to C280 of the sample and hold circuit 34 have one end connected to the corresponding analog switch SWP1 to SWP280 and the other end connected to a common line. The common line is connected to the terminal TDDC to which the sampling reference voltage VDDC is supplied. The common line is physically composed of, for example, a semiconductor substrate which constitutes this driver LSI, and the sampling reference voltage VDDC is a substrate voltage. The resistance value is 5 KΩ to 50 at a position electrically closer to the terminal TDDC than other circuits, that is, a side closer to the sampling capacitors C1 to C280.
One end of the resistor R1 of about KΩ is connected, and the other end of the resistor Rdown is connected to the ground terminal TSS to which the ground voltage VSS is applied.

When the video signal is sampled, charge transfer occurs in the common line 41, but the common line 41
Current flows to the wiring 19A from the terminal TDDC,
Alternatively, almost no current flows from the wiring 19A to the common line 41 via the terminal TDDC. That is, when the resistor Rdown is not provided, almost no current flows between the terminal TDDC and the wiring 19A. Therefore, even if the natural oxide film exists on the surface of the wiring 19A or the terminal 22 and the junction has a high resistance, that state is maintained.
Therefore, the common line 41 is opened, the voltage of the common line 41 becomes unstable, and the sampling capacitance C
There is a possibility that the video signal sampling by 1 to C280 becomes incomplete and display unevenness occurs.

However, according to this embodiment, the terminal TDDC
Since the resistor Rdown is connected between TSS and TSS, a current flows through the resistor Rdown. Therefore, a natural oxide film formed on the surface of the wiring 19A or the surface of the terminal 22, that is, the anisotropic conductive material 23 and the wiring 19A or the terminal 22.
The voltage between VDDC and VSS is applied to the junction of, the current flows, and the junction becomes stable. This is because the voltage between VDDC and VSS causes the natural oxide film to cause a kind of dielectric breakdown, and the conductive particles in the anisotropic conductive material 23 vibrate to destroy the natural oxide film. . Therefore, the common line 41
The reference voltage VDDC is surely applied to the sample hold circuit 34, and the sample hold circuit 34 accurately samples the video signal.

The normal terminal 22 is internally connected to a positive power supply for logic, a positive power supply for analog, a ground power supply, etc. through a diode, a resistor, a logic circuit, etc., and a current flows to the terminal 22 during operation. Bonding is stable. However, when the natural oxide film is formed on a terminal that is independent or insulated from other terminals, or the natural oxide film is formed on the corresponding wiring, like the reference line 41 described above, The natural oxide film remains. However, according to this embodiment, the terminal is pulled down, and a current flows through the terminal when the power is turned on. Therefore, the conduction between the terminal and the wiring can be reliably ensured. Further, since the pull-down resistor Rdown is arranged at the position closest to the terminal, it is possible to surely conduct electricity.

The circuit configuration for pulling down the terminal and energizing the terminal is not limited to the resistance element Rdown shown in FIG. For example, as shown in FIG. 6, a capacitive element Cdown may be used. If the capacitive element Cdown is used, a current flows only when the power is turned on, so that an increase in current consumption can be suppressed.
Alternatively, an active element may be used as a load that pulls down the terminal.

As the anisotropic conductive material 23, any known structure can be used. For example, JP-A-3-7406
3, a conductive film is formed on the surface of resin fine particles, and the outer surface of the conductive film is coated with a resin having a low melting point to form connection fine particles.
Disclosed is an anisotropic conductive material in which these connecting particles are mixed with an insulating adhesive in a state where they are in contact with each other and are arranged in a plane. Also in this invention, the anisotropic conductive material is sandwiched between the substrate 12 and the driver chips 20, 21A, and 21B, and thermocompression bonding is performed.
Data lines 17A, 17B, connection wirings 18, 19A,
19B and the terminals 22 on the lower surfaces of the driver chips 20, 21A and 21B can be connected.

In the above embodiment, the liquid crystal display element may be of a simple matrix (passive matrix) type. In addition, the driver LSI for driving the liquid crystal display element is not limited to the case where the wiring of the substrate is connected using the anisotropic conductive material,
It is applicable when connecting an arbitrary semiconductor element to wiring on an arbitrary substrate using an anisotropic conductive material. Further, the case where the natural oxide film is formed on the surface of the terminal and the wiring has been described as an example, but the same can be applied to the case where another insulating thin film is formed.

[0028]

As described above, according to the present invention, a terminal which is substantially independent of or insulated from other terminals and in which a current hardly flows is pulled down at a position close to the terminal. Therefore, at least when the power is turned on, a current flows through the terminal, and the junction between the terminal and the anisotropic conductive material or between the wiring and the anisotropic conductive material is stable in a low resistance state. Therefore, the bonding reliability can be improved.

[Brief description of drawings]

FIG. 1 is a plan view showing a structure of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a structure of a liquid crystal display device according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a signal side driver (data driver L shown in FIG.
FIG. 3 is a circuit diagram showing an example of the configuration of (SI).

FIG. 4 is a circuit diagram showing a configuration example of a sample hold circuit and an output buffer shown in FIG.

FIG. 5 is a diagram showing a configuration example of a pull-down circuit.

FIG. 6 is a diagram showing another configuration example of a pull-down circuit.

[Explanation of symbols]

11 ... Liquid crystal display panel, 12, 13 ... Substrate, 14 ...
Sealant, 15 ... Liquid crystal, 16 ... Address line, 1
7A, 17B ... Data line, 18 ... Scan side driver connection wiring, 19A, 19B ... Signal side driver connection wiring, 20 ... Scan side driver (address driver), 2
1A, 21B ... Signal side driver (data driver),
22 ... Terminal (electrode), 23 ... Anisotropic conductive material, 24 ...
Flexible circuit board, 31 ... Timing generation circuit,
32 ... Shift register, 33 ... Level shifter, 34 ...
・ Sample and hold circuit, 35 ・ ・ ・ Output buffer, 41 ・
..Common lines, C1 to C280 ... Sampling capacity,
Rdown ・ ・ ・ Pulldown resistance, Cdown ・ ・ ・ Pulldown capacitance

Claims (6)

[Claims] 1. A liquid crystal display panel comprising a substrate on which a plurality of wirings are formed, a plurality of terminals facing the plurality of wirings, and a built-in pull-down means for pulling down at least one of the terminals. A driving semiconductor element for driving the display panel; and an anisotropic conductive material for fixing the driving semiconductor element to the substrate and connecting the terminal to the wiring, and energizing the terminal at least when the power is turned on. Liquid crystal display device characterized by. 2. The driving semiconductor device includes a sampling circuit, the plurality of terminals include a ground terminal and a reference voltage terminal for supplying a sampling reference voltage to the sampling circuit, and the pull-down means includes the reference voltage. The liquid crystal display device according to claim 1, comprising a load that connects a terminal and the ground terminal. 3. The liquid crystal display device according to claim 1, wherein the pull-down means establishes a connection between the terminal and the wiring by the anisotropic conductive material. 4. The liquid crystal display device according to claim 1, wherein the at least one terminal is substantially insulated from other terminals except the pull-down means. 5. The liquid crystal display device according to claim 1, wherein the pull-down means is connected to a position electrically closer to the terminal than other circuits. 6. A substrate having a plurality of wirings formed thereon, and a plurality of terminals facing the plurality of wirings, wherein a predetermined terminal substantially insulated from another terminal is connected to the other terminal, At least a semiconductor element that has a built-in energization circuit that energizes the predetermined terminal when the power is turned on, and an anisotropic conductive material that fixes the semiconductor element to the substrate and connects the plurality of terminals to the plurality of wirings. An apparatus comprising a semiconductor element, comprising: a junction between the wiring and the anisotropic conductive material and a junction between the terminal and the anisotropic conductive material, which are stabilized with low resistance by the energization.