JPH08256263A - Image reader - Google Patents

Abstract

PURPOSE: To attain quick and proper shading correction even when dust is depositted onto a white reference board. CONSTITUTION: Picture elements are interleaved and the interleaved picture elements are interpolated based on a sampling pulse with an interval of 8 clocks whose timing is shifted in the unit of two clocks in response to 1st to 4th lines on a white reference board 10, the resulting picture elements are compared with picture elements stored in a correction memory 15d and the larger picture elements are stored in the correction memory 15d. The processing above is repeated to generate white reference image data and image data obtained by reading an original 11 are corrected based on the white reference image data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage means for storing white reference image data formed on the basis of image data read by the image sensor, by reading the white reference surface by the image sensor prior to reading and scanning the image by the image sensor. And an image reading device having shading correction means for correcting read data of an image read by the image sensor based on white reference image data stored in the storage means.

[0002]

2. Description of the Related Art When a digital copying machine, a facsimile machine, or the like reads an original using an optical image sensor, distortion of an optical system, variation in illuminance of a light source for illuminating the original, and sensitivity of each pixel of the image sensor Since shading distortion such as unevenness makes the pixel value of each pixel inhomogeneous, various shading correction techniques for electrically correcting such shading distortion are known.

As a typical example of this shading correction technique, a white reference plane (hereinafter referred to as "white reference plane") is read in advance before the image sensor reads and scans an image to be read as an original. Correction data used for shading correction based on image data (hereinafter,
It is called "white reference image data". ) Is created and shading correction is performed on the white level of the read data of the image obtained by reading the original image with the image sensor based on the white reference image data.

However, in such a conventional technique, the white reference image data used for shading correction must accurately reflect the optical characteristics of the image sensor.
If it is affected by dust or dirt adhering to the white reference surface, correction will be performed with a large error, which will cause deterioration of image quality.

Therefore, in order to minimize the influence of dust and the like adhering to the white reference surface, Japanese Unexamined Patent Publication No. 2-20277.
In Japanese Patent Laid-Open No. 2-9, a range in which a correction coefficient for each bit of an analog image signal can be taken is defined, and an image signal to which a bit level that specifies a correction coefficient outside this range is input is corrected in an adjacent or adjacent image. An image signal correction method that interpolates based on a signal is disclosed.

However, according to this prior art, since only local interpolation is performed based on image signals located adjacent to or in the vicinity, one pixel attached to the white reference plane
It can only deal with dust of a few pixels.

Further, in Japanese Patent Laid-Open No. 4-68868,
An envelope circuit is disclosed in which one line of image data is loaded into a memory, and the average value of the pixel values of a plurality of pixels before and after the pixel of interest is obtained from both the right side and the left side of the line and used as the pixel value of the pixel of interest. There is.

However, in this conventional technique, the average value of a plurality of pixels before and after is sequentially obtained for each pixel of interest, so that it takes time until the white reference image data used for shading correction is created, and the shading correction process is performed. Be delayed.

Further, in Japanese Utility Model Laid-Open No. 2-55769, it is based on read data obtained by reading a white reference plane during prescan and correction data of low frequency components obtained by thinning out the read data and interpolating a defective portion. Thus, an image reading device for reproducing white reference image data is disclosed.

However, in this prior art, when interpolating the thinned-out portion of the read data of the white reference plane, the arithmetic processing is performed based on the data left without being thinned out, so that it is left without being thinned out. If the data itself is affected by dust adhering to the white reference surface, incorrect correction data for the low frequency component will be used instead, and the influence of dust will expand.

[0011]

As described above, the image signal correction method disclosed in Japanese Patent Application Laid-Open No. 2-202772 can deal with only a few pixels of dust attached to the white reference surface, and In the envelope circuit disclosed in Japanese Unexamined Patent Publication No. 4-68868, the processing delay associated with the averaging process increases, and in the image reading apparatus disclosed in Japanese Unexamined Patent Publication No. 2-55769, the image quality may deteriorate. There was a problem.

Therefore, it is an object of the present invention to solve the above-mentioned problems and to provide an image reading apparatus capable of performing a quick and appropriate shading correction even when dust adheres to the white reference surface. And

[0013]

In order to achieve the above object, a first aspect of the invention is to read a white reference plane by the image sensor prior to reading and scanning of an image by the image sensor, and convert the image data read by the image sensor. An image reading apparatus having white shading correction means for storing white reference image data formed on the basis of the storage means and correcting read data of an image read by the image sensor based on the white reference image data stored in the storage means. A reading means for reading the white reference surface for a plurality of lines by the image sensor; a sampling means for intermittently sampling the image data of each line read by the reading means at a plurality of different pixel positions; and the sampling means. Other than the line based on the sampled image data A data interpolating means for interpolating and calculating the image data of the pixel, determined the white reference image data for each pixel by comparing the image data of each line which is interpolated by the data interpolating means with respect to the same pixel,
And a white reference image data storage control means for storing the white reference image data in the storage means.

According to a second aspect of the present invention, the white reference image data storage control means compares the image data of each line interpolated by the data interpolating means with respect to the same pixel, and the maximum image data of each pixel is the white reference image data. The image data is stored in the storage means.

According to a third aspect of the invention, the white reference image data storage control means removes the maximum value and / or the minimum value for the same pixel of the image data of each line interpolated by the data interpolating means, and the remaining An average value of image data is obtained for each pixel, and the average value is stored in the storage means as the white reference image data.

[0016]

According to the first aspect of the invention, when a plurality of lines of the white reference surface are read by the reading means prior to the reading and scanning of the image, the sampling means intermittently reads the image data of each line at a plurality of different pixel positions. Image data of other pixels in the line is calculated based on the image data sampled by the data interpolation means. Then, the white reference image data storage control means obtains white reference image data for each pixel by comparing the interpolated image data of each line with respect to the same pixel, and stores the white reference image data in the storage means. The read data of the image read by the image sensor is corrected based on the white reference image data stored in the storage means.

According to the second aspect of the invention, the white reference image data storage control means compares the image data of each line interpolated by the data interpolating means with respect to the same pixel, and the maximum image data of each pixel is obtained. The white reference image data is stored in the storage means.

According to the third invention, the white reference image data storage control means removes the maximum value and / or the minimum value of the same pixel of the image data of each line interpolated by the data interpolating means, and An average value of the remaining image data is obtained for each pixel, and the average value is stored in the storage means as the white reference image data.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a view showing the external arrangement of the image reading apparatus according to the present invention.

As shown in FIG. 2A, in this image reading apparatus, an original pressing cover 24 having a white original pressing 23 is openably mounted on an image reading apparatus housing 22 having a platen glass 21 on the upper surface. The original alignment mark 25 is aligned and the original is placed on the platen glass 21.
The document is read by performing a predetermined operation after placing it on the document cover 24 and closing the document pressing cover 24.

That is, as shown in FIG. 2B, the left side and the lower side of the original 26 are placed along the original guide 25, the reading surface is placed on the platen glass 21 side, and the original pressing cover 24 is closed. .

In this embodiment, the white reference surface 25a used for shading correction is provided in the document guide 25, and the white reference surface 25a is read to create white reference image data, and then the document 26 is read to read the document 26. The read data is corrected line by line based on the white reference image data.

FIG. 3 is a diagram showing the internal structure of the image reading apparatus. When a document 26 is placed on the platen glass 21 and a predetermined operation is performed, a stepping motor 22b moves a light source 22c in the sub-scanning direction. From the image sensor 2 on the image sensor control board 22f via the mirror 22d and the lens 22e.
Image to 2g.

Then, after the image sensor 22g photoelectrically converts this image formation into image data, the A / D converter provided in the control unit 22a quantizes the image data, so that, for example, each pixel has 8 pixels. 256-tone digital image data consisting of bits is obtained.

In this image reading apparatus, the white reference surface 25a is read a plurality of times while moving the reading line, and the read data is thinned out and interpolated to remove dust and dirt adhering to the white reference surface 25a. It is configured to reduce the effect of.

Next, the control unit 2 of this image reading apparatus
The shading correction circuit provided in 2a will be described.

FIG. 1 is a diagram showing a detailed configuration of a first embodiment of a shading correction circuit according to the present invention.

As shown in FIG. 1, the shading correction circuit 15 includes an interpolation circuit 15a and a pulse generation circuit 15.
b, a comparison circuit 15c, a correction memory 15d, and a correction calculation circuit 15e, the white reference plane 10 is read by four lines before the original 11 is read, and white reference image data is created.

The interpolation circuit 15a thins out pixels from the pixel row reflected by the white reference surface 10 and input through the lens 12, the image sensor 13 and the A / D converter 14, and the thinned pixels. Is a processing unit for interpolating the pixel values of and outputting to the comparison circuit 15c.

Specifically, based on the sampling pulse obtained from the pulse generation circuit 15b, the pixels located at a constant interval in the input pixel row are latched to thin out pixels other than the latched pixel, and The pixel value of the defective portion is interpolated based on the pixel value of the latched pixel.

That is, in this embodiment, when a pixel row for one line is read from the white reference surface 10 in consideration of the case where each pixel is affected by dust adhering to the white reference surface 10, it is divided into eight pixels. By latching the pixel values of the separated pixels, thinning out the pixels other than the latched pixels from the pixel row, and calculating the pixel values of the thinned pixels based on the pixel values of the latched pixels Interpolation of parts is performed.

However, if the pixel value itself of the latched pixel is affected by the dust adhering to the white reference surface 10, such thinning and interpolation will rather expand the influence of the dust.

Therefore, in the first embodiment, the white reference plane 1
The influence of dust adhering to the white reference plane 10 is reduced by reading lines of 0 different four times and interpolating the defective portion while changing the positions of pixels to be thinned out for each line.

The pulse generation circuit 15b is the interpolation circuit 1 described above.
5a is a pulse generation circuit that provides the timing of the latch performed by 5a as a sampling pulse.

The comparison circuit 15c is a circuit for comparing the correction data stored in the correction memory 15d with the interpolation data thinned and interpolated by the interpolation circuit 15a for each pixel and storing the comparison result in the correction memory 15d. is there.

The correction memory 15d is a line memory for storing the comparison result of the comparison circuit 15c, and has a storage capacity capable of storing at least each pixel value of the pixel column.

At the time when the four lines on the white reference plane 10 are processed, the correction memory 15d stores
White reference image data for shading correction is stored.

The correction arithmetic circuit 15e converts the image data obtained by reading the original 11 through the optical system of the lens 12 and the image sensor 13 and the A / D converter 14 into the correction memory 1.
This is an arithmetic circuit that performs shading correction for each line based on the pixel value of 5d, and outputs the arithmetic result to the image processing unit 16.

Each time the different lines on the white reference plane 10 are read by using the shading correction circuit 15 having the above configuration, pixels are thinned out and their interpolation is performed, and the correction memory 1
By comparing the contents of 5c with each pixel and storing a larger pixel value in the correction memory 15c, the white reference plane 10
White reference image data is created in which the effect of dust adhering to is reduced.

Next, the detailed configuration of the pulse generating circuit 15b and the generation timing of the sampling pulse output from the pulse generating circuit 15b will be described.

FIG. 4 shows a pulse generation circuit 15b shown in FIG.
It is a figure which shows the detailed structure of.

As shown in FIG. 4, this pulse generating circuit 1
5b is a sampling pixel address counter 41 for generating sampling pulses at intervals of 8 clocks, and a shift amount for shifting the generation timing of the first pulse for each line (2 clocks in the first embodiment). The sampling pixel address counter 41 includes a shift amount counter 42 that outputs the sampling pixel address counter 41. The sampling pixel address counter 41 operates based on the video clock (CK), the line synchronization signal (LD), and the line synchronization signal. When receiving the shift amount output from, the sampling pulse is output by shifting the pulse generation timing by 2 clocks for each line.

FIG. 5 is a timing chart showing the generation timing of the sampling pulse output from the pulse generation circuit 15b.

As shown in FIG. 5, in the case of the first line, the pulse 5a is generated starting from the first clock of the video clock, and the next pulse 5b is pulse 5a.
It is generated at the 9th clock, which is delayed by 8 clocks from the above, and similarly, the pulses 5c and 5d are generated.

Next, in the case of the second line, the first pulse generation timing is shifted by 2 clocks as compared with the case of the first line, the pulse 5e is generated from the third clock as a starting point, and then the pulse is sequentially pulsed every 8 clocks. To occur.

Further, in the case of the third line, the first pulse generation timing is further shifted by 2 clocks as compared with the case of the second line, the pulse 5f is generated starting from the fifth clock, and thereafter the pulse is sequentially generated every 8 clocks. To occur.

Further, in the case of the fourth line, the first pulse generation timing is further shifted by 2 clocks as compared with the case of the third line, a pulse 5g is generated from the seventh clock as a starting point, and thereafter, a pulse is sequentially generated every eight clocks. To occur.

As described above, the pulse generation circuit 15b generates sampling pulses at a pulse interval of 8 clocks while shifting the pulse generation timing for each line by the number of clocks stored in the shift amount counter 42.

Therefore, the interpolation circuit 15a has a pulse interval of 8 clocks (8 pixels), and 2 lines for each line.
The pixel value is latched based on the sampling pulse shifted by the clock (2 pixels). As a result, 7 pixels located between the latched pixels are thinned out based on the sampling pulse of the pulse generation circuit 15b. There is.

Although the thinning interval is 8 pixels and the shift amount for each line is 2 pixels in the present embodiment, the thinning interval and the shift amount can be set arbitrarily.

Next, the internal structure of the interpolation circuit 15a and the interpolation processing performed by the interpolation circuit 15a will be described in detail.

FIG. 6 is a block diagram showing a detailed structure of the interpolation circuit 15a shown in FIG.

As shown in FIG. 6, this interpolation circuit 15a
Is composed of a latch circuit 61, a register 62, an interpolation coefficient calculation circuit 63, multipliers 64 and 65, and an adder 66.

The latch circuit 61 includes a pulse generation circuit 15b.
White reference plane 1 based on the sampling pulse output by
It is a circuit that latches pixel values for every 8 pixels from each pixel column in which 0 is read.

The pixel value latched by the latch circuit 61 is held inside the latch circuit 61 until the next pixel value is latched, and is output to the register 62 when the next pixel value is latched.

The register 62 is a register for holding the pixel value received from the latch circuit 61, and the latch circuit 6
When 1 outputs the pixel value to the multiplier 64, the pixel value held in the register is output to the multiplier 65.

That is, the register 62 and the latch circuit 6
1 is continuously latched from the input pixel row 8
Pixel values of two pixels separated from each other are stored.

For example, in the case of the sampling pulse shown in FIG. 5, the latch circuit 61 first internally holds the pixel value of the first pixel latched based on the pulse 5a,
When the latch circuit 61 latches the pixel value of the ninth pixel based on the next pulse 5b, it outputs the pixel value of the first pixel to the register 62 and holds the pixel value of the ninth pixel inside. Therefore, at this point, the register 62 holds the pixel value of the first pixel, and the latch circuit 61 holds the pixel value of the ninth pixel.

Then, the register 62 and the latch circuit 61
The pixel values respectively held by are output to the multiplication units 64 and 65, and after being multiplied by necessary correction coefficients and added, the pixel values of the second pixel to the eighth pixel are interpolated.

Next, when the latch circuit 61 latches the pixel value of the 17th pixel based on the next pulse 5c, the pixel value of the 9th pixel held in the latch circuit 61 is output to the register 62, and the same. Is processed.

In this way, the pixel values of the pixels thinned out based on the pixel values held in the latch circuit 61 and the register 62 are interpolated.

Next, the interpolation processing performed by the interpolation circuit 15a having the above configuration will be specifically described.

FIG. 7 is a diagram showing a specific example of the interpolation processing performed by the interpolation circuit 15a.

As shown in FIG. 7, here, the pulse 7a is used.
Nth pixel to (n + 7) th pixel located between the nth pixel latched on the basis of the above and held in the register 62 and the n + 8th pixel latched on the basis of the pulse 7b and held in the latch circuit 61. A case will be described in which the pixel value of is interpolated by proportionally distributing the pixel value of the nth pixel and the pixel value of the n + 8th pixel.

Let the pixel value of the nth pixel be'a ', and let the nth + 8th pixel.
If the pixel value of the pixel is'b ', then the n + i-th pixel (i = 1
The pixel value ci of 7 to 7) can be estimated as ci = {(8-i) / 8} × n + (i / 8) × (n + 8).

Therefore, each pixel value is as follows: c1 = 7/8 × n + (1/8) × (n + 8) c2 = 6/8 × n + (2/8) × (n + 8) c3 = 5/8 × n + (3/8) × (n + 8) c4 = 4/8 × n + (4/8) × (n + 8) c5 = 3/8 × n + (5/8) × (n + 8) c6 = 2/8 × n + (6 / 8) × (n + 8) c7 = 1/8 × n + (7/8) × (n + 8).

Therefore, the pixel value a of the nth pixel held in the register 62 and the nth pixel held in the latch circuit 61.
In the case of interpolating the pixel value ci of the (n + i) th pixel using the pixel value b of +8 pixels, the correction coefficient calculation circuit 63 outputs (8-i) / 8 to the multiplier 65, Multiplier 6
For (4), (i / 8) is output.

Then, the interpolation circuit 15a outputs the pixel row interpolated by the above-mentioned interpolation procedure to the comparison circuit 15c, and the comparison circuit 15 outputs each pixel value of the pixel row to the correction memory 15d.
The larger pixel value is stored in the correction memory 15d by comparing with the pixel value of the pixel column held in each pixel.

For example, at the time when the interpolation circuit 15a processes the second line of the white reference surface 10, the processing result of the first line is stored in the correction memory 15d.
A pixel column that has undergone thinning and interpolation processing for the line,
The pixel row subjected to the thinning and interpolation processing on the second line is compared for each pixel, and the one having the larger pixel value is stored in the correction memory 15d.

When the interpolation circuit 15a processes the first line, since the correction memory 15a is in the initial state, the result of the interpolation processing of the first line is stored in the correction memory 15d as it is.

By performing the above-described series of processing for each of the first to fourth lines of the white reference surface 10, the white reference image data in which the influence of dust adhering to the white reference surface 10 is reduced is held in the correction memory 15d. can do.

When the image data obtained by reading the original 11 is input line by line, the correction arithmetic circuit 15e performs shading correction based on the white reference image data in the correction memory 15 and outputs it to the image processing section 16. To do.

The image processing unit 16 performs preset image processing such as filter processing, enlargement / reduction processing, and binarization processing on the image data for which the shading distortion has been corrected.

Next, the procedure for creating white reference image data performed by the shading correction circuit 15 will be described.

FIG. 8 is a flow chart showing the procedure for creating white reference image data performed by the shading correction circuit 15. Note that, here, the data interpolated by the interpolation circuit 15a is temporarily held in the line memory, and the data stored in the line memory is compared with the data stored in the correction memory 15d, so that larger data is obtained.
It will be held at 5d.

First, before reading the first line of the white reference surface 10, the reading start pixel (A), the sampling interval (S), the shift amount (X), the number of captured lines (L) and the number of effective pixels (E). Is read as initial value data (step 801), the sampling interval (S) is set in the sampling pixel address counter 41 of the pulse generation circuit 15b, and the shift amount (X) is set in the shift amount counter 42.

When the image reading process of the initial value is started, the contents of the correction memory 15d for storing the white reference image data and the line memory for temporarily storing the interpolation data are cleared (step 802). , Initial values are set in a variable M indicating the number of times of sampling and a variable k indicating a pixel position during capturing (steps 803 to 80).
4).

Then, the optically read white reference surface 1
The pixel column of the 0th M-th line is the shading correction circuit 15
Is input to the latch circuit 61 in the correction circuit 15a, the data of the kth pixel is latched based on the sampling pulse output from the pulse generation circuit 15b (step 805), and the data is stored in the latch circuit 61. Hold on.

Next, based on the data of the kth pixel held in the latch circuit 61 and the data of the kth Sth pixel held in the register 62, interpolation data of k−1th pixel to k−S + 1th pixel are sequentially obtained. It is created (step 806) and written in the line memory (step 807).

Specifically, k held by the latch circuit 61
The data of the pixel is output to the multiplier 64, the data of the k−S pixel held by the register 62 is output to the multiplier 65, and the data output by the multipliers 64 and 65 are interpolated from the interpolation coefficient calculation circuit 63. By multiplying by the coefficient and taking the sum by the adder 66, the data of the (k−1) th pixel to the (k−S + 1) th pixel located between the kth pixel and the k−Sth pixel are calculated.

However, when k−S is negative, that is, when the first pixel is latched, there is no data to be held in the register 62, so steps 806 to 807 are performed.
The process shown in is not performed.

After that, the data held in the latch circuit 61 is transferred to the register 62 (step 808), the value of the variable k indicating the pixel position being fetched is shifted to the next sampling position (step 809), and the value of the variable k is changed. Is checked to see if it exceeds the number E of effective pixels (step 810). If not, the process proceeds to step 805.

On the other hand, the value of the variable k is the number E of effective pixels.
If it exceeds, the data stored in the correction memory 15d and the data stored in the line memory are compared with each other, and the larger pixel data is written in the corresponding portion of the correction memory 15d (step 811), and the content of the correction memory 15d is updated. To do.

Then, after incrementing the variable M indicating the number of times of sampling (step 812), it is confirmed whether or not the value of the variable M has reached the upper limit value of the number of fetched lines (step 813), and the upper limit value has been reached. If not, a shift amount is added to the reading start pixel A to shift the reading start pixel (step 814) and the process proceeds to step 804. If the upper limit value is reached, the white reference image data creation process is ended.

By performing the above-described series of processing, it becomes possible to hold the white reference image data for shading correction in which the influence of dust adhering to the white reference surface 10 is reduced in the correction memory 15d.

Next, the processing results when the above-described series of processing are performed will be concretely shown.

FIG. 9 is a diagram showing waveforms of pixel values of the pixel row of the white reference image data finally held in the correction memory 15d.

FIG. 9A shows a waveform of the pixel value of the pixel row before the shading correction. Under the influence of dust adhering to the white reference surface 10, the pixel value between the pixels 9a and 9b is changed. Is showing a drop.

FIG. 9B shows a sampling pulse generated by the pulse generation circuit 15b. This pulse is output to the interpolation circuit 15a and used for the thinning process performed by the interpolation circuit 15a.

Further, in the first embodiment, since the sampling interval is 8 pixels, the pulses are separated by 8 clocks and the shift amount is 2 pixels. Therefore, the pulses generated in each line are shifted by 2 pixels. ing.

FIG. 9C shows the processing result of thinning and interpolation for each line that has read the white reference plane. In the first line, the latched pixel 9c itself is affected by dust, It is the result of expanding the influence of garbage,
For the second line to the fourth line, interpolation is performed by thinning out pixels affected by dust, and no drop in pixel value is seen.

FIG. 9D finally shows the correction memory 15d.
9 shows the waveform of the pixel value of the pixel row of the white reference image data held in FIG.
It shows that the effect of dust adhering to is improved.

That is, in this embodiment, as a result, as shown in FIG.
The pixel row processed for each line shown in (c) is compared for each pixel, and the one having the largest pixel value is adopted as the constituent pixel of the white reference image data.
The drop in pixel value in the vicinity is improved.

As described above, in the first embodiment, the pixel is determined based on the sampling pulse at the 8-clock intervals whose timing is shifted in the unit of 2 clocks in accordance with the first line to the fourth line of the white reference plane 10. The thinning-out and the interpolation of the pixel values of the thinned-out pixels are performed, the pixel value is compared with the pixel value held in the correction memory 15d, and the larger value is stored in the correction memory 15d to repeat the white reference image data. Since the image data obtained by reading the original 11 is corrected based on the white reference image data, quick and appropriate shading correction is performed even if dust adheres to the white reference surface 11. be able to.

In the first embodiment, by the comparison circuit 15c in the shading correction circuit 15, the pixel values of pixels subjected to thinning and interpolation and the correction memory 15 are stored.
The pixel values of the pixels in d are compared with each other, and the large pixels are held in the correction memory 15d. Therefore, among the pixel lines in which four lines are interpolated, the one having the largest pixel value is always white. It will be used as reference image data.

That is, when dust adheres to the white reference surface, the reflectance of that portion generally decreases, so the maximum value is adopted as the white reference image data in the first embodiment. .

However, if the maximum value is always taken, each pixel value of the white reference image data tends to be high as a whole, and if dust having a higher reflectance than the white reference surface adheres, The effect of dust adhering to the white reference surface will be magnified.

Therefore, a second embodiment of the shading correction circuit for correcting such a defect will be described below. For convenience of explanation, the same parts as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 10 is a diagram showing the detailed construction of the second embodiment of the shading correction circuit according to the present invention.

As shown in FIG. 10, this shading correction circuit 100 includes an interpolation circuit 15a, a pulse generation circuit 15b, a correction memory 15d and a correction calculation circuit 1 shown in FIG.
5e has line memories 101a to 101d and an arithmetic circuit 102 added thereto.

Similar to the shading correction circuit 15 shown in FIG. 1, the interpolation circuit 15a latches the pixel value for every 8 pixels from the input pixel row, and the pixel value of the pixel located between the latched pixels. The pulse generation circuit 15b is a pulse generation circuit that provides the timing of the latch performed by the interpolation circuit 15a as a sampling pulse.

Further, the correction memory 15d is used in the arithmetic circuit 10.
2 is a storage unit that stores the calculation result of the correction calculation circuit 1
Reference numeral 5e is an arithmetic circuit that performs shading correction on the image data obtained by reading the original 11 line by line based on the pixel values of the correction memory 15d.

The line memories 101a to 101d are storage units for storing the pixel rows thinned out and interpolated by the interpolation circuit 15a for each reading line of the white reference plane. In addition, this second
Also in this embodiment, as in the case of the first embodiment, the number of read lines on the white reference surface is four, and four line memories corresponding to the number of read lines are provided.

The arithmetic circuit 102 averages two pixel values excluding the maximum and minimum values from the pixel values existing at corresponding positions of the pixel rows held in the four line memories 101a to 101d. It is an arithmetic circuit that performs an operation that takes a value.

The reason for excluding the maximum value is to consider the case where dust with high reflectance adheres to the white reference surface and a pixel value higher than the original white reference image data appears.
The reason for excluding the minimum value is to consider the case where dust with low reflectance adheres to the white reference surface and the pixel value drops.

By using the shading correction circuit 100 having the above structure, even when various dusts having different reflectances are attached to the white reference surface, the shading correction can be performed while removing the influence of the dusts. .

Next, the detailed configuration of the arithmetic circuit 102 will be specifically described.

FIG. 11 is a diagram showing a detailed configuration of the arithmetic circuit 102.

As shown in FIG. 11, this arithmetic circuit 102
Is a maximum value removing unit 102a and a minimum value removing unit 102b.
And an average value calculation unit 102c.

The maximum value removing unit 102a is connected to the line memory 1
Of the pixel columns stored in 01a to 101d, the pixel values of the four pixels held at the corresponding positions are simultaneously accepted, the maximum value of the four pixel values is calculated, and the three maximum values are removed. The pixel value of each pixel has a minimum value removing unit
This is a processing unit for outputting to 02b.

The minimum value removing unit 102b is the maximum value removing unit 1
The minimum value is calculated from the three pixel values received from 02a, and the average value calculation unit 10 calculates the two pixel values excluding the minimum value.
2c is a processing unit for outputting.

The average value calculating unit 102c has a minimum value removing unit 1.
This is a processing unit that calculates an average value of two pixel values received from 02b.

By using the arithmetic circuit 102,
Of the four pixel values held at the corresponding positions of each pixel held in the line memories 101a to 101d, the average of two pixel values from which the maximum value and the minimum value are removed is stored in the correction memory 15d. The pixel value held in the correction memory 15d is used as white reference image data when the correction calculation circuit 15e performs shading correction.

Next, the shading correction circuit 100 described above.
The processing procedure until the white reference image data is created will be described.

FIG. 12 shows the shading correction circuit 100.
8 is a flowchart showing a procedure for creating white reference image data performed by the above.

First, before reading the first line of the white reference surface 10, the reading start pixel (A), the sampling interval (S), the shift amount (X), the number of captured lines (L) and the number of effective pixels (E). Is read as initial value data (step 1201), the sampling interval (S) is set in the sampling pixel address counter 41 of the pulse generation circuit 15 b, and the shift amount (X) is set in the shift amount counter 42.

When the image reading process of the initial value is started, first, the correction memory 15d for storing the white reference image data and the line memory 1 for temporarily storing the interpolation data respectively corresponding to the fetched lines 1 to L are read. To N are cleared (step 1202), initial values are set to a variable M indicating the number of times of sampling and a variable k indicating a pixel position during capturing (steps 1203 to 120).
4).

Then, the optically read white reference surface 1
The pixel column of the 0th M-th line is the shading correction circuit 15
Is input to the latch circuit 61 in the correction circuit 15a, the data of the kth pixel is latched based on the sampling pulse output from the pulse generation circuit 15b (step 1205), and the data is latched in the latch circuit 61. Hold on.

Next, based on the data of the k-th pixel held in the latch circuit 61 and the data of the k-Sth pixel held in the register 62, the interpolation data of the k-1th pixel to the k-S + 1th pixel are sequentially It is created (step 1206) and written in the line memory M (step 1207).

Specifically, k held by the latch circuit 61
The data of the pixel is output to the multiplier 64, the data of the k−S pixel held by the register 62 is output to the multiplier 65, and the data output by the multipliers 64 and 65 is interpolated from the interpolation coefficient calculation circuit 63. By multiplying by the coefficient and taking the sum by the adder 66, the data of the (k−1) th pixel to the (k−S + 1) th pixel located between the kth pixel and the k−Sth pixel are calculated.

However, when k-S is negative, that is, when the first pixel is latched, there is no data to be held in the register 62, and therefore steps 806 to 807 are performed.
The process shown in is not performed.

Thereafter, the data held in the latch circuit 61 is transferred to the register 62 (step 1208), the value of the variable k indicating the pixel position being fetched is shifted to the next sampling position (step 1209), and the value of the variable k is changed. Check whether the number exceeds the effective pixel number E (step 121).
0), if not exceeded, the process moves to step 1205.

On the other hand, the value of the variable k is the effective pixel number E.
If it exceeds, the variable M indicating the number of samplings
Is incremented (step 1211), it is confirmed whether or not the value of the variable M has reached the upper limit value of the number of fetched lines (step 1212), and if it has not reached the upper limit value, the shift amount is set to the reading start pixel A. In addition, after the reading start pixel is shifted (step 1213), the process proceeds to step 1204.

On the other hand, when the upper limit value is reached, each data stored in the line memories 1 to N is compared for each corresponding pixel, and the average value excluding the maximum value and the minimum value is calculated ( In step 1214), the correction memory 15d is written (step 1215), and the white reference image data creation process ends.

By performing the above-described series of processing, even if dust with high reflectance adheres to the white reference surface 10,
It is possible to hold the white reference image data for shading correction in which the influence of such dust is reduced in the correction memory 15d.

Next, the processing results when the above series of processing are performed will be concretely shown.

FIG. 13 is a diagram showing waveforms of pixel values of the pixel row of the white reference image data finally held in the correction memory 15d.

FIG. 13A shows a waveform of the pixel value of the pixel row before shading correction, which is affected by dust having a high reflectance adhered to the white reference surface 10 to cause the pixels 13a ...
The pixel value increases between the pixels 13b, and the pixels 13c-1 to 13c-1 are affected by the dust with low reflectance attached to the white reference surface 10.
It shows how the pixel value falls during 3d.

FIG. 13B shows a sampling pulse generated by the pulse generation circuit 15b. This pulse is output to the interpolation circuit 15a and used for the thinning process performed by the interpolation circuit 15a.

Further, in this embodiment, as in the case of the first embodiment, the sampling interval is 8 pixels, so that each pulse is separated by 8 clocks and the shift amount is 2 pixels, so that each line is The pulses generated in 1 are shifted by 2 pixels.

FIG. 13C shows the processing result of thinning and interpolation for each line that has read the white reference plane. In the first line, the latched pixel 13e itself is a dust of high reflectance. As a result, the influence of dust having a high reflectance is expanded.

Further, regarding the second line and the third line, since the pixels affected by dust are thinned out and interpolation is performed, no drop in pixel value is seen.

Further, in the fourth line, since the latched pixel 13f itself is affected by dust having a low reflectance, the result is that the influence of dust having a low reflectance is enlarged.

Then, the pixel values of the first line to the fourth line are stored in the line memories 101a to 101d, respectively.

FIG. 13D finally shows the correction memory 15
7 shows a waveform of the pixel value of the pixel row of the white reference image data held in d. Specifically, the maximum value 13g and the minimum value 13h of a certain pixel are removed, and the average value of the pixels 13i and 13j. Will be the result of taking.

Comparison of this waveform with that of FIG. 13A shows that the influence of dust can be improved regardless of the reflectance of dust adhering to the white reference surface 10.

As described above, in the second embodiment, the pixel is based on the sampling pulse at the 8-clock interval whose timing is shifted in the unit of 2 clocks in accordance with the first line to the fourth line of the white reference plane 10. Each line memory 101a is subjected to thinning and interpolation of pixel values of thinned pixels.
Stored in the correction memory 15d, the white reference image data is created by storing the average value of the two pixels stored in the correction memory 15d, the maximum value and the minimum value of the corresponding pixel values being removed. Since the image data obtained by reading the original 11 is corrected based on the above, even when dust having a high reflectance is attached to the white reference surface 11, it is possible to quickly and appropriately perform the shading correction.

[0139]

As described in detail above, according to the first aspect of the present invention, when the white reference plane is read by a plurality of lines prior to the scanning of the image, the image data of each line is intermittently read at a plurality of different pixel positions. Image data of other pixels in the line based on the sampled image data, and the white reference image data is calculated for each pixel by comparing the interpolated image data of each line with respect to the same pixel. Since the read data of the image read by the image sensor is corrected on the basis of the white reference image data stored in the storage means obtained and stored in the storage means, when dust adheres to the white reference surface, Even if there is, shading correction can be performed quickly and appropriately.

In the second aspect of the invention, the interpolated image data of each line is compared with respect to the same pixel, and the maximum image data of each pixel is stored as the white reference image data in the storage means. Even if dust adheres to the reference surface, it is possible to perform quick and appropriate shading correction with a simple configuration.

According to a third aspect of the invention, the maximum value and / or the minimum value relating to the same pixel of the image data of each line interpolated by the data interpolating means are excluded, and the average value of the remaining image data is removed for each pixel. Since the average value is obtained and stored in the storage means as the white reference image data, regardless of the reflectance of the dust adhering to the white reference surface, the shading is performed quickly and appropriately while eliminating the influence of the dust. It becomes possible to make a correction.

[Brief description of drawings]

FIG. 1 is a first shading correction circuit according to the present invention.
FIG. 3 is a block diagram showing the configuration of the embodiment of FIG.

FIG. 2 is a diagram showing an external configuration of an image reading apparatus according to the present invention.

FIG. 3 is a diagram showing an internal structure of the image reading apparatus shown in FIG.

FIG. 4 is a block diagram showing a detailed configuration of a pulse generation circuit shown in FIG.

5 is a timing chart showing generation timing of sampling pulses output from the pulse generation circuit shown in FIG.

6 is a block diagram showing a detailed configuration of an interpolation circuit shown in FIG.

7 is a diagram showing a specific example of an interpolation process performed by the interpolation circuit shown in FIG.

8 is a flowchart showing a procedure for creating white reference image data performed by the shading correction circuit shown in FIG.

9 is a diagram showing waveforms of pixel values of a pixel row of white reference image data held in a correction memory of the shading correction circuit shown in FIG.

FIG. 10 is a block diagram showing the configuration of a second embodiment of a shading correction circuit according to the present invention.

11 is a block diagram showing a detailed configuration of the arithmetic circuit shown in FIG.

12 is a flowchart showing a procedure for creating white reference image data performed by the shading correction circuit shown in FIG.

13 is a diagram showing waveforms of pixel values of a pixel row of white reference image data held in a correction memory of the shading correction circuit shown in FIG.

[Explanation of symbols]

10, 25a White reference surface, 11, 26 Original, 12,
22e lens, 13 image sensor, 14 A /
D converter, 15,100 shading correction circuit,
15a interpolation circuit, 15b pulse generation circuit, 15
c comparison circuit, 15d correction memory, 15e correction calculation circuit, 16 image processing unit, 21 platen glass,
22 reader housing, 22a control unit, 22
b stepping motor, 22c light source, 22d mirror, 22f image sensor control board, 22g image sensor, 23 document retainer, 24 document retainer cover, 25 document alignment mark, 41 sampling pixel address counter, 42 shift amount counter,
61 latch circuit, 62 register, 63 correction coefficient calculation circuit, 64, 65 multiplier, 66 adder, 1
01a, 101b, 101c, 101d line memory, 102 arithmetic circuit, 102a maximum value removing unit, 1
02b minimum value removal unit, 102c average value calculation unit

Front page continuation (72) Inventor Kaya Sakashita 3-7-1, Fuchu, Iwatsuki City, Saitama Prefecture Fuji Xerox Co., Ltd. Iwatsuki Plant (72) Inventor, Koji Yorimoto 3-7-1, Iwatsuki City, Saitama Prefecture Fuji X-Locks Co., Ltd. Iwatsuki Office

Claims (3)

[Claims] 1. A white reference plane is read by the image sensor prior to scanning of an image by the image sensor, white reference image data formed based on the image data read by the image sensor is stored in a storage means, and An image reading apparatus having shading correction means for correcting read data of an image read by the image sensor based on white reference image data stored in a storage means, wherein the image sensor reads the white reference surface for a plurality of lines. Sampling means for intermittently sampling the image data of each line read by the reading means at a plurality of different pixel positions, and calculating image data of other pixels of the line based on the image data sampled by the sampling means Data interpolating means White reference image data storage for obtaining the white reference image data for each pixel by comparing the image data of each line interpolated by the data interpolation means with respect to the same pixel, and storing the white reference image data in the storage means An image reading apparatus comprising: a control unit. 2. The white reference image data storage control means compares the image data of each line interpolated by the data interpolation means with respect to the same pixel, and the maximum image data of each pixel is stored as the white reference image data in the storage means. The image reading device according to claim 1, wherein the image reading device stores the image in the image reading device. 3. The white reference image data storage control means removes a maximum value and / or a minimum value for the same pixel of the image data of each line interpolated by the data interpolating means, and calculates an average value of the remaining image data. Obtained for each pixel,
The image reading apparatus according to claim 1, wherein the average value is stored in the storage unit as the white reference image data.