JPH03219978A - Image processing device - Google Patents

Abstract

PURPOSE:To obtain an image processing device capable of using a delay memory and other circuits used for a secondary filter and a binarizing circuit in a common and integral manner by a method wherein multivalued image data inputted from a first input means is multiplexed or added with a signal inputted from a second input means to be binarized. CONSTITUTION:An inputted multivalued image signal is multiplexed by a multiplexer 5 and inputted to an error addition circuit 6. In the adder, a diffu sion error e1 is added to the signal. The signal outputted from the adder is passed through a latch to be delayed for one pixel. The image signal with a 5-pixel delay is outputted as a pixel signal. The multiplexed signal of the image signal with the error signal outputted from the error addition circuit 6 is inputted to a line memory 1 to be added with error contents in an error addition circuit 7 and an error addition circuit 8. The signal has a 1-line delay each in line memories 3, 4 and inputted in a latch circuit 9. The signal is com pared with a threshold Vth by a comparator 12. As a result, the output is binarized. The binarized error E is processed through a gate and divided into error contents e1 - e12 by a diffusion error calculation circuit 16 to be diffused rearward by the error addition circuits 6, 7, and 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and for example, to an image processing device that converts a multivalued manually inputted image signal into a binary image signal.

[Conventional technology] Conventionally, laser beam printers (LBP) and ink printers
Many jet printers use a binary recording method where the recording dots are printed as R or not.
In a copying device that applies this, in order to copy images with halftone density such as photographs and halftone originals, the halftone image data that has been read is used to reproduce the halftones in a pseudo manner using an image processing circuit. is being processed.

As one of such pseudo halftone processing methods, there is a method called "error diffusion method".

The error diffusion method is a method that is characterized by diffusing the density error during binarization to surrounding pixels and preserving the density.References include R, w Floyd and L,
Steinberg An Adaptive A
lgorithm for Spatial Gray
5cale” SID 75 Digest.

Apart from this, two-dimensional filtering such as edge enhancement and smoothing is often performed as necessary in the process of image processing, and this processing is usually performed on multivalued image data. A configuration is often adopted in which the multivalued data processed in this way is binarized and output.

FIG. 12 is a diagram showing an example of the configuration of the conventional image processing apparatus. In the figure, the input multivalued image signal is F I F O (First In First Ou
t) Delayed by one line by the memories 100-103. A total of 5 lines of multivalued image signals output from each FIFO are taken out for 5 pixels each through latch circuits 106 to 110, and each is a 5x5 pixel signal D II to I.
) is input to the weighting circuit 111. The weighting circuit 111 multiplies appropriate coefficients according to the processing of each pixel signal, J. For example, 5x
Coefficient matrices when smoothing is performed using five pixels are shown in FIGS. 13(a) and 13(b). By summing the thus weighted signals in the adding circuit 112, 2
A dimensional filtered image is obtained. The signal thus obtained is input to a circuit that binarizes it using the error diffusion method. The signal is sent from point A to comparator 113
During the flow, binarization errors 01 to e12 generated when the preceding pixels were binarized are added via one-pixel delay circuits 126 to 135 and adders 114 to 125. Next, in the converter 113, the image signal obtained at point B, that is, the signal ■ which is the sum of the accumulated error signals, and the threshold value V
th (Vth=128 for 8-bit input data
(typically), and as a result, the signal V reaches the threshold value vth
When it is larger, the output is 1, otherwise the output is 0, and the output is binarized and output.

That is, when expressed as an equation, it becomes as follows, and the binarization error E at this time is as follows. Therefore, the selector 137 is not used.

The subtracter 136 is a circuit that calculates V - V max, and V max is Vmax = 255 when 8 bits are input.
is a common value.

In order to diffuse the error E obtained in this way to the subsequent pixel signal, the error E is input to the diffusion error calculation circuit 138. This diffusion error calculation circuit 138 outputs e, ~et2. e1 to e1□ are each e l= e s =
E/48, e2 = 84 = 86 = 61
゜ = 3 E/48, e 3 = 8? = e s
= e r + = 5 E /48 e =7
E/48 Then, it is diffused as e 12 = E - Σ el, and the diffusion error calculation circuit 138 is a lookup table or arithmetic circuit for calculating the above value.

As shown in FIGS. 14(a) and 14(b), the error when the focused pixel is binarized is calculated by the above error diffusion process.
By diffusing to surrounding pixels that have not yet been binarized, binarization is performed while preserving the overall density.

[Problem that the invention seeks to solve] However,
The above conventional example has the following drawbacks. That is, (1) Since the line delay memory for two-dimensional filtering and the line delay memory for error diffusion are independent, the circuit becomes thick.

(2) Since the two-dimensional filter and the binarization circuit are independent and there is a large amount of external memory, it is not easy to integrate them into a dedicated IC.

The line delay from when the 0 image is input until it is output is the delay of the two-dimensional filter (2 lines) and the delay of the 13-value conversion unit (
2 lines), resulting in a large amount of delay. This becomes a design constraint when there is a control signal accompanying the image signal, such as an editing signal.

In view of the above-mentioned drawbacks of the conventional example, an object of the present invention is to provide an image processing device that can share and integrate delay memories and other circuits used in two-dimensional filters and binarization circuits.

[Means for Solving the Problems] In order to solve the above-mentioned problems and achieve the objectives, an image processing device according to the present invention is an image processing device that performs two-dimensional filtering when binarizing a multivalued image signal. And,
a first input means for inputting the multivalued image data; a second input means for inputting the signal for the two-dimensional filtering; and a second input means for inputting the signal for the two-dimensional filtering; It is characterized by comprising a multiplexing means for multiplexing the multivalued image data and the signal inputted by the second input means, and a binarizing means for binarizing based on the multiplexed signal. According to this configuration, the first input means inputs multivalued image data, the second input means inputs a signal for two-dimensional filtering, and the multiplexing means receives a predetermined clock. The multivalued image data inputted by the first input means and the signal inputted by the second input means are multiplexed or added based on the signal, and the binarization means is based on the multiplexed or added signal. te2
Perform value conversion.

[Embodiments] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

<First example> First, a first example will be described.

FIG. 1 is a block diagram showing the configuration of a first embodiment of an image processing apparatus according to the present invention. In the same figure, 12.3.4 is a line memory, 5 is a multiplexer (MPX), 6, 7
．． 8 is an error addition circuit, 9 is a latch circuit, 10 is a weighting circuit, 11 is an addition circuit, 12 is a comparator, 13 is a subtraction circuit, 14 is a selector, 15 is a gate, and 16 is a diffusion error calculation circuit. There is. Describing the main signals in FIG. 1, Input is a multivalued (8-bit) image signal, el, e2 . ..., e1□ is a binary error signal obtained by error diffusion processing, and is a multivalued signal with positive and negative values, D,
,, DlF, I D2□+ Ds++ Dss is a multivalued pixel signal, Err is a positive and negative multivalued error signal at the pixel position of interest, fs is the basic clock signal of the image, 2
fs is a clock signal with twice the frequency of fs, vth is a threshold for binarization (Vth = 128), 0output
1 and 2 respectively indicate binarized pixel signals.

Here, the operation of the above configuration will be explained.

Figure 2 is a timing chart explaining the operation of each signal in the first embodiment, Figures 3 and 4 are block diagrams showing the configuration of the error addition circuit in the first embodiment, and Figure 5 is the first embodiment. A block diagram showing the configuration of the latch circuit 9, FIGS. 6(a) and 6(b)
) is a diagram illustrating filtering coefficients for edge enhancement in the first embodiment. In FIG. 3, 20 to 24 indicate adders, and 25 to 34 indicate latches. Also, the fourth
In the figure, 35, 36 indicate adders, 37 to . 43
indicates a latch. Furthermore, in FIG. 5, 44-
48 indicates a latch.

As shown in FIG. 2 (2) and (3), multivalued image signals input from Input (input image data V+,
V2, Va...) are multiplexed by a multiplexer 5 at a clock cycle of 2 fs. That is, as shown in Fig. 2 (4), by switching and outputting the image signal (input image data) and °°0゛, during one cycle of the clock fs shown in Fig. 2 (1). Multiplexing is performed using the image signal (input image data) and °°O''.Here, the portion given 0゛° is the binarization error e1~ due to error diffusion processing, as will be described later in the later stage. This is the processing part that accumulates e1□, and finally the signal E rr is generated.The multiplexed data output from the multiplexer 5 is input to the error addition circuit 6, where the pixel preceding by two lines is binarized. Of the error components generated at the time, e1 to e5 are added.Here, the error addition circuit 6 has the configuration shown in FIG. ing.

The multiplexed signal input from the left side to the error addition circuit 6 is added with a diffusion error e1 by an adder 20.

The diffusion error e1 is a multiplexed signal similar to the output from the multiplexer 5, as shown in FIG. 2 (5). That is, the first half of the clock fs is the data ladder "O", and the second half is the diffusion error e1. Therefore, (4), (
5), what is added to the input signal by the adder 20 is the value of only the error component in the second half of the clock fs, and the value of only the image signal in the first half, and the error component and the image signal are added to the input signal. Output is unchanged. In this way, the signal output from adder 20 passes through latches 25, 26 to be delayed by one pixel. In order to drive two latches with a clock of 2 fs, a delay of exactly l clocks of fs, that is, one pixel, is performed. The image data portion of this signal is taken out as data D11 for two-dimensional filtering, and then similarly passed through adders 21 to 24 and latches 27 to 34, and then shifted pixel by pixel to generate error components ex, ea+. ..., es are accumulated. And 5
The image signal delayed by a pixel is taken out from the last latch 34, and the pixel signal D1. is output as Pixel signal DI
l and D15 are image data separated by 4 pixels. Then, the multiplexed signal of the image signal and the error signal output from the error addition circuit 6 is input to the line memory 1.

The line memory 1 has a capacity sufficient to hold pixel signals and error signals for one line, is driven by a clock signal 2fs, and has the function of delaying the signal by one line.

This line memory 1 is a FIFO, and the error addition circuit 6
The timing of the start of writing and the start of reading is controlled so as to cancel out the delay of 5 pixels at . The signal read out from the line memory 1 in this way is sent to the error adding circuit 6.
The error addition circuit 7 having the same configuration as the error component e6~
elo is added. Then, the delay for one line is again performed by the line memory 2, and the error components all and eI□ are added to the input image signal by the error addition circuit 8. The error addition circuit 8 has the configuration shown in FIG. In FIG. 4, when the above-mentioned addition of error components and delay of one pixel are performed by adders 35 and 36 and latches 37 and 38, pixel signal D2 is obtained from the pixel position after adding e1□.
□ and the cumulative error signal E rr are taken out. Pixel signal D
2□ is the target pixel signal that is currently being binarized, and E
rr is the cumulative error of the corresponding or multiplexed pair. Since the pixels after the pixel of interest have already been binarized, the error signal is not necessary, and only the image signal is latched by the clock fs. However, latches 41, 42, 43
It should be mentioned that this configuration is not essentially necessary and can be omitted since the same effect can be obtained by shifting the writing start timing of the next stage line memory 3 by that amount.

In this way, the signal output from the error addition circuit 8 is delayed by one line in each of the line memories 3 and 4. As described above, only the image signal flows through this processing section, so the clock signal is fs, and the storage capacity of the memory is half that of the line memories 1 and 2. Also, line memory 4
Since it does not have a latch in the preceding stage, there is no need to shift the timing of writing start and reading start.

Next, the image signal output from the line memory 4 is input to the latch circuit 9. The latch circuit 9 has the configuration shown in FIG. As shown in the figure, pixel signals Ds+ and Dss separated by four pixels are obtained simultaneously by latches 44-48.

From the explanation of FIGS. 2 to 5 above, pixel signals D11 to D
55. A cumulative error signal E rr is obtained. Dz〜D
The pixel signal of ss is the signal at the position shown in FIG. 6(a) among the 5×5 pixels. Pixel signal D II to D sg
A weighting circuit 10 weights each of the signals using the coefficients shown in FIG. 2(b). The signal weighted according to each coefficient by the circuit 10 and the cumulative error signal E rr are summed by the adding circuit 11 . That is, as expressed in the following formula (1), Vl−坏(D+++D+s+Ds+÷Ds6)+3Dz
□) + Err - (1) is obtained. Note that ■ is defined as an additional value. The term excluding the cumulative error signal E rr is edge enhancement processing using the known Laplacian.

The signal obtained by adding the cumulative error E rr to the two-dimensional filtered signal is compared with the threshold value vth by the comparator 12 . As a result of this comparison, the output is
As shown in equation (2) below, it is binarized by:

In this way, the error accompanying the binarization is calculated at the same time as the binarization is performed. Since the binarization error E is as shown by the following equation (3), the subtraction circuit 13 calculates V-Vmax, and selects this result and the addition value V according to the binarization output. By switching at 14, the binarization error E is obtained. Here, it is assumed that Vmax=255.

The binarization error E determined in this way is gated by fs which is an inversion of the clock fs at the gate 15, and a multiplexed signal as shown in FIG. 2 (5) is generated. This multiplexed signal is processed by the diffusion error calculation circuit 16 into e1 to e+
z is divided into error components. The diffusion error calculation circuit 16 is a look-up table or an arithmetic circuit, and generates the following output. That is, el = 85 = E/48. e2
= e 4 = e a = e lo = 3 E /
48, e s = e 7” e 9 = e
+ + = 5 E / 48, e s = 7
E/48.

e+z=E-Σel.

This corresponds to the diffusion matrix shown in FIG. 14(b) described above, but other matrices may be used. The error components e1 to e+2 thus obtained are diffused backward by the error addition circuits 6, 7.8.

With the above circuit configuration, it is possible to perform edge enhancement and simultaneously perform binarization using error diffusion processing. In the first embodiment, by serially multiplexing error components and image data, the number of line memory parts can be reduced and other circuits can also be shared. moreover,
The amount of delay in the entire circuit can also be kept to two lines.

Although the first embodiment described above attempted to share the memory by serially multiplexing the signals, the present invention is not limited to this, and by multiplexing the data width, Effects similar to those of the embodiment can be obtained. That is, the number of bits handled by the line memory 1.2 and the error addition circuits 6 and 7.8 in FIG. , by removing the selector 5, setting all image clocks to fs, omitting latches for serial processing, and multiplexing signals in parallel, it becomes possible to integrate a two-dimensional filter and an error diffusion circuit.

Furthermore, the weighting coefficients for the pixel signals shown in FIG. 6(b) used in the first embodiment described above are just one example, and the present invention is not limited thereto; Other coefficients may be chosen to change .

Furthermore, the pixel extraction position according to the first embodiment described above is not limited to that shown in FIG. Furthermore, the two-dimensional filtering processing performed here is not limited to edge enhancement.

Further, in the first embodiment described above, the threshold value vth used in the comparator 12 was set to a fixed value of 128, but the present invention is not limited to this, and may be set to other values, depending on the case. may be variable.

<Second example> Next, a second example will be described.

FIG. 7 is a block diagram showing the configuration of a second embodiment of the image processing apparatus of the present invention, and FIG. 8 is an error addition circuit 55 of the second embodiment.
FIG. 9 is a block diagram showing the structure of the latch circuit 58 of the second embodiment.

In FIG. 7, 51-54 are line memories, 55-5
7 is an error addition circuit, 58 and 59 are latch circuits, 60 is a weighting circuit, 61 is an addition circuit, and 62 is a look-up table (LUT). In addition, in the signals in the same figure, Input is a multi-value (8-bit) image signal, e1e2 to e+2 are multi-value signals having positive and negative values of binary error components due to error diffusion, Dl+, DI□ to D ss indicates a multi-value pixel signal having positive and negative values, f3 indicates a basic clock signal of an image, and 0output indicates a binarized multi-value signal, since each signal has the same meaning as in the first embodiment described above. , using the same symbols. In FIG. 8, 70 to 74 indicate adders, and 75 to 78 indicate latches. Furthermore, in FIG. 9, 79 to 82 indicate latches.

Here, the operation of the above configuration will be explained.

In FIG. 7, the error components e1 to e5 are added to the multivalued image signal applied to I nput in an error addition circuit 55, and the pixel signals (i) to (i)+s are arranged pixel by pixel. Image data for pixels is generated. As shown in FIG. 5, the configuration of this error addition circuit 55 is such that an input image signal is first added to an error component e1 in an adder 70, and the result is output as a pixel signal D I+, 75 to latch. Since the clock signal f is the fundamental frequency of the image, the pixel signal increases each time it passes through the latches 76, 77, and 78, and 2°D+a and D14 become 1.
Delayed by a pixel. By repeating this process, the adders 71 to 74 add the next error components e2 to e5 to the previous pixel signal.
The pixel signals DI2 to DI5 are simultaneously generated and output.

The image signal (pixel signal) output from the error addition circuit 55 is delayed by one line in the line memory 51. The line memory 51 is a FIFO memory, and controls the timing of the start of writing and the start of reading so as to cancel out the delay of four clocks (four pixels) caused by the error addition circuit 55. Therefore, after one line of delay is performed by the line memory 51, the image signal is converted into error components e6 to e by an error addition circuit 56 having the same configuration as the error addition circuit 55. Error components are added sequentially, and pixel signals D21 to I)zs are simultaneously generated and output.

Next, the image signal outputted from the error addition circuit 56 is again delayed by one line in the line memory 52, and an error addition circuit 55 having almost the same configuration as the next error addition circuit 55
7, error components ex and e12 are added. The error addition circuit 57 is configured such that the error components e++ and e+i are added to positions corresponding to the error components e+ and e2 added to the adders 70 and 71 of the error addition circuit 55 shown in FIG. 8, respectively.

In this way, the image signal output from the error addition circuit 57 is delayed by one line in the next line memory 53, and
The signal is input to the latch circuit 58. The latch circuit 58
As shown in the figure, it has a configuration in which five latches 79 to 82 are connected in series, and the input image signal is delayed by l clocks by the clock signal f8, and the pixel signals D41 to D46 are simultaneously processed. Generate and output. Then, the image signal output from the latch circuit 58 is delayed by one line in the next line memory 54, and then the pixel signal D! 1 to D ss is generated and output.

In this way, the error calculation circuits 56 and 57 and the latch circuit 5
The pixel signals Dz~D□ obtained from 8.59 are
This is image data of a 5×5 pixel matrix (range) shown in FIG. 3(a). This image data is weighted by a circuit 60, for example, the weighting shown in FIG. 13(b) is performed by a coefficient. Next, the weighting is performed by the circuit 60
The summation V of all the weighted data is calculated by the next addition circuit 61, and the summation (2) becomes image data subjected to two-dimensional filtering (smoothing) of the pixel of interest (corresponding to the position of D22). The image data (2) of the pixel of interest is calculated to include error data of the error diffusion process, and binarization is performed based on this value. In the second embodiment, since the determination is made with reference to the binarized LUT62, here the LUT6
Let's talk about 2.

The LUT 62 performs binarization according to the table below.

That is, it becomes. In the second example, for an 8-bit input image signal, Vth=128. Vmax is fixed at 255.

By setting the LUT 62 in this way, the first
This means that the diffusion matrix shown in Figure 4(b) has been set.

In this way, in the second embodiment, the binarization error is added to the image signal to be smoothed (two-dimensional filtered) and averaged, and the circuits required for the two processes of smoothing and density averaging are shared. can do.

Now, in the second embodiment described above, approximation calculation is performed that includes the binarization error in the image signal subjected to the two-dimensional filter processing, but the present invention is not limited to this, and is based on the conventional technology. In order to reduce the difference from the results obtained by normal filter processing, a method for further increasing accuracy may be used.

Therefore, a modification of the second embodiment will be explained.

FIG. 10 is a block diagram for explaining the configuration of a modification of the second embodiment, and FIGS. 11(a) and 11(b) are diagrams for explaining the error diffusion method of the modification of the second embodiment. In Figure 10,
Components similar to those shown in FIG. 7 are designated by the same reference numerals and their explanations will be omitted.

This modification has a configuration in which the amount of error diffusion is further subdivided (error components e1 to e2.) compared to the second embodiment.
In place of the latch circuits 58 and 59 in FIG. 7 used in the embodiment, error addition circuits 71 and 72 having the same configuration as the error addition circuit 55 are provided, and the error addition circuit 5
7, the error component e! ++, error component et in addition to eta
a to e+s are also subject to addition. Also, the modified LUT7
3, the error components e1 to e+z are the same as in the table above,
The error components er4 to e25 are e1 to e25 for the pixel of interest.
A distribution coefficient that is point symmetrical to e1□ and has an inverted sign is set.

As shown in FIGS. 11(a) and 11(b), two-dimensional filter processing is performed by adding extra data to cancel out the binarization error that is just diffused to a symmetrical position with respect to the pixel of interest. It is possible to reduce calculation errors when performing That is, in the second embodiment, since the image data used for filter processing includes a binarization error, a value different from the result of filter processing based purely on image data is output. . Therefore, by adding the binarization error with the sign reversed to the area ahead of the pixel of interest (which has already been binarized), when filter processing is performed, the positive and negative error components cancel each other out, and the overall result is Calculation errors can be reduced.

Now, the weighting coefficients shown in FIG. 13(b) used in the second embodiment are merely examples, and it goes without saying that the coefficients and matrix shape can be modified in various ways as required.

[Effects of the Invention] As explained above, according to the present invention, by multiplexing or adding the image signal and the error signal, it is possible to share the line memory and circuit, and it is more efficient than when these are configured separately. In addition to reducing the circuit size and cost, it is also possible to reduce the overall line delay.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the first embodiment of the image processing apparatus of the present invention, FIG. 2 is a timing chart explaining the operation of each signal in the first embodiment, and FIGS. FIG. 5 is a block diagram showing the configuration of the latch circuit 9 of the first embodiment. FIGS. 6(a) and (b) are the edge diagrams of the first embodiment. FIG. 7 is a block diagram showing the configuration of the second embodiment of the image processing device of the present invention; FIG. 8 is a block diagram showing the configuration of the error addition circuit 55 of the second embodiment. 9 is a block diagram showing the configuration of the latch circuit 58 of the second embodiment, FIG. 1O is a block diagram explaining the configuration of a modification of the second embodiment, and FIGS. 11(a) and (b) 12 is a block diagram showing the configuration of a conventional image processing device. FIGS. 13(a) and (b) are general two-dimensional filtering. Figures for explaining the method. Figures 14(a) and 14(b) are diagrams for explaining a general error diffusion method. In the figure, 1 to 4, 51 to 54... line memory, 5...
・MPX, 6~8, 55~57 70~72...Error addition circuit, 9.58, 59°10
6~110...Latch circuit, 10,60°111...
・Weighting is a circuit, 11, 61, 112...addition circuit,
12,113... Comparator, 13°136...
Subtraction circuit, 14,137...Selector, 14...Gate, 16,138...Error calculation circuit, 100-10
5...FIFO1114~125°20~24,35
, 36.70-74... adder, 126-135...
・1 pixel delay circuit, 25~34° 37~48.75~8
2...Latch, 62°73...LUT.

Claims (6)

[Claims] (1) An image processing device that performs two-dimensional filtering when binarizing a multi-value image signal, comprising: a first input means for inputting the multi-value image data; and a signal for the two-dimensional filtering. 2nd to enter
input means; multiplexing means for multiplexing the multivalued image data input by the first input means and the signal input by the second input means based on a predetermined clock signal; An image processing device comprising: binarization means that performs binarization based on the converted signal. (2) The image processing apparatus according to claim 1, wherein the binarization means uses an error diffusion method. (3) The signal for the two-dimensional filtering has already been
2. The image processing apparatus according to claim 1, wherein the error component is diffused by valued pixels. (4) An image processing device that performs two-dimensional filtering when binarizing a multi-value image signal, comprising: a first input means for inputting the multi-value image data; and a signal for the two-dimensional filtering. 2nd to enter
input means; addition means for adding the multivalued image data input by the first input means and the signal input by the second input means based on a predetermined clock signal; An image processing apparatus comprising: binarization means for binarizing a signal based on the obtained signal. (5) The image processing apparatus according to claim 4, wherein the binarization means uses an error diffusion method. (6) The signal for the two-dimensional filtering has already been
5. The image processing apparatus according to claim 4, wherein the error component is diffused by the valued pixels.