JPH08256057A - Phase locked loop circuit and control method for the same - Google Patents

Abstract

PURPOSE: To provide the phase locked loop circuit and control method for the same with which a frequency can be pulled in a short time without skipping any output frequency just after the start of operation. CONSTITUTION: A voltage controlled oscillation circuit 1 starts operation corresponding to a control signal from a first control signal generator 8, a first frequency divider 5 starts operation corresponding to a control signal from a second control signal generator 6 after the operation of the voltage controlled oscillation circuit 1 is stabilized, a feedback abutting signal is inputted from the first frequency divider 5 to a phase comparator 4 synchronously with a reference abutting signal from a second frequency divider 6, and a voltage signal corresponding to the phase difference of both the signals is generated by a charge pump 3 and an integration circuit 2 and inputted to the voltage controlled oscillation circuit 1. In this case, the oscillation frequency is changed, the operation for inputting that change through the first frequency divider 5 to the phase comparator 4 again is cyclically repeated, and the oscillation frequency of the voltage controlled oscillation circuit 1 is fixed in the state of no phase difference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit in an oscillator circuit, and more particularly to a phase locked loop circuit for shortening a frequency pulling time and a control method thereof.

[0002]

2. Description of the Related Art As one of the techniques for maintaining the oscillation frequency of an oscillation circuit at a constant frequency, the output of a voltage controlled oscillation circuit,
A phase comparison circuit that performs phase comparison with a reference signal is provided, and a circuit that generates a voltage signal according to the phase comparison result in this phase comparison circuit is provided, and its output is input as a control signal of the voltage controlled oscillation circuit. A so-called phase-locked loop is configured as a PLL (Ph
It is well known and known as an ase locked loop) method.

[0003]

In such a conventional phase locked loop, it is common to start and stop the operation by simultaneously turning on / off the power of the entire phase locked loop including the voltage controlled oscillator. Target. By the way, the operation characteristics of the voltage controlled oscillator circuit itself immediately after the power supply is generally as shown in FIG.
At the same time, the oscillating frequency rises and becomes higher than the original free-running frequency (shown by the dotted line in Fig. 5). After that, the frequency gradually decreases, becoming slightly lower than the free-running frequency. Then, the oscillation frequency fluctuates above and below the free-running frequency, such that the frequency rises again, and the free-running frequency is finally reached.

On the other hand, a phase-locked loop circuit including such a voltage-controlled oscillator circuit is also supplied with power at the same time as power is supplied to the voltage-controlled oscillator circuit and starts operating, so-called transient immediately after the start of operation of the voltage-controlled oscillator circuit. In this state, the output signal of the voltage controlled oscillator circuit is taken into the phase locked loop circuit and the phase is locked.Therefore, the output frequency of the phase locked loop circuit is instantaneously jumped to the original frequency. However, there is a disadvantage that the power consumption of the entire apparatus using the phase locked loop increases in the end because the time required for the operation is prolonged.

As a technique for solving such an inconvenience, for example, operation start, operation stop, and reset of only the frequency dividing circuit, which is one of the constituent elements of the phase locked loop, are performed, and the voltage controlled oscillator circuit is used. Is known to be configured to perform forced phase synchronization by continuing the operation. However, in such a configuration, since the voltage controlled oscillator circuit is always in the operating state, there is an inconvenience that the power consumption of the circuit increases, which is not an appropriate technique.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a phase locked loop circuit and a control method for the phase locked loop circuit in which the output frequency does not jump immediately after the operation is started and the frequency can be pulled in in a short time. To aim. Another object of the present invention is to provide a phase locked loop circuit and its control method that consume less power. Another object of the present invention is to provide a phase locked loop circuit capable of pulling in a frequency for a short time without holding the voltage controlled oscillator circuit in an always operating state, and a control method thereof.

[0007]

The invention according to claim 1 for solving the above-mentioned problems of the prior art, is a voltage-controlled oscillation means in which the oscillation frequency changes according to the magnitude of a voltage signal externally input. Phase comparing means for comparing the phases of the externally input reference signal and the output signal of the voltage controlled oscillator circuit,
In a phase comparison circuit comprising a voltage generation means for generating a voltage signal according to an output phase difference of the phase comparator and inputting the voltage signal to the voltage control oscillation means, the voltage control oscillation means and the phase comparison means A frequency dividing means provided between the frequency control oscillating means and the frequency dividing means, and the frequency dividing means after the operation of the voltage controlled oscillating means is started and after a transitional state immediately after the operation of the voltage controlled oscillating means is elapsed. It is characterized in that it has an operation control means for bringing the peripheral means into an operation start state.

According to a second aspect of the present invention for solving the above-mentioned problems of the conventional example, in the method of controlling the phase locked loop circuit according to the first aspect, the operation control means sets the voltage control oscillation means to an operating state, and It is characterized in that the frequency dividing means is brought into the operation start state after the transient state of the voltage controlled oscillation means has elapsed.

[0009]

According to the first and second aspects of the present invention, when power is supplied to the entire circuit, the circuit portion excluding the frequency dividing means becomes operative, while the voltage controlled oscillating means starts operation and outputs. After passing through a so-called transient state in which the oscillation frequency changes,
The frequency division means is operated by the operation control means, and the frequency division output signal is input to the phase comparison means in synchronization with the reference signal input to the phase comparison means. Therefore, unlike the conventional case, the reference signal and the output signal of the frequency dividing means are stably synchronized, so that the frequency pull-in in the so-called loop circuit formed by the voltage controlled oscillating means, the frequency dividing means and the phase comparing means is short. Done in time.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the phase locked loop circuit according to the present invention will be described below with reference to FIGS. here,
FIG. 1 is a circuit configuration diagram of an embodiment of a phase locked loop circuit according to the present invention, and FIG. 2 is a timing chart of a main part for explaining the operation of the phase locked loop circuit of the present embodiment, and FIG. FIG. 4 is a characteristic diagram showing a change in output frequency with the passage of time, and FIG. 4 is a circuit diagram showing one embodiment of the first and second control signal generators used in the phase locked loop circuit of this embodiment. Yes, FIG. 5 is a characteristic diagram showing the change characteristic of the output frequency after the start of the operation of the voltage controlled oscillator circuit alone.
The members, arrangements, and the like described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.

As shown in FIG. 1, the phase locked loop circuit according to the present embodiment is a voltage controlled oscillator circuit (in FIG.
Abbreviated as “O”) 1, an integrating circuit 2, a charge pump 3
, A phase comparator 4, a first frequency divider (abbreviated as "DIV1" in FIG. 1) 5, a second frequency divider (abbreviated as "DIV2" in FIG. 1) 6, and a reference signal. Oscillator (Fig. 1
7 and a first control signal generator (abbreviated as “CONT SIG1” in FIG. 1).
8 and a second control signal generator (in FIG. 1, "CON
T SIG2 ”) 9 and a control circuit 10.

The reference signal oscillator (OSC) 7 is, for example,
It is an oscillator circuit using a crystal oscillator. The second frequency divider (DIV2) 6 has a predetermined frequency division ratio, and divides the output signal of the reference signal oscillator (OSC) 7 by this predetermined frequency division ratio and outputs it. .

The phase comparator 4 serving as a phase comparison means includes a second frequency divider and an output signal of the voltage controlled oscillation circuit (VCO) 1 input via a first frequency divider (DIV1) 5 described later. Comparing the phases of the output signals of the reference signal oscillator (OSC) 7 input via the (DIV2) 6 and outputting a pulse signal having a pulse width corresponding to the phase difference between the two input signals. Is.

The charge pump 3 outputs a pulse current corresponding to the pulse width of the pulse signal input from the phase comparator 4 to the integrating circuit 2. This charge pump 3
Of the charge pump 3 connected to the output side of the
The pulse current inputted from is integrated and a voltage signal corresponding to the magnitude is output to the voltage controlled oscillator (VCO) 1. In this embodiment, the charge pump 3 and the integrating circuit 2 implement a voltage generating means.

The voltage controlled oscillator circuit (VCO) 1 as the voltage controlled oscillator means oscillates a frequency corresponding to the voltage signal input from the integrating circuit 2 and also includes a first control signal generator ( The control signal input from the CONT SIG1) 8 controls the start and stop of the oscillation operation.

A first frequency divider (DIV) as frequency dividing means.
1) 5 is for dividing the signal output from the voltage controlled oscillator circuit (VCO) 1. The first frequency divider (DIV 1) 5 in this embodiment is the second control signal. A control signal input from the generator (CONT SIG2) 9 controls the start / standby and stop of the frequency dividing operation. In the start standby state, the frequency dividing operation is started by the signal input from the second frequency divider (DIV2) 6.

The control circuit 10 controls the operations of the first and second control signal generators 8 and 9. The control circuit 10 controls the first and second control signal generators 8 and 9. Based on the above, the first control signal generator 8 determines the operation timing of the voltage controlled oscillator circuit 1, and the second control signal generator 9 determines the operation timing of the first frequency divider 5, as will be described later.
A control signal for controlling each is output.

Incidentally, the first and second control signal generators 8 and 9
Is realized by a counter circuit or a one-shot multivibrator, for example, a so-called integrating circuit composed of a resistor and a capacitor, and further, for example, FIG.
It can be realized by using an integrating circuit having an inverting circuit as shown in (a) and (b). In particular, the second control signal generator 9 of this embodiment resets the first frequency divider 5 at the rising time of the first frequency divider 5, and then the first frequency divider 5 The frequency division of the output signal of the voltage controlled oscillator circuit 1 is started in synchronization with the reference matching signal, and the reference matching signal input to the phase comparator 4 and the feedback matching signal are forcedly phase-locked.
In the present embodiment, the operation control means is realized by the second control signal generator 9 and the control circuit 10.

Next, the operation of the phase locked loop having the above structure will be described with reference to FIG. First, at time 0 shown in FIG. 2, power is supplied to the phase-locked loop circuit of the present embodiment, and the voltage-controlled oscillator circuit (VCO) 1 and the first frequency divider (DIV1) 5 are excluded. The circuit part starts operating.

Simultaneously with the start of the circuit operation, the control circuit 10 outputs a signal rising from the zero level to a predetermined level to the first and second control signal generators 8 and 9 (FIG. 2 (b)). )reference).

Next, from the time point when the output signal of the control circuit 10 is input from the first control signal generator 8, a predetermined time τ
At the time point 1 has passed, a control signal that rises from a zero level to a predetermined level is output (see FIG. 2C) and is input to the voltage controlled oscillator circuit (VCO) 1, so that the voltage controlled oscillator circuit (VCO) 1 is Power is supplied and operation starts. By the way, since the voltage controlled oscillator (VCO) 1 itself in this embodiment is basically the same as that conventionally used, the operation is started and the frequency of the output signal reaches the free-running oscillation frequency. By then, it reaches a steady state through a transient state.

That is, as shown in FIG. 5, the oscillation frequency rises with the start of operation (supply of power) and becomes higher than the original free-running frequency (the portion indicated by the dotted line in FIG. 5). , The frequency gradually decreases, becomes a frequency slightly lower than the free-running frequency, and then the frequency rises again and again. , The free-running frequency is reached after a lapse of time t1 from the start of operation.

On the other hand, the time τ from the start of the operation of the control circuit 10
At the time when 2 (τ1 <τ2) has passed, the second control signal generator 9 outputs the control signal rising from the zero level to the predetermined level (see FIGS. 2 (d) and 2 (g)), and this control signal is Input to the first frequency divider (DIV1) 5,
As a result, the first frequency divider (DIV1) 5 is in the operation start state from this point.

Here, suppose that the time τ 2 for determining the operation timing of the second control signal generator 9 is the time required for the output oscillation frequency of the voltage controlled oscillator circuit (VCO) 1 to stabilize. First, τ2 <(τ1 +) will be described as divided into a case where it is smaller than the time (τ1 + t1) expressed from the start time of the operation of the
The case of t1) will be described.

Time τ 2 from the start of the operation of the control circuit 10
After a lapse of time, the first frequency divider (DIV1) 5 enters an operation standby state by the control signal from the second control signal generator 9, and operates in synchronization with the output signal of the second frequency divider (DIV2) 6. And the frequency-divided signal of the output signal of the voltage controlled oscillator (VCO) 1 is output from the first frequency divider 5 (the signal output from the first frequency divider 5 will be referred to as "Return match signal"). That is, from the first frequency divider 5 to the second
The signal synchronized with the frequency divider 6 is output (this is called "forced phase synchronization").

Here, since the voltage controlled oscillator circuit 1 is in the transient state as described above from the start of the operation of the control circuit 10 until the time (τ1 + t1) has passed, the first frequency divider 5 is The output timing of the divided signal output via
It changes as illustrated in FIG. 2 (e).

After the first frequency divider 5 is in the operating state, the output signal from the second frequency divider 6 (the output signal of the second frequency divider 6 is referred to as "reference Match signal "
The first rising edge of the feedback matching signal from the first frequency divider 5 becomes synchronized with the rising edge of the first frequency divider 5 (FIGS. 2 (e) and 2 (f)). Four
Will be input to.

Then, the phase comparison of the two signals is performed in the phase comparator 4, and a pulse signal having a pulse width corresponding to the phase difference is output from the phase comparator 4. The pulse signal from the phase comparator 4 outputs a pulse current according to the pulse width of the input pulse signal from the charge pump 3, and the integrating circuit 2 converts the pulse current into a voltage signal according to the current value. Voltage controlled oscillator circuit 1
Will be input to.

As a result, the oscillation frequency of the voltage controlled oscillator circuit 1 changes according to the voltage signal input from the integrating circuit 2, and the voltage is adjusted so that the phase difference between the reference matching signal and the feedback matching signal becomes zero. A so-called phase-locked loop formed by the control oscillation circuit 1, the first frequency divider 5, the phase comparator 4, the charge pump 3, and the integration circuit 2 cyclically operates, and the output frequency of the voltage control oscillation circuit 1 becomes stable. This is what you will do.

However, at the time when the forced phase synchronization is achieved as described above, the voltage controlled oscillator circuit 1 is still in the transient state in which the output oscillation frequency is not stable as described above (see FIG. 5). Since the phase difference obtained in the phase comparator 4 as described above is large unlike the case where the output frequency of the voltage controlled oscillator circuit 1 reaches a stable state, a frequency jump occurs as in the conventional case. (See the characteristic curve of the one-dot chain line in FIG. 3).

Therefore, in this case, after the time (τ1 + t1) when the voltage controlled oscillator circuit 1 becomes stable (see FIG. 2).
(See (a)), for example, at time t3 (see FIG. 2A), the oscillation frequency of the voltage controlled oscillator circuit 1 becomes stable. After all, in this case, a long frequency pull-in time t3 is required.

Therefore, the time τ2 required for the second control signal generator 9 to output the control signal is set to be longer than the time required for the output frequency to stabilize after the voltage controlled oscillator circuit 1 starts oscillating. By setting so that stable operation can be obtained as described below.

That is, when τ2 ≧ (τ1 + t1) with reference to the time point when the control circuit 10 starts the operation, the second control signal generator 9 controls the time τ2 after the control circuit 10 starts the operation. A signal is output (see FIG. 2G), and the first frequency divider 5 enters the operation start state. And
The output signal of the voltage controlled oscillator circuit 1 which has finished the transient state as described above and has a stable output frequency is frequency-divided by the first frequency divider 5.

As a result, the feedback matching signal first output from the first frequency divider 5 and the reference matching signal from the second frequency divider 6 are synchronized with the phase comparator 4 by forced phase synchronization. It will be input (see FIGS. 2F and 2H). Then, the phase comparison of the two signals is performed by the phase comparator 4
The voltage signal according to the result of the phase comparison is input to the voltage controlled oscillator circuit 1 by the charge pump 3 and the integrating circuit 2 so that the phase difference between the reference matching signal and the feedback matching signal becomes zero. After the time t4, the output frequency of the voltage controlled oscillator circuit 1 is stabilized by the operation of the phase locked loop described in (see the characteristic curve of the solid line in FIG. 3). ).

Therefore, the frequency pull-in is completed without so-called jumping of the output frequency of the voltage controlled oscillator circuit 1 as in the case of τ2 <(τ1 + t1),
As a result, it takes less time to pull in the frequency. The time required to pull in the frequency is τ2 <(τ
It is about half to one third of the time t3 required in the case of 1 + t1).

As described above, in the phase locked loop circuit of the present embodiment, τ2 ≧ (τ1 + t1), that is, the operation of the first frequency divider 5 based on the control signal of the second control signal generator 9 is started. By presetting the output frequency of the voltage controlled oscillator circuit 1 after the time required for the stable state has elapsed, unlike the conventional case, the frequency pull-in can be performed in a short time without causing the frequency jump as described above. Is possible.

[0037]

As described above, according to the present invention, the so-called phase-locked loop operates after the transient state of the output frequency immediately after the start of the operation of the voltage controlled oscillation means. Since the phase-locked loop does not operate based on the output frequency of the voltage-controlled oscillation means in 1), so-called frequency skipping is eliminated unlike in the past, so that the frequency can be pulled in in a shorter time than in the past. That is the effect.

Further, unlike the prior art, the voltage controlled oscillator is not always kept in an operating state, and the frequency can be pulled in in a short time as described above.
The power consumption is less than that of the conventional one, and the power saving effect can be achieved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of a phase locked loop circuit according to the present invention.

FIG. 2 is a timing chart in the main part for explaining the operation of the phase locked loop circuit of the embodiment.

FIG. 3 is a characteristic diagram showing changes in output frequency over time.

FIG. 4 is a circuit diagram showing an embodiment of first and second control signal generators used in the phase locked loop circuit of the embodiment.

FIG. 5 is a characteristic diagram showing a change characteristic of the output frequency after the start of the operation of the voltage controlled oscillator circuit alone.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Voltage controlled oscillation circuit, 2 ... Integration circuit, 3 ... Charge pump, 4 ... Phase comparator, 5 ... First frequency divider,
6 ... 2nd frequency divider, 7 ... Reference signal oscillator, 8 ... 1st control signal generator, 9 ... 2nd control signal generator, 10
... Control circuit

Claims (2)

[Claims] 1. A phase for comparing a phase of an externally input reference signal and an output signal of the voltage controlled oscillation circuit with a voltage controlled oscillation means whose oscillation frequency changes according to the magnitude of an externally input voltage signal. In a phase comparison circuit comprising a comparison means and a voltage generation means for generating a voltage signal according to an output phase difference of the phase comparator and inputting the voltage signal to the voltage control oscillation means, the voltage control oscillation means and the phase Frequency dividing means provided between the voltage controlling oscillator and the comparing means for dividing the output signal of the voltage controlling oscillator, and a transient state after the operation of the voltage controlling oscillator is started and immediately after the operation of the voltage controlled oscillator is started. A phase-locked loop circuit comprising: an operation control unit that sets the frequency dividing unit to an operation start state after a lapse of time. 2. The phase control circuit according to claim 1, wherein the operation control means sets the voltage control oscillation means in an operation state and sets the frequency division means in an operation start state after a transitional state of the voltage control oscillation means. Synchronous circuit control method.