JPH08256020A - Linear compensation circuit - Google Patents

Linear compensation circuit

Info

Publication number
JPH08256020A
JPH08256020A JP5778795A JP5778795A JPH08256020A JP H08256020 A JPH08256020 A JP H08256020A JP 5778795 A JP5778795 A JP 5778795A JP 5778795 A JP5778795 A JP 5778795A JP H08256020 A JPH08256020 A JP H08256020A
Authority
JP
Japan
Prior art keywords
data
initial value
sample data
sample
distortion correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5778795A
Other languages
Japanese (ja)
Inventor
Masaru Adachi
勝 安達
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP5778795A priority Critical patent/JPH08256020A/en
Publication of JPH08256020A publication Critical patent/JPH08256020A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the memory capacity of initial data by memorizing only the specified sample value of the initial value of distortion correction data and preparing the other data while interpolating them. CONSTITUTION: An initial value memory 19 does not store distortion correction amounts corresponding to all modulated signal levels but stores only required sample data. Concerning data between sample data, they are estimated/ interpolated while using data for several samples. Therefore, when they are estimated/interpolated, the sample data intervals are decided so as not to damage compensation characteristics. When a power source is turned on, a microprocessor 17 inputs the distortion correction amount sample data from the initial value memory 19 and calculates data excepting for the omitted sample data according to an estimation/interpolation algorithm while using the sample data for several samples. The calculated data and initial value for correction are written through a data selector 16 into a RAM 14.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は増幅器の非線形性を補償
するための、線形補償回路の改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a linear compensation circuit for compensating the non-linearity of an amplifier.

【0002】[0002]

【従来の技術】従来技術の一例を図2を用いて説明す
る。入力端子より入力された送信データ系列は、波形生
成ROM(Read Only Memory)1に入力される。この波
形生成ROM1には、帯域制限された複素ベースバンド
信号波形データが予め書き込まれており、入力送信デー
タ列に対応した複素ベースバンド信号が読み出される。
この波形生成ROM1の出力は、加算器2によりRAM
(Random Access Memory)14に格納された補償データ
と加算され、上記送信データ列の入力レベルに対して増
幅器5の出力レベルが線形となるように予め補償データ
が与えられる。このRAM14の補償データの内容は、
該補償データと波形生成ROM1からの出力信号とを加
算した結果、増幅器5の非線形歪が打ち消されるよう
に、増幅器5の入出力特性と逆傾向の特性を有する複素
信号波形データが書き込まれている。
2. Description of the Related Art An example of conventional technology will be described with reference to FIG. The transmission data sequence input from the input terminal is input to the waveform generation ROM (Read Only Memory) 1. Band-limited complex baseband signal waveform data is written in advance in the waveform generation ROM 1, and the complex baseband signal corresponding to the input transmission data string is read out.
The output of the waveform generation ROM 1 is transferred to the RAM by the adder 2.
The compensation data is added to the compensation data stored in the (Random Access Memory) 14, and the compensation data is given in advance so that the output level of the amplifier 5 becomes linear with respect to the input level of the transmission data string. The content of the compensation data in the RAM 14 is
As a result of adding the compensation data and the output signal from the waveform generation ROM 1, complex signal waveform data having characteristics opposite to the input / output characteristics of the amplifier 5 is written so that the nonlinear distortion of the amplifier 5 is canceled. .

【0003】次に、この加算器2の出力信号は、DA変
換器・LPF(Low PassFilter)3に入力され、ディジ
タル信号からアナログ信号に変換され、LPFにより不
要成分を除去された後、直交変調器4に与えられる。こ
の直交変調器4では、入力したベースバンド信号で発振
器8の出力信号を直交変調し、増幅器5へ供給する。こ
こで、RAM14の値を適応的に変化させるために、増
幅器5の出力信号の一部を方向性結合器7を介して検出
し、直交復調器9で、発振器8の出力を用いて復調す
る。復調された信号は、LPF・AD変調器10のLP
Fで帯域制限された後、AD変換器により複素ベースバ
ンド信号に変換される。さらに、波形生成ROM1の出
力信号を遅延器15によって遅らせることによりタイミ
ングを合わせた送信ベースバンド信号を得て、このタイ
ミングを合わした送信ベースバンド信号から前記復調信
号を減算器11により減算を行う。この減算器11の出
力信号には、所要の係数K(0<K≦1)を乗算器12
で掛け合わせる。さらに、乗算器12の出力信号は、加
算器13でRAM14の出力信号に加算される。
Next, the output signal of the adder 2 is input to a DA converter / LPF (Low Pass Filter) 3, converted from a digital signal to an analog signal, and unnecessary components are removed by the LPF, followed by quadrature modulation. Given to vessel 4. The quadrature modulator 4 quadrature-modulates the output signal of the oscillator 8 with the input baseband signal and supplies it to the amplifier 5. Here, in order to adaptively change the value of the RAM 14, a part of the output signal of the amplifier 5 is detected via the directional coupler 7 and demodulated by the quadrature demodulator 9 using the output of the oscillator 8. . The demodulated signal is the LP of the LPF / AD modulator 10.
After being band-limited by F, it is converted into a complex baseband signal by an AD converter. Further, the output signal of the waveform generation ROM 1 is delayed by the delay device 15 to obtain a transmission baseband signal with a matched timing, and the demodulated signal is subtracted from the transmission baseband signal with a matched timing by the subtracter 11. The output signal of the subtractor 11 is multiplied by the required coefficient K (0 <K ≦ 1) by the multiplier 12
Multiply by. Further, the output signal of the multiplier 12 is added to the output signal of the RAM 14 by the adder 13.

【0004】以上の動作により、波形生成ROM1の変
調ベースバンド出力信号よりも、復調ベースバンド信号
の方が大きい場合には、RAM14の補償データの内容
を大きくするよう書き替えられ、また、反対に、波形生
成ROM1の変調ベースバンド出力信号よりも、復調ベ
ースバンド信号の方が小さい場合にはRAM14の補償
データの内容を小さくするよう書き替えられる。このよ
うに、増幅器5の特性が変化しても、適応的に追従する
ように制御されている。しかし、電源立ち上げ時等は、
RAM14の値が十分に収束していないため、増幅器の
非線形特性を正確に補償できない。このため、電源立ち
上げ時には、データセレクタ16を介して、増幅器補償
用初期値を初期値ROM19から読み出してRAM14
に書き込み、十分な補償が行えるようにする。この電源
立ち上げ時に、初期値をRAM14に書き込んだ後、デ
ータセレクタ16は波形生成ROM1からの出力信号を
RAM14に供給する。
According to the above operation, when the demodulation baseband signal is larger than the modulation baseband output signal of the waveform generation ROM 1, the compensation data in the RAM 14 is rewritten so as to be larger, and vice versa. If the demodulation baseband signal is smaller than the modulation baseband output signal of the waveform generation ROM 1, the content of the compensation data in the RAM 14 is rewritten so as to be smaller. In this way, even if the characteristic of the amplifier 5 changes, it is controlled so as to follow adaptively. However, when the power is turned on,
Since the value of the RAM 14 is not sufficiently converged, the nonlinear characteristic of the amplifier cannot be accurately compensated. Therefore, when the power is turned on, the amplifier compensation initial value is read from the initial value ROM 19 via the data selector 16 and the RAM 14 is read.
Please write in and allow sufficient compensation. When the power is turned on, after writing the initial value to the RAM 14, the data selector 16 supplies the output signal from the waveform generation ROM 1 to the RAM 14.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、前述の
従来技術では、変調ベースバンド信号すべてに対して、
増幅器補償用初期データを持っていなければならず、保
持するデータ量が非常に多いという欠点を有していた。
本発明の目的は、この欠点を除去し、初期データのメモ
リ容量を低減した線形補償回路を提供することにある。
However, in the above-mentioned prior art, for all modulated baseband signals,
Since the initial data for compensating the amplifier must be stored, the amount of data to be stored is very large.
An object of the present invention is to eliminate this drawback and provide a linear compensation circuit with a reduced initial data memory capacity.

【0006】[0006]

【課題を解決するための手段】本発明は、上記の目的を
達成するために、電力増幅器の非線形歪は、緩やかな歪
成分であって、その歪補正データも緩やかな特性である
ことに着目し、歪補正データ初期値の特定のサンプル値
だけをメモリしておき、その他のデータは補間すること
によって作成するように構成したものである。
In order to achieve the above object, the present invention focuses on that the non-linear distortion of a power amplifier is a gradual distortion component and its distortion correction data is also a gradual characteristic. However, only a specific sample value of the distortion correction data initial value is stored in memory, and other data is created by interpolation.

【0007】[0007]

【作用】その結果、波形生成ROM1の出力であるベー
スバンド信号全てに対して、増幅器補償用初期データを
メモリしておく必要が無く、補間に必要な最低限のサン
プルデータのみをメモリしておけば良いので、大幅にメ
モリ量を削減することが可能である。
As a result, it is not necessary to store the amplifier compensation initial data for all the baseband signals output from the waveform generation ROM 1, but only the minimum sample data required for interpolation. Since it is enough, it is possible to significantly reduce the memory amount.

【0008】[0008]

【実施例】本発明の実施例を図1および図3を用いて説
明する。なお、プレディストーションの動作について
は、従来例と同じである。図3は、波形生成ROM1の
出力信号と歪補正値との関係を示した図である。図1に
示す初期値メモリ19には、図3に示すような全ての変
調信号レベルに対して歪補正量を記憶させておくのでは
なく、所要のサンプルデータ(●印のデータ)のみを記
憶させておく。サンプルデータ間のデータ(○印のデー
タ)については、数サンプルのサンプルデータを用い、
推定/補間を行う。従って、サンプルデータ間隔は、推
定/補間を行った場合、補償特性を損なわない間隔とす
る。電源立ち上げ時、マイクロプロセッサ17は、初期
値メモリ19からの歪補正量サンプルデータを入力し、
欠落しているサンプルデータ以外のデータを数サンプル
のサンプルデータを用い、推定/補間アルゴリズムより
算出する。このようにして算出されたデータ、およびサ
ンプルデータからなる補償用初期値を、データセレクタ
16を介し、RAM14に書き込む。この電源立ち上げ
時に初期値をRAM14に書き込んだ後、データセレク
タ16は波形生成ROM1からの出力信号をRAM14
に供給する。
Embodiments of the present invention will be described with reference to FIGS. 1 and 3. The operation of predistortion is the same as the conventional example. FIG. 3 is a diagram showing the relationship between the output signal of the waveform generation ROM 1 and the distortion correction value. The initial value memory 19 shown in FIG. 1 does not store the distortion correction amount for all modulation signal levels as shown in FIG. 3, but stores only required sample data (data indicated by ●). I will let you. For the data between the sample data (data with circles), use sample data of several samples,
Estimate / interpolate. Therefore, the sample data interval is an interval that does not impair the compensation characteristics when the estimation / interpolation is performed. When the power is turned on, the microprocessor 17 inputs the distortion correction amount sample data from the initial value memory 19,
Data other than the missing sample data is calculated by an estimation / interpolation algorithm using sample data of several samples. The compensation initial value composed of the data thus calculated and the sample data is written in the RAM 14 via the data selector 16. After writing the initial value to the RAM 14 when the power is turned on, the data selector 16 outputs the output signal from the waveform generation ROM 1 to the RAM 14.
Supply to.

【0009】[0009]

【発明の効果】以上述べたように、本発明によれば、記
憶させておく増幅器補償用初期データ量を大幅に減少さ
せることが可能となり、メモリ容量を削減することが可
能となる。初期値メモリのメモリ容量は、サンプルデー
タ間隔をN(Nは2以上の自然数)とすると、1/Nの
容量ですみ、大幅なメモリ容量の削減を実現することが
できる。
As described above, according to the present invention, the amount of initial data for amplifier compensation to be stored can be greatly reduced, and the memory capacity can be reduced. Regarding the memory capacity of the initial value memory, if the sample data interval is N (N is a natural number of 2 or more), the capacity is only 1 / N, and a significant reduction in memory capacity can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の構成を示すブロック図。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

【図2】従来技術の一例を示すブロック図。FIG. 2 is a block diagram showing an example of a conventional technique.

【図3】波形生成ROM出力と歪補正値の関係を示す
図。
FIG. 3 is a diagram showing a relationship between a waveform generation ROM output and a distortion correction value.

【符号の説明】[Explanation of symbols]

1…波形生成ROM 2…加算
器 3…D/A・LPF 4…直交
変調器 5…増幅器 6…アン
テナ 7…方向性結合器 8…発振
器 9…直交復調器 10…L
PF・A/D 11…減算器 12…乗
算器 13…加算器 14…R
AM 15…遅延器 16…デ
ータセレクタ 17…マイクロプロセッサ 19…初
期値ROM
1 ... Waveform generation ROM 2 ... Adder 3 ... D / A / LPF 4 ... Quadrature modulator 5 ... Amplifier 6 ... Antenna 7 ... Directional coupler 8 ... Oscillator 9 ... Quadrature demodulator 10 ... L
PF / A / D 11 ... Subtractor 12 ... Multiplier 13 ... Adder 14 ... R
AM 15 ... Delay device 16 ... Data selector 17 ... Microprocessor 19 ... Initial value ROM

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 入力信号に補償データを加算する加算手
段と、この加算後の信号を増幅する増幅手段と、該増幅
手段の出力信号と上記入力信号とが与えられ上記補償デ
ータを算出する算出手段とを備えた線形補償回路におい
て、 予め所要数のサンプルデータが格納されたメモリ手段
と、該サンプルデータを補間推定して初期補償データを
算出する手段とを具備することを特徴とする線形補償回
路。
1. Computation for calculating the compensation data given an addition means for adding compensation data to an input signal, an amplification means for amplifying the signal after the addition, and an output signal of the amplification means and the input signal. A linear compensating circuit comprising: means for storing a predetermined number of sample data in advance; and means for interpolating and estimating the sample data to calculate initial compensation data. circuit.
JP5778795A 1995-03-16 1995-03-16 Linear compensation circuit Pending JPH08256020A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5778795A JPH08256020A (en) 1995-03-16 1995-03-16 Linear compensation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5778795A JPH08256020A (en) 1995-03-16 1995-03-16 Linear compensation circuit

Publications (1)

Publication Number Publication Date
JPH08256020A true JPH08256020A (en) 1996-10-01

Family

ID=13065604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5778795A Pending JPH08256020A (en) 1995-03-16 1995-03-16 Linear compensation circuit

Country Status (1)

Country Link
JP (1) JPH08256020A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006050073A (en) * 2004-08-02 2006-02-16 Fujitsu Ltd Distortion compensating apparatus
JP2009246854A (en) * 2008-03-31 2009-10-22 Sony Corp Electronic apparatus, dispersion adjustment method of ic internal components section of electronic apparatus, and ic
JP2009246852A (en) * 2008-03-31 2009-10-22 Sony Corp Electronic apparatus, dispersion adjustment method of ic internal component section of electronic apparatus, and ic
JP2009246853A (en) * 2008-03-31 2009-10-22 Sony Corp Electronic apparatus, dispersion adjustment method of ic internal component section of electronic apparatus, and ic

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006050073A (en) * 2004-08-02 2006-02-16 Fujitsu Ltd Distortion compensating apparatus
JP4492246B2 (en) * 2004-08-02 2010-06-30 富士通株式会社 Distortion compensation device
JP2009246854A (en) * 2008-03-31 2009-10-22 Sony Corp Electronic apparatus, dispersion adjustment method of ic internal components section of electronic apparatus, and ic
JP2009246852A (en) * 2008-03-31 2009-10-22 Sony Corp Electronic apparatus, dispersion adjustment method of ic internal component section of electronic apparatus, and ic
JP2009246853A (en) * 2008-03-31 2009-10-22 Sony Corp Electronic apparatus, dispersion adjustment method of ic internal component section of electronic apparatus, and ic
US8121578B2 (en) 2008-03-31 2012-02-21 Sony Corporation Electronic apparatus, dispersion adjustment method of IC internal component section of electronic apparatus and IC
US8676146B2 (en) 2008-03-31 2014-03-18 Sony Corporation Electronic apparatus, dispersion adjustment method of IC internal component section of electronic apparatus and IC

Similar Documents

Publication Publication Date Title
JP3156439B2 (en) Distortion compensation circuit
JP2883260B2 (en) Distortion compensation circuit
US6141390A (en) Predistortion in a linear transmitter using orthogonal kernels
US5867065A (en) Frequency selective predistortion in a linear transmitter
CA2200387C (en) Method of correcting nonlinearities of an amplifier, and radio transmitter employing a method of this type
US6373902B1 (en) Device and method for linearizing transmitter in digital communication system
US5905760A (en) Method of correcting nonlinearities of an amplifier, and radio transmitter employing a method of this type
US20040208259A1 (en) Additive digital predistortion system employing parallel path coordinate conversion
JP3560398B2 (en) Amplifier with distortion compensation
CA2347407A1 (en) A linear amplifier arrangement
WO1999022444A1 (en) Linearization method and amplifier arrangement
JP3994308B2 (en) Predistortion type distortion compensation circuit
JP4168259B2 (en) Nonlinear distortion compensation circuit, nonlinear distortion compensation method, and transmission circuit
JPH0580856B2 (en)
JP3268135B2 (en) transceiver
CN1578119B (en) Non-linear compensation circuit, transmission apparatus and non-linear compensation method
EP1170859B1 (en) Distortion compensation method and apparatus
JP2007049621A (en) Pre-distortion amplifying device
JPH08256020A (en) Linear compensation circuit
JP3187251B2 (en) Distortion compensation circuit
JP5673475B2 (en) Distortion compensation apparatus and distortion compensation method
JP2002141754A (en) Pre-distortion device
JP3254794B2 (en) Modulation device and modulation method
JPH0531326B2 (en)
JPH0363265B2 (en)