JPH08251537A - Digital signal recording device and reproducing device - Google Patents

Abstract

PURPOSE: To improve the image quality at the time of high speed reproduction by recording an error check code and special reproduction data for usual reproduction and special reproduction to an area to record the error check code. CONSTITUTION: A 1st error correction code circuit 31 adds an error check code for special reproduction to data in 2nd and 3rd memories 16, 17 when error correction is coded for special reproduction based on an externally received command information signal. A rate discrimination circuit 18 detects a transmission rate of a transport packet to be received. A recording data control circuit 19 sets a recording mode of a digital VTR based on a recording data rate and outputs various control signals based on the setting result and controls 1st-3rd correction coding circuits 31, 22, 32 based on external command information. When recording data to be recorded on a magnetic recording tape are generated, any of usual reproduction error check code, usual reproduction data and special reproduction error check code and special reproduction data is recorded in an area recording the error check code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video tape recorder (hereinafter referred to as a digital VTR) having a track format for recording a digital video signal and a digital audio signal in each of predetermined areas of an oblique track, and digital. In a disc player or the like, a digital video signal and a digital audio signal are input as a bit stream, a digital signal recording device for recording the bit stream, and a digital signal reproducing device for reproducing the recording medium recorded by the digital signal recording device. It is about.

[0002]

2. Description of the Related Art FIG. 27 is a track pattern diagram of a conventional general household digital VTR. In the figure, a diagonal track is formed on the magnetic tape, and one track is a video area for recording a digital video signal,
It is divided into two areas, an audio area for recording digital audio signals.

There are two methods for recording video and audio signals on such a home digital VTR. One is a so-called baseband recording method in which an analog video signal and an audio signal are input and the video signal and the audio signal are subjected to high-efficiency coding to reduce the data rate for recording. The other is a so-called transparent recording system for recording a digitally transmitted bit stream.

ATV being discussed in the United States
(Advanced Television) signal, or DVB (Digital) under consideration in Europe.
The latter transparent recording method is suitable for recording a video broadcasting signal. The reason is that the ATV signal or the DVB signal is a signal that has already been digitally compressed, and a high-efficiency encoder and a decoder are not required, and since it is recorded as it is, there is no deterioration in image quality. On the other hand, the disadvantage is that
This is the image quality during special playback such as high-speed playback and still and slow motion. Particularly, if the bit stream is recorded on the diagonal track as it is, almost no image can be reproduced at the time of high speed reproduction.

Hereinafter, as a digital VTR system for recording the above-mentioned ATV signal, October 26, 1993.
"Int" held in Ottawa, Canada from the 28th to the 28th
international workshop on HD
"A Record" for the technology announcement on TV '93
ing Method of ATV data on
a Consumer Digital VCR ". The contents will be described below as a conventional example.

As a basic specification of a home digital VTR prototype, SD (Standard Define) is used.
mode), the recording rate of the digital video signal is 25 Mbps, and the field frequency is 60 Hz.
In some cases, one frame of video is recorded in a video area of 10 tracks. Here, if the data rate of the ATV signal is set to 17 to 18 Mbps, transparent recording of the ATV signal becomes possible in this SD mode.

FIG. 28 is a diagram showing the head scanning loci of the rotary head during normal reproduction of the digital VTR and during high-speed reproduction. In the figure, adjacent tracks are alternately recorded obliquely by a rotary head having different azimuth angles. During normal reproduction, the tape feed speed is the same as during recording, so the rotary head can trace along the recording track as shown in FIG. 28 (a). However, during high speed reproduction, the tape speeds are different, so that it is possible to trace across several tracks and reproduce only the fragments of each same azimuth track. FIG. 28B shows the case of fast-forwarding at 5 times speed.

An MPEG2 bitstream (ATV signal and DVB signal bitstreams are MPEG2
Compliant with the bitstream of), only intra-coded blocks can be independently decoded without reference to other frames. If the MPEG2 bit stream is recorded on each track in sequence, the reproduction data at the time of high-speed reproduction is separated from the intra-coded data from the reproduction signal intermittently reproduced, and is intra-coded. The image will be reconstructed using only the data. At this time, the reproduced area is not continuous on the screen, and the block fragments spread on the screen. Moreover, since the bitstream is variable length coded, there is no guarantee that all of the screen will be updated periodically, and some may not be updated for a long time. As a result, the image quality during high-speed playback is not sufficient,
It would be unacceptable for home digital VTRs.

FIG. 29 is a block circuit diagram of a conventional bit stream recording apparatus capable of high speed reproduction. here,
The video area of each track is divided into a main area for recording a bit stream of all ATV signals and a copy area for recording an important part (HP data) of the bit stream used when an image is constructed during high speed reproduction. During high-speed playback, only the intra-coded block is effective, so this is recorded in the copy area. However, in order to further reduce the data, the low-frequency components are extracted from all intra-coded blocks and the HP data To record as. In FIG. 29, 1 is a bit stream input terminal, 2 is a bit stream output terminal, 3 is an HP data output terminal, 4 is a variable length decoder, 5 is a counter, 6 is a data sampling circuit, and 7 is EOB (End). of Blo
ck) is an additional circuit.

The MPEG2 bit stream is input from the input terminal 1 and output from the output terminal 2 as it is,
It is sequentially recorded in the main area. On the other hand, the bit stream from the input terminal 1 is also input to the variable length decoder 4,
The syntax of the MPEG2 bit stream is analyzed, an intra image is detected, timing is generated by a counter 5, a low frequency component of all blocks of the intra image is extracted by a data extracting circuit 6, and E
The OB adding circuit 7 adds EOB to form HP data and records it in the copy area.

FIG. 30 is a diagram showing an outline of the conventional digital VTR during normal reproduction and high-speed reproduction. During normal playback, all bitstreams recorded in the main area are played back, and MPEG outside the digital VTR is played.
2 sent to the decoder and the HP data is discarded. On the other hand, during high speed reproduction, only HP data in the copy area is collected and sent to the decoder, and the bit stream in the main area is discarded.

Next, the arrangement of the main area and the copy area on one track will be described. FIG. 31 is a diagram showing an example of a rotary head scanning locus during general high-speed reproduction. If the tape speed is an integral multiple speed and phase lock control is performed, head scanning is synchronized with the same azimuth track.
Therefore, the position of the reproduced data is fixed. Figure 31
In the above, assuming that a portion in which the output level of the reproduction signal is higher than −6 dB is reproduced, a shaded area is reproduced by one head. FIG. 31 shows an example of 9x speed, and at 9x speed, signal reading of this shaded area is guaranteed. Therefore, HP data may be recorded in this area. However, at other speeds, signal reading is not guaranteed and this area must be chosen for reading at some tape speeds.

FIG. 32 is a diagram for explaining the overlap areas at a plurality of conventional high speed reproduction speeds, and shows an example of three tape speed scan areas in which the heads are synchronized with the same azimuth track. The area scanned at each tape speed has some overlapping areas. A copy area is selected from these areas to ensure the reading of HP data at different tape speeds. In FIG. 32, 4 times, 9 times,
Although the case of fast-forwarding at 17 times is shown, these scan areas are the same as the case of fast-forwarding at -2 times, -7 times, and -15 times.

At some tape speeds it is not possible for the head to trace the exact same area. This is because the number of tracks traversed by the head differs depending on the tape speed. In addition, it should be possible to trace from any one of the same azimuth tracks. FIG. 33 shows a conventional digital VTR.
FIG. 6 is a diagram showing rotary head scanning loci at 5 × speed and 9 × speed in FIG. In the figure, areas 1, 2, and 3 are selected from the overlapping area of 5 × speed and 9 × speed. By repeatedly recording the same HP data on 9 tracks, the HP data can be read at either 5 × speed or 9 × speed.

FIG. 34 is a view showing two rotary head scanning loci during 5 × speed reproduction in a conventional digital VTR. As can be seen from the figure, by repeatedly recording the same HP data on the same number of tracks as the tape speed,
Data can be read by the head synchronized with the same azimuth track. Therefore, by duplicating the HP data for the same number of tracks as the maximum tape speed for high-speed reproduction, the duplicate HP data can be guaranteed to be read at both the forward and backward directions at some tape speeds. You can

FIG. 35 is a track layout diagram in a conventional digital VTR, showing an example of a main area and a copy area. In the home digital VTR, the video area of each track is composed of 135 sync blocks, the main area is 97 sync blocks, and the copy area is 32 sync blocks. This copy area is shown in FIG.
The overlapping areas corresponding to 4 ×, 9 ×, and 17 × speeds are selected. In this case, the main area data rate is about 1
Since the same data is recorded in the copy area 17 times at 7.46 Mbps, it becomes about 338.8 kbps.

[0017]

The conventional home-use digital VTR is constructed as described above, and since the special reproduction data is recorded in the copy area several times in duplicate, the special reproduction data is recorded. The recording rate is extremely low, and there is a problem that the reproduced image quality cannot be sufficiently obtained particularly in slow reproduction or high speed reproduction. For example,
If the number of intra-frames is 2 frames / sec, the data amount of only ATV signal intra-coded is predicted to be about 3 Mbps, but in the conventional example, only about 340 Kbps can be recorded, and the reproduced image quality is extremely deteriorated.

The DVB signal has a different recording rate depending on the program. Specifically, the current PAL or S
The image quality of ECAM is about 5 to 5.5 Mbps, and that of "studio quality" is 9 Mbps.
The amount of data is about the same. When recording a recording signal having a plurality of recording rates on the digital VTR, the following problems occur. For example, when recording the 9 Mbps program on the digital VTR, since the recording rate of the main area is 17.46 Mbps as described above, nothing is recorded in the area of about 8.5 Mbps and the usage efficiency of the magnetic tape is improved. There was a problem that it was very bad.

The present invention has been made to solve the above problems, and particularly, effectively utilizes a limited area for recording data for high-speed reproduction, and reliability of reproduction data at high-speed reproduction. It is an object of the present invention to provide a digital signal recording device for efficiently recording a multi-rate recording signal on a recording medium, and a digital signal reproducing device for reproducing the recording medium while improving the image quality.

[0020]

According to a first aspect of the present invention, there is provided a digital signal recording apparatus having a plurality of recording modes including at least a standard recording mode, in a frame or field input in a transport packet state. ,
Alternatively, in a digital signal recording device for transparently recording a frame- or inter-field encoded digital video signal and a digital audio signal on a recording medium, a transmission rate determination means for determining the transmission rate of the input transport packet. Recording mode setting means for setting the recording mode of the digital signal recording device based on the above-mentioned discrimination result, data separating means for separating a frame or field encoded digital video signal from the transport packet, and the data. Special reproduction data generating means for generating special reproduction data by reconstructing the frame- or field-encoded digital video signal separated by the separating means, and the transport packet,
The area for recording the error check code is usually provided with a recording format generating means for generating a recording format so as to record the special reproduction data and the error check code at a predetermined position of a track on a recording medium. The recording format generating means is controlled so as to record any one of the reproduction error check code, the normal reproduction data, the special reproduction error check code, and the special reproduction data.

A digital signal recording apparatus according to a second aspect of the present invention is configured to generate the special reproduction data in the form of the transport packet.

Further, in the digital signal recording apparatus according to the third aspect of the present invention, when the recording format generating means generates the sync block format, the data of 5 sync blocks is generated by using the two transport packets. It is configured to do.

Further, in the digital signal recording apparatus according to the fourth aspect of the present invention, when the recording format is generated, the special reproduction is performed on the scanning locus scanned by the head at the predetermined high reproduction speed of each recording mode. The recording format generating means is controlled so as to arrange the data.

Further, in the digital signal recording apparatus according to the fifth aspect of the present invention, when the recording format is generated, the head scans the subcode area or the VAUX area at a predetermined high reproduction speed of each recording mode. The recording format generating means is controlled so that the special reproduction data is arranged on the scanning locus.

A digital signal reproducing apparatus according to a sixth aspect of the present invention has a plurality of recording modes including a standard recording mode and records special reproduction data separated from the recording data in a predetermined area. In a digital signal recording / reproducing apparatus for reproducing a recording medium, recording mode detecting means for detecting the recording mode from a reproduction signal, recording medium traveling speed means for controlling the tape traveling speed of the recording medium based on the recording mode detection result, In the recording mode, the head has a tracking control means for controlling the tracking so that the head scans the subcode area or the VAUX area during high-speed reproduction at a predetermined tape traveling speed.

[0026]

In the digital signal recording apparatus according to the first aspect of the present invention, the digital signal recording apparatus has a plurality of recording modes including at least the standard recording mode, and is in the frame or field input in the state of the transport packet, or in the frame or field. In a digital signal recording device that transparently records an inter-coded digital video signal and a digital audio signal on a recording medium, first, the transmission rate of the input transport packet is determined. Then, the transmission rate determining means and the recording mode of the digital signal recording device are set based on the determination result. On the other hand, the digital video signal encoded in the frame or in the field from the input transport packet is separated from the transport packet. Then, the separated digital video signal subjected to the frame or intra-field encoding is reconstructed and converted into special reproduction data. Then, in order to record the input transport packet, the special reproduction data, and the error check code at a predetermined position of the track on the recording medium, the recording format is formed in the recording format generating means. When recording data to be recorded on the magnetic recording tape by the recording format generating means, in the area for recording the error check code, the error check code for normal reproduction, the normal reproduction data, and the error check for special reproduction are written. The recording format generating means is controlled so as to record either the code or the special reproduction data.

Further, in the digital signal recording apparatus according to the second aspect of the present invention, when the special reproduction data is generated, the special reproduction data is generated in the form of a transport packet including the transport header.

Further, in the digital signal recording apparatus according to the third aspect of the present invention, the recording format generating means collects two input transport packets. Then, the data of these two transport packets is converted into data of 5 sync blocks and recorded in a predetermined area for recording the data for normal reproduction and the data for special reproduction.

Further, in the digital signal recording apparatus according to the fourth aspect of the present invention, when the recording format is generated, the special reproduction is performed on the scanning locus scanned by the head at a predetermined high reproduction speed of each recording mode. Place the data for use. Then, the recording format generating means is controlled so as to record in the special reproduction data recording area generated by the special reproduction data generating means.

Further, in the digital signal recording apparatus according to the fifth aspect of the present invention, when the recording format is generated, the head scans the subcode area or VAUXX area at a predetermined high reproduction speed of each recording mode. The recording format generating means is controlled so that the special reproduction data is arranged on the scanning locus.

Further, in the digital signal reproducing apparatus according to the sixth aspect of the present invention, the digital signal reproducing apparatus has a plurality of recording modes including the standard recording mode, and the special reproduction data separated from the recording data is stored in a predetermined area. In a digital signal recording / reproducing apparatus for reproducing a recorded recording medium, the recording mode is detected from a reproduction signal during reproduction. Then, the tape running speed of the recording medium is controlled based on the recording mode detection result. At that time, the tracking is controlled so that the head scans the subcode area or the VAUX area during high-speed reproduction at a predetermined tape running speed in the recording mode.

[0032]

【Example】

Example 1. FIG. 1 is a digital VTR according to a first embodiment of the present invention.
3 is a block circuit diagram of the recording system of FIG. In the figure, reference numeral 1 is a transport packet input terminal. Reference numeral 10 detects a transport header in a transport packet and also detects a header such as a sequence header or a picture header included in a bitstream to detect a frame,
Alternatively, a header analysis circuit for separating intra-field encoded (hereinafter referred to as intra-encoded) data, 11 is a parallel / serial conversion for converting an input transport packet into 1-bit bit stream data.
A serial circuit (hereinafter, referred to as P / S conversion circuit) 12 is a bit stream of an image (hereinafter, referred to as an intra image) coded in a frame or field based on the header information detected by the header analysis circuit 10. The data is separated, and each high reproduction speed (25 Mbp of the first embodiment is
4x speed and 18x speed in s recording mode, 12.5
4x speed and 18x speed in Mbps recording mode,
8x speed and 36 in 6.25Mbps recording mode
It is a special reproduction data generation circuit for generating special reproduction data at double speed.

A storage packet 13 stores the transport packet input from the input terminal 1 once in the memory and, at the time of outputting the data, converts it into the sync block format shown in FIG. 13B (details will be described later). 1 is a memory, 14 is a quadruple speed reproduction data generation circuit for generating a quadruple speed special reproduction transport packet using the quadruple speed reproduction data output from the special reproduction data generation circuit 12, and 15 is a special The 18x speed reproduction data generation circuit generates 18x speed special reproduction transport packets using the 18x speed reproduction data output from the reproduction data generation circuit 12. It should be noted that the first embodiment has three types of recording modes as will be described later, and the high-speed reproduction speed supported in each recording mode is different. The data and the data for high speed reproduction on the high speed side are referred to as 18 × speed reproduction data.

Reference numeral 16 temporarily stores in the memory the data for quadruple speed reproduction input in the form of transport packets, and converts the data into a sync block format when outputting the data (see FIG. 13, details will be described later). The second memory 17, 17 temporarily stores the 18 × speed reproduction data input in the form of transport packets in the memory, and converts it into a sync block format when outputting the data (see FIG. 13, details will be described later). This is the third memory. Reference numeral 31 denotes an error check code for special reproduction (hereinafter referred to as “error check code for special reproduction” when performing error correction coding for special reproduction on the data in the second memory 16 and the third memory 17 by an externally input command information signal. A first error correction code circuit for adding a C5 check code), 18 is a rate discriminating circuit for detecting the transmission rate of an input transport packet, and 19 is a recording data rate output from the rate discriminating circuit 18. The recording mode of the digital VTR is set, various control signals are output based on the setting result, and the first error correction code circuit 31 and the second error correction code circuit 22 (described later) are output by command information from the outside. A recording data control circuit for controlling a third error correction code circuit 32 (described later). Reference numeral 33 is an input terminal for inputting command information from the outside.

Reference numeral 20 denotes an input transport packet output from the first memory 13 and the second memory 16,
And a data synthesizing circuit that rearranges the respective special reproduction data output from the third memory 17 in the order of a predetermined sync block (the various data are the first data
13 is converted into the sync block format shown in FIG. 13B in the memory 13, the second memory 16, and the third memory 17, and 21 is the fourth memory.
Reference numeral 22 denotes a command information signal externally input to the recorded data stored in the fourth memory 21, and an error check for normal reproduction accompanied by interleaving of 10 tracks when error correction coding for normal reproduction is performed. A second error correction code circuit for adding a code (hereinafter referred to as C4 check code) (interleave at the time of error correction coding for normal reproduction will be described later), 32 is a C4 check code in the fourth memory 21. It is a third error correction code circuit that adds error correction check codes in the horizontal direction (C1 check code) and vertical direction (C2 check code) defined in the SD standard to the added data. Reference numerals 23a and 23b denote digital modulation circuits that perform digital modulation on the recording data to which the error correction check code is added and output from the fourth memory 21. In addition,
The ID information and sync information are added to the data of each sync block at the time of input to the digital modulation circuits 23a and 23b. Reference numerals 24a and 24b are recording amplifiers, 25 is a rotary drum, 26a is a rotary head for recording / reproducing A track data, and 26b is a rotary head for recording / reproducing B track data. 27 is a drum motor control circuit for controlling the drum motor 28, 28 is a drum motor, 29 is a capstan motor control circuit for controlling the capstan motor 29, and 30 is a capstan motor.

FIG. 2 is a block diagram showing an example of the arrangement of the trick play data generation circuit 12 of the first embodiment. In addition, in the figure, the portions denoted by the same reference numerals as those of the conventional example shown in FIG.
The configuration and operation are the same. Reference numeral 35 is an input terminal for inputting a bitstream of data encoded in a frame or field (hereinafter referred to as intra data), 36 is an input terminal for a control signal output from the recording data control circuit 19, and 37a is quadruple speed reproduction. The data output terminal 37b is an output terminal for 18x speed reproduction data.
Reference numeral 4 is a variable length decoder for performing variable length decoding on the input intra data, 5 is a counter, 6a is a data extracting circuit for extracting data for 4 × speed reproduction from the bit stream of the input intra data, and 6b is also 18 × speed reproduction. A data extracting circuit for extracting the data for reproduction, 7a is provided at the end of each DCT block of the data for quadruple speed reproduction at the EOB (En
An EOB adding circuit for adding a d Of Block) code, and an EOB adding circuit 7b for adding an EOB to the end of each DCT block of 18 × speed reproduction data.

FIG. 3 is a block diagram showing an example of the structure of the quadruple speed reproduction data generation circuit 14 of the first embodiment. 4
Since the double-speed reproduction data generation circuit 14 and the 18-speed reproduction data generation circuit 15 have the same circuit configuration, the detailed description of the 18-speed reproduction data generation circuit 15 is omitted here. In the figure, reference numeral 40 denotes a transport header, a sequence header output from the header analysis circuit 10,
An input terminal for header information such as a picture header and additional information such as a quantization table, 41 is an input terminal for quadruple speed reproduction data output from the special reproduction data generation circuit 12, and 42 is an input terminal 40. A transport header correction circuit that corrects and outputs the transport header, and 43 is a header such as a sequence header or a picture header detected by the header analysis circuit 10 in the quadruple speed reproduction data output from the special reproduction data generation circuit 12. A header adding circuit for adding information and additional information (quantization table information and the like) necessary for decoding the 4 × speed reproduction data, and 44 is serial / parallel conversion to bit stream data output from the header adding circuit 43. Generates 8-bit data with 1 byte, and collects 184 bytes of data. A packetizing circuit forming a data portion of the transport packet, 45 is a transport header adding circuit for adding the transport header output from the transport header modifying circuit 42 to the data of the transport packet output from the packetizing circuit 44. Is.

FIG. 4 shows the recording data control circuit 19 of the first embodiment.
It is a block diagram showing an example of 1 composition. In the figure, 50
Is a recording data rate input terminal output from the rate determining circuit 18, 51, 52, 53 and 54 are output terminals for various control signals, and 55 is a digital signal based on recording data rate information input via the input terminal 50. A recording mode setting circuit for setting the recording mode of the VTR, 56 is a data combining circuit 20, a third error correction code circuit 32, based on the recording mode signal output from the recording mode setting circuit 55.
And a control signal such as a timing signal for generating recording data to the digital modulation circuits 23a and 23b, and recording amplifiers 24a and 24b.
Is a recording timing generation circuit for outputting a recording control signal for recording data on the magnetic tape, and 57 is a code for controlling the code amount of various special reproduction data based on the recording mode signal output from the recording mode setting circuit 55. A special reproduction data code amount setting circuit for outputting an amount control signal, and 58 a servo system reference signal generating circuit.

FIG. 5 is a block diagram showing a configuration example of the data synthesizing circuit 20 of the first embodiment. In the figure, 121,
122 and 123 are the first memory 13 and the second memory, respectively.
Of the memory 16 and the third memory 17, the input terminal for inputting a control signal for setting the number of repetitions of the same data output from the recording data control circuit 19 for each recording mode. A terminal, 126 is a format generation circuit that generates a predetermined recording format, 127 is a format generation circuit control circuit that controls the format generation circuit 126 based on a repeat count control signal, and 128 is an output terminal to the fourth memory 121. is there.

FIG. 6A is a diagram showing an example of the head arrangement of the rotary heads 26a and 26b on the rotary drum 25 of the digital VTR for recording a multi-rate bit stream, and FIG. The rotary heads 26a and 2 when recording data on a magnetic tape using the digital VTR having the rotary head arrangement shown in a).
It is a figure which shows the scanning trace of 6b. In the first embodiment, FIG.
The rotary drum 25 shown in (a) is controlled at 9000 rpm to record the recording data on the magnetic tape. When data is recorded using the rotary heads 26a and 26b, the data is recorded on the magnetic tape substantially simultaneously by the rotary heads 26a and 26b arranged adjacent to each other as shown in FIG. 6B. .

FIG. 7 is a diagram showing the recording mode of the digital VTR for recording the multi-rate bit stream of the first embodiment. In the first embodiment, there are a 25 Mbps recording mode (hereinafter referred to as a standard recording mode), a 12.5 Mbps recording mode (hereinafter referred to as a 1/2 times recording mode), and a 6.25 Mbps recording mode (hereinafter referred to as a 1/4 times recording mode). A case of a digital VTR having three kinds of recording modes will be described.

FIG. 10 is a data format diagram of a video signal recording area in one track of a video signal according to the SD standard. According to the SD standard, a Reed-Solomon code of (85, 77, 9) (hereinafter referred to as C1 check code) in the recording direction and an error correction code of the video area in the vertical direction (14) are used as error correction codes in the video area.
9,138,12) Reed-Solomon code (hereinafter C2
It is written as a check code. ) Is used. Further, as an error correction code in the audio signal area, a (85, 77, 9) Reed-Solomon code (C1) similar to the video signal in the recording direction is used.
As the check code, a (14, 9, 6) Reed-Solomon code (hereinafter, referred to as a C3 check code) is used in the vertical direction.

FIG. 11 is a diagram showing the structure of one sync block in the SD standard. According to the SD standard, one sync block data is composed of 90 bytes as shown in FIG. 11, of which the first 5 bytes are the sync pattern and the ID.
A signal is recorded, and an error correction code (C1 detection code) is recorded in the rear 8 bytes.

FIG. 12 is a diagram showing a recording format in one track of the SD standard. In the SD standard, as described above, as shown in FIG. 12 (or FIG. 10), 149 sync blocks are prepared as an area for recording video data per track. Among them, 3 sync blocks are VA
As a UX data recording area (note that the VAUX data recording area is located at two locations, one is 2 sync blocks, and the other is 1 sync block).
The sync block is provided as an error correction code recording area (C2 check code). Further, one sync block is composed of 90 bytes as shown in FIG.
A sync pattern and an ID signal are recorded in the first 5 bytes, and an error correction code (C1 detection code) is recorded in the last 8 bytes. Therefore, the data that can be stored in one sync block is 77 bytes.

FIG. 13 is a diagram showing a sync block format according to the first embodiment. FIG. 13 (a) is a transport packet diagram included in an input bit stream (or data), and FIG. 13 (b) is recorded on a magnetic tape. FIG. 3 is a block diagram of a recording sync. The bit stream input from the input terminal 1 includes a digital video signal, a digital audio signal, and further digital data relating to the video signal and the audio signal, which are converted into transport packets shown in FIG. It is separated and transmitted. The packet is composed of a 4-byte header part and a 184-byte data part.

In the first embodiment, the bit stream is detected in transport packet units, and the two detected transport packets are recorded data blocks of 5 sync blocks (sync block format) as shown in FIG. 13B. Convert and record. In FIG. 13B, H1 is the first header and H2 is the second header.
Identification data and the like indicating which sync block of 5 sync blocks (the data area in one sync block is composed of 77-byte data as shown in FIG. 11) are recorded in H1. Identification data such as video data or audio data is recorded in H2. In addition,
The sync byte added to the beginning of each transport header does not have to be recorded. In the first embodiment, the description will be continued assuming that all the data in the transport packet is recorded.

FIG. 14 is a diagram showing the number of sync blocks that can be reproduced from one track at each high reproduction speed in the first embodiment. Note that each value in the figure is a sync block that can be reproduced from one track at each reproduction speed when special reproduction is performed using a rotary head having a 10 μm (the track pitch in the SD standard is 10 μm). It shows the number. Note that the calculation is for one track (180
The number of sync blocks (corresponding to degrees) is set to 186 sync blocks, and it is calculated assuming that a portion in which the output level of the reproduction signal is higher than −6 dB can be obtained as in the conventional example.

In the first embodiment, in any of the three different recording modes described above, data can be efficiently reproduced at the time of high speed reproduction, and additional information such as time information and music number information is reproduced. It provides a recording format that can be used.

FIG. 15 is a diagram showing a track format of a 4-track cycle including the arrangement of the special reproduction data recording area of the first embodiment. As shown in the figure, in the first embodiment, the bit stream (hereinafter referred to as normal reproduction data) recording area and the special reproduction data recording area on each track are repeated every four tracks. Hereinafter, these four tracks will be referred to as a track format. In the following description, the track recorded by the rotary head 26a is referred to as A track, and the track recorded by the rotary head 26b is referred to as B track.

In FIG. 15, T1 is the first track recorded by the rotary head 26a of the A channel, T1.
2 is the second track recorded by the B-channel rotary head 26b, and T3 is the A-channel rotary head 2
6a indicates the third track recorded, and T4 indicates the fourth track recorded by the B-channel rotary head 26b. In the first embodiment, as described above, data is recorded on the magnetic tape by using the four tracks from the first track to the fourth track as one unit (hereinafter referred to as one track format). F marked on the lower side of the truck in the figure
0, f1, and f2 indicate the types of pilot signals recorded on each track as reference signals for performing tracking control during reproduction. It should be noted that normal reproduction data and special reproduction data are recorded in the video area of 135 sync blocks excluding the C2 check code recording area and the VAUX data recording area in the video area.

In FIG. 15, A0 to A4 indicate the arrangement of the 18 × speed reproduction data recording area in the standard recording mode on the magnetic tape. Each 18 × speed reproduction data recording area (A0 to A4) has a width of 5 sync blocks. As shown in the figure, the 18x speed reproduction data recording area is provided with five areas on each A track (T1 and T3). In the figure, the same reference numerals (A0-
The same data is recorded in the area marked A4).

Similarly, in FIG. 15, B0 shows the arrangement of the quadruple speed reproduction data recording area in the standard recording mode on the magnetic tape. 4x speed data recording area B0
Has a width of 25 sync blocks. Also, 4
As shown in the figure, the double-speed reproduction data recording area is provided at one place on the T2 track.

The number of sync blocks assigned to each data recording area was determined based on the data shown in FIG. That is, as shown in FIG. 14, 62 sync blocks can be obtained from one track in quadruple speed reproduction in the standard recording mode. Also, at the 18 × speed reproduction, 10.94 sync blocks can be acquired from one track. FIG. 15 shows the data arrangement on the magnetic tape corresponding to each special reproduction speed in the standard recording mode constructed based on this. Further, in the 1/2 × recording mode, 4 × speed is set on the low speed side and 9 × speed is set on the high speed side.
In the / 4 × recording mode, 8 × speed is set on the low speed side and 18 × speed is set on the high speed side. This is an example of the double speed number set as the high speed playback speed required in each mode, and in the three recording modes, the high speed playback area is set as the double speed number that can be used as a common area. Is. At this time, in the 1/2 speed recording mode, 124 sync blocks can be acquired from one track during 4 × speed reproduction, and 46.5 sync blocks can be acquired from one track during 9 × speed reproduction.
Further, in the 1/4 recording mode, 106.29 sync blocks can be obtained from one track when reproducing at 8x speed, and 43.76 from one track when reproducing at 18x speed.
Sync block can be obtained.

Further, in FIG. 15, D0 to D3 are C4.
The arrangement of the code recording area (hereinafter referred to as ECC3) on the magnetic tape is shown. ECC3 area D0 to D3 is 1
It is configured with a width of 0 sync block. Also, ECC
As shown in the figure, the three areas are provided at one location on each of the tracks T1 to T4. Details of the ECC3 area will be described later.

In each recording mode, data is recorded on the magnetic tape by repeatedly recording the one-track format shown in FIG.

An embodiment of the data recording method of the digital VTR when recording a multi-rate signal will be described below with reference to FIGS. 6 to 8. In FIG. 6A, the rotary heads 26a and 26b are arranged adjacent to each other on the rotary drum 25, and the magnetic tape is wound around the rotary drum 25 by approximately 180 degrees. In the first embodiment, the rotary drum 25 is driven at 9000 rpm (constant) in each recording mode.

First, the standard recording mode will be briefly described with reference to FIG. In the standard recording mode, the magnetic tape is driven at the standard magnetic tape feeding speed defined in the SD standard, and as shown in the figure, the recording signals of two channels are generated by the rotating heads 26a and 26b every one rotation of the rotating drum 25. The data is recorded on the magnetic tape almost at the same time (see FIG. 6B). FIG. 16 shows a recording track pattern on the magnetic tape in the standard recording mode. 16 repeatedly records the one-track format shown in FIG. In the standard recording mode, 4 using the information of the B0 area in FIG.
Double speed high speed reproduction is performed, and 18 times high speed reproduction is performed using the information in the areas A0 to A4. At that time, as shown in FIG. 16, the same special reproduction data is duplicated for the B0 area.
The track format is repeatedly recorded, and the 9-track format is repeatedly recorded for the areas A0 to A4. Therefore, regarding the data of the B0 area, FIG.
As shown in, the same data is repeatedly recorded twice with 8 tracks as a cycle, and the same data is repeatedly recorded 18 times with 36 tracks as a cycle in the areas A0 to A4. The track pitch in the figure is 10 μm.

Similarly, the case of the 1/2 recording mode will be briefly described. The rotary drum 25 is driven at 9000 rpm as in the standard recording mode as described above. On the other hand, the feeding speed of the magnetic tape is 1/2 times that in the standard recording mode. Therefore, when data is recorded every one rotation of the rotary drum 25 as in the standard recording mode, the feed speed of the magnetic tape is halved, so that the data previously recorded by the rotary head 26b is changed to the rotary head 26a.
Will overwrite it. This is because data is recorded at a track pitch of 10 μm in each recording mode as described above. Therefore, in the case of the 1/2 times recording mode, FIG.
As shown in FIG. 6B, control is performed so that the recording signals of the two channels are recorded on the magnetic tape by the rotary heads 26a and 26b every two revolutions so that the data for one track is recorded on the magnetic tape substantially at the same time (FIG. 6). (See (b)). FIG. 17 shows the recording track pattern on the magnetic tape in the 1/2 recording mode. 17 repeatedly records the one-track format of FIG. In the 1/2 recording mode, the information in the area B0 in FIG.
Double-speed high-speed reproduction is performed, and 9-fold high-speed reproduction is performed using information in the areas A0 to A4. At that time, as shown in FIG. 17, the same trick play data is recorded in one track format in the B0 area, and 4.5 track format is repeatedly recorded in the areas A0 to A4. Therefore, for the data in the B0 area, as shown in FIG. 17, the same data is recorded only once with 4 tracks as a cycle, and with respect to the A0 to A4 areas, the same data is repeatedly recorded 9 times with 18 tracks as a cycle. The track pitch in the figure is 10 μm.

Next, the case of the 1/4 times recording mode will be described. The rotary drum 25 is driven at 9000 rpm as in the standard recording mode as described above. On the other hand, the feeding speed of the magnetic tape is 1/4 of the standard recording mode.
Double. Therefore, when data is recorded every one rotation of the rotary drum 25 as in the standard recording mode, the previously recorded data is recorded in the rotary heads 26a and 26b because the feeding speed of the magnetic tape is 1/4 times. Will overwrite it. Therefore, in the case of the 1/4 times recording mode, FIG.
As shown in FIG. 6C, the recording signals of two channels are controlled by the rotary heads 26a and 26b so that the data for one track is recorded on the magnetic tape at almost the same time every four rotations (FIG. 6). (See (b)). The recording track pattern on the magnetic tape in the 1/4 times recording mode is the same as that in the 1/2 times recording mode.
This is shown in FIG. Figure 1 in 1/4 recording mode
The information of the B0 area of No. 5 is used for high speed reproduction at 8 times speed, and the information of the A0 to A4 areas is used for high speed reproduction at 18 times speed. At that time, as in the case of the 1/2 recording mode, as shown in FIG.
As shown in FIG. 7, the same trick play data is recorded in the 1-track format for the B0 area, and the 4.5-track format is repeatedly recorded for the A0 to A4 areas. Therefore, regarding the data in the B0 area,
As shown in 7, the same data is 1 with 4 tracks as a cycle.
Only once, the same data is repeatedly recorded 9 times in the A0 to A4 areas with a period of 18 tracks.

Next, FIG. 16 shows a rotary head scanning locus when high speed reproduction is performed in the recording format in the standard recording mode of the first embodiment. FIG. 18 shows a rotary head scanning locus when quadruple speed reproduction is performed in the recording format of FIG. 16 in the standard recording mode. Further, FIG. 19 shows a rotary head scanning locus when 18 × speed reproduction is performed in the recording format of FIG. 16 in the standard recording mode.

Further, FIG. 17 shows a rotary head scanning locus when high speed reproduction is performed in the recording format of the 1/2 time recording mode and the 1/4 time recording mode of the first embodiment shown in FIG. FIG. 20 shows a rotary head scanning locus when quadruple speed reproduction is performed with the recording format of FIG. 17 in the 1/2 recording mode. In addition, FIG. 21 shows the case of FIG.
7 shows a rotary head scanning locus when 9 × speed reproduction is performed in the recording format of No. 7. Further, FIG. 22 shows a rotary head scanning locus when the 8 × speed reproduction is performed in the recording format of FIG. 17 in the ¼ recording mode. Also, in FIG.
17 shows a rotary head scanning locus when 18 × speed reproduction is performed in the recording format of FIG. 17 in the double recording mode.

Here, the details will be described with reference to the reproducing system.
According to the recording track pattern shown in FIG. 6, the rotary head scans the ITI area and the VAUX1 area of the sync block address 19 during the 4 × speed reproduction in the standard recording mode. That is, the tracking can be controlled using the pilot signals f0, f1, and f2 in the ITI area during special reproduction, and the VAUX1 area is SD.
Since it is reserved as an area for recording additional information according to the standard, additional information such as time information and music number information can be recorded here and reproduced at high speed reproduction.
Further, during 18 × speed reproduction, the rotary head scans the ITI area and the sub code area. That is, the tracking can be controlled using the pilot signals f0, f1, and f2 in the ITI area during special reproduction, and
During double speed reproduction, additional information such as time information and music number information recorded in the sub code area can be reproduced.

Further, according to the recording track pattern shown in FIG. 17, as shown in FIGS. 20 and 21, 1 /
In the 2 × recording mode, the sub code area is scanned during the 4 × speed reproduction. In addition, the rotary head scans the sub-code area even at 9 × speed reproduction. That is, it is possible to reproduce the additional information such as the time information and the music number information recorded in the sub-code area during both the 4 × speed reproduction and the 9 × speed reproduction. During 9 × speed reproduction, control is performed only by speed control.

Further, according to the recording track pattern shown in FIG. 17, as shown in FIGS. 22 and 23, 1 /
In the 4 × recording mode, the sub code area is scanned during the 8 × speed reproduction. In addition, the rotary head scans the sub-code area also at the 18 × speed reproduction. That is, it is possible to reproduce the additional information such as the time information and the music number information recorded in the sub-code area during both the 8 × speed reproduction and the 18 × speed reproduction. It should be noted that during 18 × speed reproduction, control is performed only by speed control.

Next, the operation of the recording system will be described with reference to FIGS. The transport packet input from the input terminal 1 is input to the header analysis circuit 10, the first memory 13, and the rate determination circuit 18. The header analysis circuit 10 first detects a transport header from the input transport packet. Then, the detected transport header is analyzed, and from the transport stream, the Program Asso
Citation Table (PAT) and Pro
The PID of the program to be separated from the gram map table (PMT) and recorded in the digital VTR is detected. The detected PID information is output to the first memory 13 and the rate determination circuit 18.

Further, the header analysis circuit 10 separates the transport packet for transmitting the video data of the program to be recorded based on the detected PID. Then, the data in the separated transport packet is analyzed to separate the header information such as the sequence header, the picture header, and the slice header, and the intra image data is separated from the transport packet based on the header information. At this time, the various header information added to the intra image data and the additional information added to the header information are also separated.

The sequence header is header information provided in the bit stream of the video signal and is MP
Identification information of EG1 and MPEG2, image aspect ratio,
Image transmission rate information and the like are added. The picture header is a header added to the beginning of each frame or field to indicate the beginning of each frame or field, and a mode signal such as an encoding mode and a quantization table are added.
Also, in MPEG2, when transmitting one frame of data, the screen of one frame (field) is divided into a plurality of slices and transmitted. The slice header points to the beginning (for details of each header, refer to the MPEG2 draft).

The header information detected by the header analysis circuit 10 and the additional information (for example, quantization table information) accompanying the header information are generated by the P / S conversion circuit 11, the first memory 13, and the 4-times speed reproduction data generation. It is output to the circuit 14, the 18 × speed reproduction data generation circuit 15, and the rate determination circuit 18. The intra image data separated by the header analysis circuit 10 is output to the P / S conversion circuit 11.

In the rate discriminating circuit 18, based on the PID information of the program to be recorded, which is input from the header analysis circuit 10, the transport packet of the program to be recorded is transmitted from the transport packet input via the input terminal 1. To separate. Then, by analyzing the header information added to the video data, the audio data, and the digital data relating to the video data and the audio data from the separated transport packets, the transmission rate of each data is detected, and the recorded data of the program is recorded. The rate is output to the recording data control circuit 19. The transmission rate of only the video data may be detected at the same time when the header analysis circuit 10 analyzes the header of the video data.

The recording data rate of the program detected by the rate discriminating circuit 18 is input to the recording data control circuit 19. The operation of the recording data control circuit 19 will be described with reference to FIG. The recording data rate input via the input terminal 50 is input to the recording mode setting circuit 55, and the optimum recording mode for recording the program is selected from the four types of recording modes and output. For example, the recording data rate of the program is 5.
If it was 5 Mbps, the 1/4 times recording mode (6.2
5 Mbps recording mode) is selected, and if it is 9.0 Mbps, 1/2 times recording mode (12.5 Mbps recording mode) is selected.

The output of the recording mode setting circuit 55 is input to the recording timing generation circuit 56, the special reproduction data code amount setting circuit 57, and the servo system reference signal generation circuit 58. In the servo system reference signal generation circuit 58, a reference signal, tape feed speed information, track identification signal (track number, frequency information of pilot signal of 4 track period, etc.) necessary for controlling the rotation phase of the rotary drum 25.
And so on. In the first embodiment, the rotary drum 25
The number of rotations is set to 9000 rpm in each recording mode. On the other hand, in the special reproduction data code amount setting circuit 57, when the recording mode signal is input, the B0 area and A0 to A4 are input.
The code amount control information of the special reproduction data to be recorded in the area (see FIG. 15) is output to the special reproduction data generation circuit 12, the second memory 16, and the third memory 17.

In the recording timing generation circuit 56, the selection result of the recording mode and the servo system reference signal generation circuit 5 are recorded.
Various control signals are generated based on a reference signal for controlling the rotation phase of the rotary drum 25 output from the control unit 8. The details will be described later.

On the other hand, the intra image data detected by the header analysis circuit 10 (hereinafter referred to as intra frame)
(Note that in the following description, a case where encoded data is recorded in units of one frame will be described) is P /
P / S conversion is performed by the S conversion circuit 11 and converted into 1-bit bit stream data. The intraframe bitstream data converted into 1-bit serial data is input to the trick play data generation circuit 12.

Data reproduction circuit 1 for special reproduction using FIG.
The operation of No. 2 will be described. In image compression by MPEG2, a block of 8 lines × 8 pixels (hereinafter, referred to as DCT block) is subjected to discrete cosine transform (hereinafter, referred to as DCT), and data subjected to DCT (hereinafter, referred to as DCT coefficient) is quantized. After performing the conversion, the DCT coefficient is sequentially read from the low-frequency component in which the power spectrum is concentrated in a scanning order called zigzag scanning, and run-length encoding (separating into run-length data and coefficient data) with a coefficient of 0 is performed. .. Then, the run-length encoded data is subjected to two-dimensional variable length encoding to reduce the transmission rate.

The serial data of the intra image input via the input terminal 35 is input to the variable length decoder 4, the data extracting circuit 6a and the data extracting circuit 6b. The variable length decoder 4 performs variable length decoding on the input bit stream. In the first embodiment, the input bit stream is not completely decoded at the time of variable length decoding, but
The circuit size is reduced by detecting and outputting only the run length length of the variable length codeword and the code length of the variable length codeword, but it goes without saying that the variable length decoding may be performed completely. The counter 5 counts the number of DCT coefficients in one DCT block decoded on the basis of the run length length, and outputs the count result to the data extracting circuit 6a and the data extracting circuit 6b.

Hereinafter, in the standard recording mode, the 1/2 recording mode, and the 1/4 recording mode (see FIGS. 15 and 1).
6 and FIG. 17), the operation will be described. First, the operation in the standard recording mode will be described. In the standard recording mode, the data sampling circuit 6a
4 × speed reproduction data output from the special reproduction data code amount setting circuit 57 via the input terminal 36 (in the first embodiment, a signal to be recorded in the B0 area will be referred to as 4
It is called double speed playback data. The signal recorded in the A0 to A4 areas is hereinafter referred to as 18x speed reproduction data for convenience.)
Based on the code amount control information (number of DCT coefficients to be transmitted) and the count result output from the counter 5, the variable length code word of the quadruple speed reproduction data to be transmitted is extracted. The timing for extracting data is until the number of decoded DCT coefficients output from the counter 5 is compared with the code amount control information input through the input terminal 36 and before the code amount control information is exceeded. Control is performed so as to transmit the variable length codeword. The break of the variable length code word is detected by the code length information output from the variable length decoder 4.

Similarly, the data sampling circuit 6b also controls the code amount of the 18 × speed reproduction data, the counter 5,
And 18 based on the information output from the variable length decoder 4.
The variable length codeword of the double speed reproduction data is extracted. The EOB code is added to the end of each DCT block by the EOB adding circuit 7a and the EOB adding circuit 7b, and the extracted data is output from the output terminal 37a and the output terminal 37b, respectively. The head of each DCT block is detected by the variable length decoder 4 and output to the counter 5 and the data sampling circuits 6a and 6b.

At this time, the number of DCT coefficients for extracting data may be the same or different in each recording mode or each double speed number. The fact that the number of extracted DCT coefficients is different means that the number of DCT blocks recorded in the recorded special reproduction transport packet is different. The area in which special reproduction data can be recorded is limited as described above. Therefore, if the number of special reproduction data recording areas for each special reproduction speed is the same number of sync blocks, the number of special reproduction data recording areas to record increases when the number of recorded DCT coefficients in one DCT block is increased. The update cycle (hereinafter referred to as refresh) of the high-speed reproduced image data during reproduction becomes long. The reproduction image quality is improved because more DCT coefficients are transmitted. On the contrary, DC in 1DCT block
When the number of T coefficients recorded is reduced, the data amount of the special reproduction data per frame is reduced, and the special reproduction data recording area is small, so that the refresh of the high-speed reproduction image is shortened. The reproduced image quality is poor because the number of recorded DCT coefficients is small. The amount of data to be extracted in each recording mode or each double speed may be determined by the trade-off between refresh and image quality.

The 4 × speed reproduction data and the 18 × speed reproduction data output from the special reproduction data generation circuit 12 are input to the 4 × speed reproduction data generation circuit 14 and the 18 × speed reproduction data generation circuit 15, respectively. It Since the subsequent processing is the same at each reproduction speed (4 × speed and 18 × speed), a method of generating 4 × speed reproduction data will be described here. Hereinafter, the operation of the quadruple speed reproduction data generation circuit 14 will be described with reference to FIG. In the 4 × speed reproduction data generation circuit 14, the transport header information and various header information (including additional information) input from the header analysis circuit 10 and the 4 × speed reproduction data output from the special reproduction data generation circuit 12 are output. A transport packet for quad speed reproduction is generated using the data. The transport header information input via the input terminal 40 is modified by the transport header modification circuit 42.

Specifically, based on the intra information output from the header analysis circuit 10, the header information indicating the continuity of the transport packet in the transport header of the transport packet transmitting the intra image is rewritten. On the other hand, in the header addition circuit 43, in the trick play bit stream output from the trick play data generation circuit 12, header information such as a sequence header, a picture header, and a slice header detected by the header analysis circuit 10, and each header. Information (encoding mode flag,
Alternatively, quantization table information or the like) is added.

The special reproduction data to which the header information is added is subjected to serial / parallel conversion in the packetizing circuit 44 and 1 byte is converted into 8-bit data. The serial / parallel converted 8-bit data is 184
The data part of the transport packet is composed by dividing it into bytes. It should be noted that when serial / parallel conversion, each header information is set to 4 as specified in MPEG2.
"0" data is inserted before each header information so as to be composed of bytes. This is because each header information is composed of 32 bits and needs to be composed of 4 bytes when a transport packet is generated.

More specifically, when the header information extends over 5 bytes, "0" information is added before the header information to control the header information to be configured by 4 bytes. 184 composed of the packetizing circuit 44
The data of the transport packet of bytes is added with the transport header information output from the transport header correction circuit 42 in the transport header addition circuit 45 and output. The reading of the header information from the transport header correction circuit 42 is output based on the timing signal output from the packetization circuit 44. The 4 × speed reproduction data generated by the 4 × speed reproduction data generation circuit 14 is output to the second memory 16 in the form of transport packets.

In the above description, the transport packetization of the 4 × speed reproduction data has been described, but the 18 × speed reproduction data is also subjected to the same processing. The 18 × speed reproduction data output from the special reproduction data generation circuit 12 is 18
The data is input to the double speed reproduction data generation circuit 15. In the 18 times data generation circuit 15, the header addition circuit 43 adds each header and additional information based on the header information output from the header analysis circuit 10 and then the packetization circuit 44 serial / parallel in the manner described above. The data part of the transport packet is formed by the conversion, the modified transport header output from the transport header modification circuit 42 is added by the transport header addition circuit 45, and the third memory in the form of the transport packet is added. It is output to 17.

The respective special reproduction transport packet data output from the 4 × speed reproduction data generation circuit 14 and the 18 × data generation circuit 15 are input to the second memory 16 and the third memory 17. It that time,
In the second memory 16 and the third memory 17, the storage area of the special reproduction data for one frame is set based on the code amount information output from the recording data control circuit 19. In the second memory 16 and the third memory 17, the input data is stored in the storage area in the memory in the form of transport packets to form one frame (field) of special reproduction data.

Second memory 16 and third memory 1
The special reproduction data of one frame composed of 7 is the first
An error correction check code for special reproduction (hereinafter referred to as a C5 check code) is added in the error correction code circuit 31.
The data to which the C5 check code is added in the first error correction code circuit 31 is read from the memory for each of the two special reproduction transport packets based on the data request signal output from the data synthesis circuit 20. FIG.
As shown in (b), it is converted into data of 5 sync blocks and output to the data synthesizing circuit 20. At that time, FIG.
The H1 and H2 header information shown in (b) is added.

On the other hand, the transport packet input through the input terminal 1 is input and stored in the first memory 13. The first memory 13 reads out the input data based on the control signal (data request signal) output from the data synthesizing circuit 20. At this time, the data input in transport packet units is converted into data of 5 sync blocks as shown in FIG. 13B in units of 2 transport packets, and is output. Note that, as in the case of special reproduction data, when the data of the sync block is output from the first memory 13, the H1 and H
2 header information is added.

The recording data control circuit 19 generates a recording format based on the control signal output from the recording timing generation circuit 56. The recording format generation operation will be described below. The recording timing generation circuit 56
Based on the recording mode output from the recording mode setting circuit 55, a track identification signal in one track format of special reproduction data, a track number, and a repeat count control signal for recording the same data for each recording mode are provided to the data synthesizing circuit. Output to 20. Data is generated in the data synthesizing circuit 20 and the third error correction coding circuit 32 based on the reference signal output from the servo system reference signal generating circuit 58 for controlling the rotation phase of the rotary drum 25 and the recording mode. Output the start signal.

FIG. 9 shows control signals output from the recording timing generation circuit 56 in each recording mode. The control signals output from the recording timing generation circuit 56 for each recording mode will be described below. FIG. 9A shows a reference signal for controlling the rotation phase of the rotary drum 25, which is output from the servo system reference signal generation circuit 58. Figure 9
(B) shows a data generation start signal in the standard recording mode. FIG. 9C shows the recording amplifier 24 in the standard recording mode.
It is a data recording timing signal output to a and 24b. Actually, the recording timing signal output to the recording amplifier 24b is delayed from the recording timing signal output to the recording amplifier 24a by the distance between the rotary heads (usually about 5 sync blocks). FIG. 9D shows the recording timing of the data of each channel in the standard recording mode. As shown in the figure, in the standard recording mode, each control signal is output for each rotation of the rotary drum 25, and data is recorded on the magnetic tape.

FIG. 9E shows a data generation start signal in the 1/2 recording mode. FIG. 9F shows a data recording timing signal output to the recording amplifiers 24a and 24b in the 1/2 recording mode. FIG. 9G shows the recording timing of the data of each channel in the 1/2 recording mode. As shown in the figure, in the 1/2 recording mode, each control signal is output every two rotations of the rotary drum 25, and data is recorded on the magnetic tape.

FIG. 9H shows a data generation start signal in the 1/4 times recording mode. FIG. 9I shows a data recording timing signal output to the recording amplifiers 24a and 24b in the 1/4 times recording mode. FIG. 9J shows the recording timing of the data of each channel in the 1/4 times recording mode. As shown in the figure, in the 1/4 recording mode, each control signal is output every four rotations of the rotary drum 25, and data is recorded on the magnetic tape. Actually, as described above, the recording timing signal output to the recording amplifier 24b is delayed from the recording timing signal output to the recording amplifier 24a by the distance between the rotary heads (usually about 5 sync blocks).

The data synthesizing circuit 20 generates a recording format based on the control signal. First, when the data generation start signal is input, the format generation circuit control circuit 1
The track number of the track to be recorded next at 27,
And the type and area of special reproduction data to be recorded in the track of each channel generated based on the identification of the track in the 1-track format. The format generation circuit 126 outputs the data for 4 × speed reproduction and the data for 18 × speed reproduction on a predetermined track based on the sync block information signal input from the recording data control circuit 19 to the format generation circuit control circuit 127. The recording format is generated so as to be arranged in the area of. At this time, the number of times the special reproduction data at each speed is repeated is confirmed. If the data has been repeated a predetermined number of times, the next special reproduction data is read from the memory in which the corresponding special reproduction data is stored, and the data request signal is output.

Specifically, when the 18 × speed reproduction data is repeatedly recorded 18 times in the standard recording mode, the data is output to the third memory 17 so that the next special reproduction data for 25 sync blocks is output. Output the request signal. The 18 × speed reproduction data of the 25 sync blocks read from the third memory 17 is temporarily stored in the 18 × speed reproduction data storage memory provided in the data synthesis circuit 20. Similarly, when the 4 × speed reproduction data is repeatedly recorded twice in the standard recording mode, the data request signal is output to the second memory 16 so as to output the next special reproduction data for 25 sync blocks. The 4 × speed reproduction data of the 25 sync blocks read from the second memory 16 is temporarily stored in the 4 × speed reproduction data storage memory provided in the data synthesis circuit 20. If the number of repetitions is less than or equal to the predetermined number, the recording data is generated using the special reproduction data for each speed stored in the data synthesizing circuit 20.

Similarly, when the 18 × speed reproduction data is repeatedly recorded 9 times in the 1/2 recording mode, the third recording data is recorded.
The data request signal is output to the memory 17 to output the next special reproduction data for 25 sync blocks. Third
The 18x speed reproduction data of the 25 sync blocks read out from the memory 17 is temporarily stored in the 18x speed reproduction data storage memory provided in the data synthesizing circuit 20. Similarly, when the data for quadruple speed reproduction is recorded once in the ½ × recording mode, the second memory 16
Then, the data request signal is output so as to output the next special reproduction data for 25 sync blocks. Second memory 16
The 4 × speed reproduction data of the 25 sync blocks read out by the above is stored in the data synthesizing circuit 20.
It is temporarily stored in the data storage memory for double speed reproduction. If the number of repetitions is less than or equal to the predetermined number, the recording data is generated using the special reproduction data for each speed stored in the data synthesizing circuit 20.

Similarly, when the 18 × speed reproduction data is repeatedly recorded 9 times in the ¼ recording mode, the third recording data is recorded.
The data request signal is output to the memory 17 to output the next special reproduction data for 25 sync blocks. Third
The 18x speed reproduction data of the 25 sync blocks read out from the memory 17 is temporarily stored in the 18x speed reproduction data storage memory provided in the data synthesizing circuit 20. Similarly, in the 1/4 recording mode, if the 4 × speed reproduction data is recorded once, the second memory 1
A data request signal is output to 6 so as to output the next special reproduction data for 25 sync blocks. Second memory 1
The 4 × speed reproduction data of the 25 sync blocks read out from 6 is temporarily stored in the 4 × speed reproduction data storage memory provided in the data synthesizing circuit 20. If the number of repetitions is less than or equal to the predetermined number, the recording data is generated using the special reproduction data for each speed stored in the data synthesizing circuit 20.

When the confirmation of the number of repetitions of the special reproduction data is completed, the data arrangement within one track is set by using the track identification signal. The track identification signal is shown in Fig. 1.
5 is an identification signal for identifying the tracks T1 to T4 shown in FIG. In the first embodiment, since data for two tracks is recorded almost at the same time, the track identification signal outputs a signal for identifying the T1 track or the T3 track. First, the data arrangement in the track to be recorded by the rotary head 26a is set. When the data arrangement in one track is set, the special reproduction data for each speed provided in the first memory 13 and the data synthesizing circuit 20 in units of one sync block is read out, and one track is read. Minute recording data is generated and output to the fourth memory 21. When the recording data for one track to be recorded by the rotary head 26a is completed, the track to be recorded by the rotary head 26b is generated by the same procedure.

The recording data for two tracks generated by the data synthesizing circuit 20 is temporarily recorded in the fourth memory 21. The recording data of each channel stored in the fourth memory 21 is subjected to the error correction coding for normal reproduction in which the C4 check code is added with the interleave of 10 tracks in depth in the second error correction coding circuit 22. . The data of the fourth memory 21 to which the C4 check code is generated and added by the second error correction code circuit 22 is added and the error correction check code based on the SD standard is generated and added by the third error correction code circuit 32. (See Figure 10). The third error correction code circuit 32 adds 2 to which the error correction check code is added based on the data generation start signal output from the recording timing generation circuit 56.
A read control signal is output to the fourth memory 21 so as to read the data for the tracks substantially at the same time. In the fourth memory 21, the recording data for one track of each channel is read based on the read control signal, and at this time, S
A track format based on the D standard is generated. Specifically, a sync signal and an ID are provided between each sync block.
An interval of 5 bytes is provided for adding a signal, and a predetermined amount of gaps between the ITI area, subcode area, and each data are opened, and the above data is output. The output of the fourth memory 21 is input to the digital modulation circuits 23a and 23b.

Digital modulation circuits 23a and 23b
First adds a sync signal and an ID signal to the head of each sync block. In the first embodiment, the identification signal of the recording mode is recorded as the ID signal. The data to which the ID signal is added is digitally modulated and output to the recording amplifiers 24a and 24b. At the time of digital modulation, digital modulation is performed based on the track identification information output from the recording timing generation circuit 56. The digitally modulated data input to the recording amplifiers 24a and 24b is amplified, and the rotary head 26a,
And 26b on the magnetic tape.

Next, the operation of the servo system will be described. Rotating drum 25 output from servo system reference signal generating circuit 58
The reference signal for controlling the drum motor is input to the drum motor control circuit 27. The drum motor control circuit 27, based on the reference signal and the rotational phase information of the rotary heads 26a and 26b output from the drum motor 28, 900
The drum motor 28 is controlled to 0 rpm. The drum motor 28 is driven by the drive voltage of the drum motor output from the drum motor control circuit 27. The drum motor 28 outputs the rotation phase of the rotary drum 25 to the drum motor control circuit 27.

Similarly, the capstan motor control circuit 29
Controls the capstan motor on the basis of a reference signal for controlling the rotary drum 25, a recording mode, and rotation information of the capstan motor (traveling speed information of the magnetic tape) output from the capstan motor 30. As shown in FIG. 7, the running speed of the magnetic tape in each recording mode is 1/2 in the 1/2 recording mode and 1 in the 1/4 recording mode, where 1 is the standard recording mode. / 4
Controlled by double. The capstan motor control circuit 29
A drive voltage for driving the capstan motor 30 is output using the reference signal of the rotary drum 25 and the rotation information of the capstan motor so that the tape traveling speed is set according to the recording mode. The capstan motor 30
Outputs the rotation information of the capstan motor to the capstan motor control circuit 29.

Next, the structure of the reproducing system of the digital VTR for reproducing the magnetic tape having the above recording format will be described. FIG. 24 is a block circuit diagram of the reproducing system of the digital VTR of the first embodiment. Note that the same reference numerals as those in FIG. 1 have the same configurations and operations, and thus description thereof will be omitted. In the figure, 60a and 60b are reproduction amplifiers, 61a and 61b are digital demodulation circuits, and 62a.
Is a fifth memory, and 63 is a first error correction decoding circuit for correcting and detecting an error in the reproduced signal by using the C1 check code and the C2 check code for the reproduced digital signal.

Reference numeral 73 represents the recording data contents of the ECC3 area set by the external input command information at the time of recording,
It is an input terminal for inputting an ECC3 mode signal. 64 is a sixth memory for storing a reproduced digital signal for normal reproduction, and 71 is a normal reproduction of the sixth memory 64 when error correction coding for normal reproduction is performed based on the ECC3 mode information signal. A second error correction decoding circuit for correcting and detecting an error in the special data, 65 is a seventh memory for storing special reproduction data, and 72 is an error correction code for special reproduction based on the ECC3 mode information signal. A third error correction decoding circuit that corrects and detects an error in the special reproduction data of the seventh memory 65 when conversion is performed, and 66 is a sixth memory 64 and a seventh memory 65.
Is a switch for switching the output of the signal based on a selection signal output from a reproduction system control circuit 68 described later, 67 is a recording mode detection circuit for detecting the recording mode of the data at the time of recording from the digital demodulated reproduction digital signal, and 68 is an input terminal A reproduction system that generates a reference signal for controlling the drum motor 28 and the capstan motor 30 based on the mode signal input via the control signal 69 and the recording mode detection result, and outputs a switching signal of the switch 66. A control circuit, 69 is an input terminal for the mode signal, and 70 is an output terminal.

Before explaining the operation of the reproducing system, FIG.
8, FIG. 20 and FIG. 22 will be used to describe the operation when high-speed reproduction is performed at the speed set for each recording mode using the 4 × speed reproduction data in the digital VTR shown in the first embodiment. In the high speed reproduction using the 4 × speed reproduction data, the traveling speed control of the magnetic tape and the phase control of the rotary heads 26a and 26b are performed.

FIG. 18 shows the rotary head 2 when quadruple speed reproduction is performed using a magnetic tape recorded in the standard recording mode.
6B is a diagram showing a scanning trace, and in the standard recording mode as shown in the figure, the 4 × speed reproduction data is recorded in the track of the B channel as described above, and as described above, the 2 track format period, Since the same data is repeatedly recorded (the same data is recorded in two recording areas), the rotary head 2 is located at the center of the B0 area.
If the phase of the rotary head is controlled so that the reproduction output of 6b is maximized, it is possible to reproduce all the quadruple speed reproduction data as shown in FIG. Further, when reproducing a magnetic tape recorded in the standard recording mode at a quadruple speed,
As shown in, the rotary head 26b can also reproduce data in the VAUX1 area. Also, tracking is I
You can call in the TI area.

FIG. 20 is a diagram showing the scanning locus of the rotary head 26b when the 4 × speed reproduction is performed using the magnetic tape recorded in the 1/2 × recording mode. In the case of the mode, as described above, the special reproduction data is recorded in the unit of one track format for the quadruple speed reproduction data, and the phase of the rotary head is adjusted so that the reproduction output of the rotary head 26b is maximized at the center of the B0 area. If the control is performed, it is possible to reproduce all the quadruple speed reproduction data as shown in FIG. Further, when reproducing the magnetic tape recorded in the 1/2 recording mode at 4 × speed, the data in the sub code area can be reproduced by the rotary head 26b as shown in FIG.

FIG. 22 is a diagram showing a scanning locus of the rotary head 26b in the case of performing the 8 × speed reproduction using the magnetic tape recorded in the 1/4 × recording mode.
In the double recording mode, the special reproduction data is recorded in the unit of one track format as the quadruple speed reproduction data as described above, but the rotary head 26b is located at the center of the B0 area.
If the phase control of the rotary head is performed so that the reproduction output of No. 4 is maximized, it is possible to reproduce all the quadruple speed reproduction data as shown in FIG. When reproducing a magnetic tape recorded in the 1/4 times recording mode at 8 times speed,
As shown in, the rotary head 26b can also reproduce the data in the sub code area.

Next, with reference to FIGS. 19, 21 and 23, the operation when high speed reproduction using the 18 × speed reproduction data is performed by the digital VTR shown in the first embodiment will be described. In addition, the running speed control of the magnetic tape, the rotary head 26a,
And 26b are controlled.

FIG. 19 is a diagram showing a scanning locus of the rotary head 26a when the 18-fold speed reproduction is performed using the magnetic tape recorded in the standard recording mode. As shown in FIG. 18x speed reproduction data is A
Since it is recorded on the track of the channel (A0 to A4 areas), and as described above, the same data is repeatedly recorded during the 9-track format period (the same data is recorded on 18 tracks). FIG. 19
As shown in, all the 18 × speed reproduction data can be reproduced. Further, when reproducing the magnetic tape recorded in the standard recording mode at 18 times speed, the rotary head 26a can also reproduce the data in the sub-code area as shown in FIG. Also, tracking can be applied in the ITI area.

FIG. 21 is a diagram showing the scanning locus of the rotary head 26a in the case of performing 9 × speed reproduction using a magnetic tape recorded in the 1/2 × recording mode.
In the double recording mode, the 18 × speed reproduction data is recorded in the track of the A channel as described above (A0 to 0).
(A4 area), and as described above, the same data is repeatedly recorded (the same data is recorded on 9 tracks) during the 4.5-track format period.
As shown in FIG. 21, all 18 × speed reproduction data can be reproduced. Further, when reproducing the magnetic tape recorded in the 1/2 recording mode at 9 times speed, the data in the sub code area can also be reproduced by the rotary head 26a as shown in FIG.

FIG. 23 is a diagram showing a scanning locus of the rotary head 26a when 18 times speed reproduction is performed using a magnetic tape recorded in the 1/4 times recording mode.
In the 4 × recording mode, the 18 × speed reproduction data is recorded in the A channel track as described above (A0
(A4 area), and since the same data is repeatedly recorded (the same data is recorded on 9 tracks) during the 4.5-track format period as described above, 18 times speed is set as shown in FIG. All the data for reproduction can be reproduced. When reproducing the magnetic tape recorded in the 1/4 times recording mode at 18 times speed,
As shown in, the rotary head 26a can also reproduce data in the sub code area.

In the standard recording mode, tracking during high speed reproduction can be performed in the ITI area.
For example, in the case of 18 × speed reproduction, the tracking phase may be detected and controlled in one data area of the special reproduction data recording area, or the tracking phase may be detected in a plurality of special reproduction data recording areas. For quadruple speed reproduction, the tracking phase may be detected and controlled by the rotary head 26a at a predetermined position of the adjacent A track. Further, the tracking phase may be roughly adjusted in the ITI area and finely adjusted in the special reproduction area. In particular, the tracking control method described above is effective when there is a bend in the track due to compatible reproduction or the like.

Next, the operation of the above reproduction system during normal reproduction will be described. The data reproduced from the magnetic tape via the rotary heads 26a and 26b on the rotary drum 25 is amplified by the reproduction amplifiers 60a and 60b and input to the digital demodulation circuits 61a and 61b. The output of the reproduction amplifier 61a is also output to the capstan motor control circuit 29. In the digital demodulation circuits 61a and 61b, data detection is carried out from the inputted reproduced data, and after converted into reproduced digital data, digital demodulation is carried out. The ID signal added to the head of each sync block is detected by the digital demodulation circuits 61a and 61b. The reproduced digital data digitally demodulated by the digital demodulation circuits 61a and 61b is input to the fifth memory 63 and the data for one track is collected to form the error correction code block shown in FIG. When the construction of the error correction code block shown in FIG. 10 is completed, the first error correction decoding circuit 63 uses the C1 check code and the C2 check code to detect and correct the error that has occurred during reproduction.

The reproduced digital data subjected to error correction in the first error correction decoding circuit 63 is read from the fifth memory 62 and output to the sixth memory 64 and the seventh memory 65. At this time, the special reproduction data (4 × speed reproduction data and 18 × speed reproduction data) reproduced from the special reproduction data recording area is input to the seventh memory 65, and the reproduction digital data for normal reproduction is stored in the 7th memory 65. 6 to the memory 64. The special reproduction data input to the seventh memory 65 is corrected by the third error correction decoding circuit 72 when the special reproduction error correction encoding is performed based on the ECC3 mode information signal. And the normal reproduction data input to the sixth memory 64 is detected based on the ECC3 mode information signal, and if the normal reproduction error correction encoding is performed, the second error correction decoding circuit Error correction and detection are performed by 71.

On the other hand, the ID signal detected by the digital demodulation circuits 61a and 61b is the recording mode detection circuit 67.
Is input to. The recording mode detection circuit 67 displays the reproduced I
The data recording mode is detected from the D signal. The reproduction system control circuit 68 determines the reproduction mode of the digital VTR based on the mode signal output from the input terminal 69. When the input mode signal is the normal reproduction mode, the reproduction system control circuit 68 outputs the reference signal of the rotation phase of the rotary drum 25 to the drum motor control circuit 27, and outputs the reference signal of the recording mode separated from the ID signal. Based on the determination result, the tape traveling speed information is output to the capstan motor control circuit 29.

The switch 66 selects the output of the sixth memory 64 during normal reproduction based on the selection information output from the reproduction system control circuit 68. The sixth memory 64 is shown in FIG.
The normal reproduction data stored in the sync block format shown in (b) has header information H when data is read.
1 and H2 are deleted and the original transport packet is restored and output to the switch 66. The normal reproduction data output from the sixth memory 64 is switched by the switch 66.
Is output from the output terminal 70 via.

Next, the operation of the servo system during normal reproduction will be described. In the reproduction system control circuit 68, the recording mode detection circuit 67
The tape running speed information of the capstan motor is output to the capstan motor control circuit 68 on the basis of the recording mode detection result output by the controller, and a signal indicating whether or not the rotational phase of the rotary drum 25 is controlled is output from the recording mode detection result. To do. Needless to say, phase control is required in each recording mode during normal reproduction. On the other hand, the reference signal of the rotation phase of the rotary drum 25 output from the reproduction system control circuit 68 is input to the drum motor control circuit 27. The drum motor control circuit 27 outputs the reference signal and the rotary head 26a output from the drum motor 28,
The drum motor is controlled to 9000 rpm based on the rotation phase information of the above and 26b. The drum motor 28 is driven by the drive voltage of the drum motor output from the drum motor control circuit 27. It should be noted that the rotation phase of the rotary drum 25 is transferred from the drum motor 28 to the drum motor control circuit 27.
Output to. During reproduction, the rotation phase information of the rotary drum 25 is output from the drum motor control circuit 27 to the capstan motor control circuit 29.

The capstan motor control circuit 29 controls the rotation phase information of the rotary drum 25, the recording mode, the tape running speed information, the reproduction signal output from the reproduction amplifier 60a, and the capstan motor output from the capstan motor 30. The capstan motor is controlled based on the rotation information of the magnetic tape (traveling speed information of the magnetic tape). As shown in FIG. 7, the running speed of the magnetic tape in each recording mode is set to 1 in the standard recording mode, 1/2 in the 1/2 recording mode, and 1/4 in the 1/4 recording mode. 1 /
It is controlled four times. During normal reproduction, the capstan motor control circuit 29 controls the traveling speed of the magnetic tape so as to reach the tape traveling speed according to the recording mode, and also the rotation phase information of the rotating drum 25 and the ITI.
The rotation phase of the rotary drum 25 is detected using the ATF information recorded in the area, and the phase control is also performed. The capstan motor 30 outputs the rotation information of the capstan motor to the capstan motor control circuit 29.

Next, the operation during high speed reproduction will be described. The data intermittently reproduced from the magnetic tape via the rotary heads 26a and 26b on the rotary drum 25 is amplified by the reproduction amplifiers 61a and 61b and input to the digital demodulation circuits 61a and 61b. Also,
The output of the reproduction amplifier 61a is also output to the capstan motor control circuit 29. The digital demodulation circuits 61a and 61b perform data detection from the input reproduction data, convert the reproduction data into reproduction digital data, and then perform digital demodulation. The ID signal added to the head of each sync block is the digital demodulation circuits 61a and 6a.
It is detected in 1b. The reproduced digital data digitally demodulated by the digital demodulation circuits 61a and 61b is input to the fifth memory 62.

When data is input, the fifth memory 62 separates the recording area for high speed reproduction data based on the ID signals output from the digital demodulation circuits 61a and 61b, and separates only the special reproduction data. Once the fifth memory 6
Store in 2. In the first embodiment, the reproduction amplifier 6 is used for high-speed reproduction using the data recorded in the B0 area.
0b and the data output from the digital demodulation circuit 61b are used to perform various controls, and in the case of high speed reproduction using the data recorded in the A0 to A4 areas, the data is output from the reproduction amplifier 60a and the digital demodulation circuit 61a. Various controls are performed using the data.

The special reproduction data stored in the fifth memory 62 is subjected to error correction by the C1 check code in the first error correction decoding circuit 63 in units of one sync block, and the error generated during high speed reproduction is detected. Corrections and detections are made. The data that has been subjected to error correction by the first error correction decoding circuit 63 is sequentially read from the fifth memory 62 and input to the seventh memory 65. The fifth memory 6
The output of 2 is also input to the sixth memory 64, but no data is written during high speed reproduction.

The seventh memory 65 is based on the track number separated from the ID information, the sync block number, and the H1 and H2 header information shown in FIG. 13 recorded in the input special reproduction data. The special reproduction data that has been reproduced is recorded in a predetermined address in the seventh memory 65. The storage area for one frame of special reproduction data in the seventh memory 65 is determined based on the recording mode signal output from the recording mode detection circuit 67. The special reproduction data stored in the sync block format shown in FIG. 13B in the seventh memory 65 is read in units of 5 sync blocks when the data is read, the header information H1 and H2 are deleted, and the transport packet Is output to the switch 66. The special reproduction data output from the seventh memory 65 is output from the output terminal 70 via the switch 66.

Next, the operation of the servo system during high speed reproduction will be described. The ID signal detected by the digital demodulation circuits 61a and 61b is input to the recording mode detection circuit 67. The recording mode detection circuit 67 detects the data recording mode from the reproduced ID signal. Reproduction system control circuit 68
Determines the reproduction mode of the digital VTR based on the mode signal output from the input terminal 69. When the input mode signal is the high speed reproduction mode, the reproduction system control circuit 68 outputs a control signal to the switch 66 so as to select the output of the seventh memory 65, and various control signals to the servo system. Is output.

The servo system control method during high-speed reproduction using the B0 area (FIGS. 15 and 16) in the standard recording mode, the 1/2 recording mode, and the 1/4 recording mode will be described below. explain. As described above, during high-speed reproduction using B0 in each recording mode, magnetic tape running control is performed in each recording mode, and rotational phase control of the rotary drum 25 is also performed. Therefore, the reproduction system control circuit 68
A reference signal of the rotation phase of the rotary drum 25 is output to the drum motor control circuit 27, and tape running speed information is output to the capstan motor control circuit 29 based on the determination result of the recording mode separated from the ID signal. .

The drum motor control circuit 27 is 9000 based on the above reference signal and the rotational phase information of the rotary heads 26a and 26b output from the drum motor 28.
Control the drum motor to rpm. Drum motor 28
Are driven by the drive voltage of the drum motor output from the drum motor control circuit 27. The drum motor 28 outputs the rotation phase of the rotary drum 25 to the drum motor control circuit 27. Also, during playback, the rotary drum 2
The rotation phase information of No. 5 is output from the drum motor control circuit 27 to the capstan motor control circuit 29.

The capstan motor control circuit 29 controls the rotation phase information of the rotary drum 25, the recording mode, the tape traveling speed information, the reproduction signal output from the reproduction amplifier 60b, and the capstan motor output from the capstan motor 30. The capstan motor is controlled based on the rotation information of the magnetic tape (traveling speed information of the magnetic tape). In addition,
The phase control in the first embodiment performs tracking control based on the rotational phase information of the rotary drum output from the drum motor control circuit 27 so that the reproduction output of the central portion of the B0 area on the magnetic tape becomes maximum. . The capstan motor control circuit 29 controls the traveling speed of the magnetic tape in accordance with the tape traveling speed information, and
The rotation phase of the rotary drum 25 is controlled as described above. In the standard recording mode, as described above, ITI
Since the area is scanned at the time of quadruple speed reproduction, the ATF information recorded in the ITI area may be used to detect the rotational phase of the rotary drum 25 and perform phase control. The rotation information of the capstan motor 30 is output from the capstan motor 30 to the capstan motor control circuit 29.

Next, the operation of the servo system at the time of high speed reproduction using the A0 to A4 areas (FIGS. 15 and 16) in the standard recording mode, the 1/2 recording mode and the 1/4 recording mode. Will be explained. As shown in FIG. 19, in the standard recording mode, the recording data is arranged so that the tracking phase error can be detected in the ITI area and the rotational phase of the rotary drum 25 can be controlled. That is, the special reproduction data is arranged on the scanning locus of the rotary head 26a in order to obtain a sufficient reproduction data rate of the special reproduction data at the time of 18 × speed reproduction.

The control system of the servo system at the time of high speed reproduction using the 18 × speed reproduction data in each recording mode will be described below. As described above, A0 in the standard recording mode
During high-speed reproduction using A4 to A4, the running control of the magnetic tape and the rotational phase control of the rotary drum 25 are performed in each recording mode. Therefore, the reproduction system control circuit 68 outputs the reference signal of the rotation phase of the rotary drum 25 to the drum motor control circuit 27, and the capstan motor control circuit 29 based on the determination result of the recording mode separated from the ID signal. The tape running speed information is output to.

The drum motor control circuit 27 determines 9000 based on the reference signal and the rotational phase information of the rotary heads 26a and 26b output from the drum motor 28.
Control the drum motor to rpm. The drum motor 28 is driven by the drive voltage of the drum motor output from the drum motor control circuit 27. The drum motor 28
Outputs the rotation phase of the rotary drum 25 to the drum motor control circuit 27. During playback, the rotary drum 25
Is output from the drum motor control circuit 27 to the capstan motor control circuit 29.

The capstan motor control circuit 29 controls the rotation phase information of the rotary drum 25, the recording mode, the tape traveling speed information, the reproduction signal output from the reproduction amplifier 60b, and the capstan motor output from the capstan motor 30. The capstan motor is controlled based on the rotation information of the magnetic tape (traveling speed information of the magnetic tape). In addition,
In the phase control in the standard recording mode in the first embodiment, the ITI area on the magnetic tape is detected based on the rotational phase information of the rotary drum output from the drum motor control circuit 27, and the tracking state in the ITI area is detected. Is sampled and the tracking phase error is detected. The capstan motor control circuit 29 controls the traveling speed of the magnetic tape in accordance with the tape raw speed information, and detects and controls the rotational phase of the rotary drum 25 in the above-described manner. The rotation information of the capstan motor 30 is output from the capstan motor 30 to the capstan motor control circuit 29.

Since the digital VTR shown in the first embodiment is configured as described above, it is possible to record signals having different recording rates in the same recording format (track format) for each recording rate, and to use a special At the time of reproduction, it is possible to reproduce the additional information recorded in the sub-code area or the VAUX1 area, such as time information and music number information.

In each recording mode, in order to obtain a sufficient reproduction data rate of the special reproduction data, the special reproduction data recording area is set in the rotary head 2 in the first embodiment.
6 was placed on the scanning locus. Therefore, according to the first embodiment, by arranging the recording area of the high-speed reproduction data on the scanning locus of the rotary head 26 during high-speed reproduction, the special reproduction data can be arranged with maximum efficiency. The reproduction data rate can be improved, and the reproduction image quality at high speed reproduction can be improved.

In the first embodiment, the tape running speed in the standard recording mode is 4 times, 18 times, and 1/2 times.
The tape running speed in the double recording mode is 4 times and 9 times, and the tape running speed in the 1/4 times recording mode is 8 times,
The special reproduction data is arranged on the scanning locus of the rotary head 26 at the time of high-speed reproduction in the respective recording modes as 18x and 18x, but the set speed is not limited to this.

Further, although the case where the recording format is shown in FIG. 15 has been described in the first embodiment, it is not limited to this format, and the special reproduction data is separated from the input data and is determined in advance on the recording medium. In a digital signal recording device, a reproducing device, and a recording / reproducing device (digital VTR, digital disc player, etc.) having a recording format for recording in different areas, the recording format of special reproduction data is set to a plurality of recording rates as described above. In addition, the rotary head 26 scans the subcode or the VAUX1 area during high-speed reproduction, so that special reproduction data during high-speed reproduction can be efficiently recorded. Area or VAUX1 area information can be reproduced It is possible to obtain an additional function of the time of high-speed playback because kill.

The recording data is not limited to the ATV signal or the DVB signal. For example, in the case of Japan which compresses a video signal based on MPEG2, the same applies when the ISDB signal or the signal compressed by MPEG1 is recorded. It goes without saying that the effect of.

When recording the data transmitted in the transport packet format represented by MPEG2 in the digital VTR represented by the SD standard, the first embodiment is adopted.
Then, two transport packets were converted to and recorded in 5 sync block formats, but the present invention is not limited to this, and when the sync block format is generated, the input m transport packets are used. Generates sync line data for n lines (m and n are positive numbers).

Further, when recording the converted sync block format data on the recording medium, by configuring the recording format on the recording medium such that the data of the n sync blocks is arranged on the same track. The effect is that the data of the transport packet can be efficiently converted into the sync block format.

Further, since the data of the n sync blocks is completed in the same track, at the time of reproduction, when converting the data of the sync block format into the data of the transport packet, the track information such as the track identification signal and the sync It is possible to easily separate the sets of the n sync block formats by using the block number, and it is particularly effective to reduce the circuit scale of the reproducing system.

Further, there is an effect that the data recording area can be effectively utilized without recording the identification signal of n sync blocks, and the length of one sync block is limited to that shown in FIG. Absent.

A data recording area for 4 × speed reproduction, 1
The arrangement of the data recording area for octuple speed reproduction, the error correction check code recording area, or the number of areas is not limited to this.

The track cycle is not limited to the 4-track cycle.

Further, in the first embodiment, the speed during high speed reproduction in the standard recording mode (standard mode) is selected as 4 times speed or 18 times speed as the high speed reproduction speed, but the present invention is not limited to this, and other speeds may be used. Even at a double speed, the same effect can be obtained if the special reproduction data recording area is arranged on the scanning loci of the rotary heads 26a and 26b as described above.

Further, it is needless to say that the high speed reproduction, particularly on the high speed side in the standard recording mode, may be set to 8.5 times speed in the case of the recording format shown in the first embodiment and realized only by speed control. Absent.

The high speed reproduction speeds set for the respective recording modes are not limited to those shown in the first embodiment.

Further, the number of data areas for special reproduction is not limited to that shown in the first embodiment, and in each recording mode, the rotary heads 26a and 26b are set to the sub heads during high speed reproduction of special reproduction data. It may be arranged on the scanning locus for scanning the code area or the VAUX area.

The size of the trick play data area is not limited to that shown in the first embodiment.

In the first embodiment, the 25 Mbps recording mode is the standard recording mode, but the present invention is not limited to this, and 50 Mbps is the standard recording mode or 12.
Even when 5 Mbps is set as the standard recording mode, the same track format is used in each recording mode, and only the number of times the special reproduction data is repeated is switched in each recording mode for recording, whereby the special reproduction data can be efficiently recorded. Therefore, it is possible to improve the reproduction image quality of the high-speed reproduction image in each recording mode.

In the first embodiment, the case of a digital VTR having three kinds of recording modes, that is, the standard recording mode, the 1/2 recording mode and the 1/4 recording mode shown in FIG. 7, will be described. However, the present invention is not limited to this, and for example, two types of the above recording modes,
It goes without saying that the same effect can be obtained with a digital VTR having four types of recording modes. Further, the recording modes are not limited to the above three types of recording modes.

Example 2. In the second embodiment, a method of using the area shown as the ECC3 area in the first embodiment will be described. In the present embodiment, in addition to the C4 check code, normal reproduction data, special reproduction data, or C5 check code is recorded in the ECC3 area indicated by D0 to D3 in FIG. To do.

First, the case where the C4 check code is recorded in the ECC3 area will be described. D0-D during normal playback
All of the C4 check codes recorded in the area 3 are reproduced. The configuration of the C4 check code in this embodiment is (138,
128, 11) Reed-Solomon code,
Perform track interleaving.

An interleaving method which is an embodiment of the present invention will be described with reference to FIG. Note that the track number in the data block when constructing the C4 check code is Tn.
(0 ≦ Bn ≦ 9), the sync block number in the track is SBn (0 ≦ SBn ≦ 137), and the data whose sync block data number is Dn (0 ≦ Dn ≦ 75) is D [Dn, SBn, Tn],
(D [0,0,0], D [0,1,1], D [0,
2, 2], ..., D [5 × (j- (j mod 1
0)) / 10 mod 76, j, (j mod 1
0)], ..., D [60, 126, 6], D [60,
127, 7], ..., D [65, 136, 6], D
[65,137,7]). Where D [0,0,
0] to D [60,126,6], and D [65,13]
128 bytes of [7, 7] are information symbols, D [60, 1
The 10 bytes from 27,7] to D [65,136,6] are the C4 check code. FIG. 25 schematically shows the interleave operation. Interleaving is performed on the data (symbols) of the 138 sync blocks in the direction of the arrow.

This operation is performed on all the data in the sync block at the head of each track. That is, when generating the C4 check code with the i-th data starting from the sync block at the beginning of the k-th track, (D [i, 0,
k], D [(i, 1, (k + 1 mod 10)], ...
.., D [(i + 5 * (j- (j mod 10)) /
10) mod 76, j, (k + j mod 1
0)], ..., D [(i + 60 mod76), 1
27, (k + 127 mod 10)], D [(i +
60 mod 76), 128, (k + 128 mod
10)], ..., D [(i + 65 mod 76),
138, (k + 138 mod 10)]) becomes 1
Interleaving is performed by changing i from 0 to 75 per track and applying it to 10 tracks (k is changed from 0 to 9) to generate a C4 check code. 25, or (X mod Y) or (X mod. Y) in the above equation represents the remainder when the integer X is divided by the integer Y. The data for which the C4 check code has been generated by interleaving is recorded in a predetermined area shown in FIG. 16 or FIG.

Next, the burst error correction capability of the C4 check code of this embodiment will be described. As shown in FIG. 25, each track is subjected to data interleaving with a depth of 10 tracks and encoded. Further, since the C4 check code has a minimum distance of 11, it is possible to correct errors up to 10 erasures. In the first embodiment, unlike the case of the conventional interleaving, focusing on the distance of the interleaved data on the track of track number 0 shown in FIG. 25, symbols can be arranged at equal intervals of all 10 sync blocks + 5 symbols, Regardless of where a long dropout occurs during normal reproduction (when a long burst error occurs within one track), the error correction capability by the C4 check code can be made uniform regardless of the position where the burst error occurs. .

In the C4 check code, as shown in FIG. 25, a data block of 138 sync blocks was subjected to data interleaving with a depth of 10 tracks to generate a code word. Further, since the C4 check code has a minimum distance of 11, it is possible to correct errors up to 10 erasures. Therefore, assuming that no error is detected in other tracks, the maximum burst error correction capability is 10 × 10.
= 100 sync blocks. Therefore, it is possible to restore the data by the C4 check code even when the data of 100 sync blocks in one track has not been reproduced due to dropout during normal reproduction.

In the SD standard digital VTR, when the frame frequency is 30 Hz, one frame of digital video signal is recorded on 10 tracks. At that time, 1 above
Track numbers are sequentially added to the ID signal from the beginning of the 10 tracks for recording frame data. Specifically, since the same number is added to the pair of the A track and the B track, track numbers 0 to 4 are added. As is well known in the United States, since the frame frequency is 30 Hz, the track number is added in the above-described manner in the SD standard digital VTR. Example 2
Then, I will omit the explanation, but PAL / SECA in Europe etc.
In the M area, since the frame frequency is 25 Hz, one frame of data is recorded on 12 tracks, and track numbers 0 to 5 are added. Therefore, it goes without saying that the interleaving may be performed in units of 12 tracks.

The general formula of the above data interleaving method is shown below. Here, when the number of data in the u direction shown in FIG. 25 is n1, the number of effective samples in the w direction is n3, the number of information symbols of the C4 check code is k2, and the minimum distance of the C4 check code is d3, the code word V (Z) is expressed by the following polynomial. V (Z): polynomial expression of code word D (u, v, w): symbol ... 0 ≦ u <n1, 0 ≦ v <k2 + d
3-1, 0 ≦ u <n3 α: 0 <α ≦ n1 / (k2 + d3-1) × n3 Here, α is a parameter that determines the interleave length and is determined so as to satisfy the above condition. Note that when determining α, it is possible to generate a very efficient codeword by deciding not to use the error detection flag detected by the same C2 check code in one codeword.

Next, in the case of performing the 18 × speed reproduction in the standard recording mode shown in FIG. 19 in the first embodiment, and in FIG.
The case where the ECC3 area is used as the special reproduction data or the area for recording the C5 check code will be described as an example of the case of performing the 4 × speed reproduction in the standard recording mode shown in FIG. As shown in FIG. 19, when the 18 × speed reproduction is performed in the standard recording mode, the EC is set as the sixth burst.
The head 26a traces the C3 area. Also, FIG.
As shown in FIG. 8, when quadruple speed reproduction is performed in the standard recording mode, the head 26b traces the quadruple speed reproduction area and the ECC3 area in contact with the quadruple speed reproduction area.

The details of the recording area in the case where the ECC3 area is used as an area for recording the C5 check code in this embodiment will be described below. 26 is the same as FIG.
It is an enlarged view of the ECC3 area, special reproduction data,
Alternatively, details of the ECC3 area when used as an area for recording the C5 check code are shown. As shown, T1
The area of 5 sync blocks in the ECC3 area corresponding to the sixth burst following the five 18x speed reproduction areas A0 to A4 provided on the track and the T3 track is the 18x speed reproduction area or the 18x speed reproduction C5 area. As the areas for recording the check code, E0 is provided on the T1 track and E1 is provided on the T3 track. Further, in the figure, the ECC adjacent to the 4 × speed reproduction area B0 provided as one area on the T2 track
An area of 5 sync blocks in 3 areas is provided as an area for quadruple speed reproduction or an area F1 for recording a C5 check code for quadruple speed reproduction. The number of sync blocks in each area of E0, E1, and F1 is set according to FIG. In this embodiment, the ECC3
The code configuration for recording the C5 check code in the area is a (30, 25, 6) Reed-Solomon code.

As described above, the ECC3 area is arranged in the 10 sync blocks at the upper end of the video area, and the ECC3
By recording not only the C4 check code but also the C5 check code for 18x speed reproduction or the data for 18x speed reproduction in the area of, the ECC at 18x speed reproduction in the standard recording mode is recorded.
Five sync blocks in the three areas can be reproduced as the sixth burst area following the five areas A0 to A4. Therefore, when it is desired to increase the amount of data for 18 × speed reproduction in the areas E0 and E1, the data for 18 × speed reproduction is recorded, and the reliability of the 18 × speed reproduction data is increased. Records the C5 check code for 18 × speed reproduction.

By arranging the ECC3 area in 10 sync blocks at the upper end of the video area and arranging the 4 × speed reproduction area B0 in the standard recording mode at a position adjacent to the ECC3 area, the standard recording mode is set. At the time of quadruple speed reproduction, 5 sync blocks adjacent to the B0 area in the ECC3 area can be reproduced as one area continuous with the B0 area. Therefore, the above F1
In this area, if it is desired to increase the amount of data for quadruple speed reproduction, quadruple speed reproduction data is recorded, and if it is desired to increase the reliability of quadruple speed reproduction data, quadruple speed reproduction data is recorded. Record the C5 check code.

As described above, in this embodiment, the ECC3 area is arranged in the ten sync blocks at the upper end of the video area, and either the C4 check code, the C5 check code, or the special reproduction data is placed in the ECC3 area. Since the data can be recorded, it is possible to improve the reproduction image quality during high-speed reproduction and the reliability of high-speed reproduction data depending on the application.

The data to be recorded in the ECC3 area is not limited to the C4 check code, the C5 check code, the normal reproduction data and the special reproduction data, and other additional information may be recorded.

The data structure of the ECC3 area is not limited to this, and the C5 check code structure is not limited to this.

Further, in the present embodiment, 4 in the standard recording mode.
The case where the double speed reproduction and the 18 times speed reproduction are performed has been described as an example, but the present invention is not limited to this, and the four times speed reproduction and the nine times speed reproduction in the 1/2 times recording mode as in the first embodiment are performed. Or at 8x speed playback in 1 / 4x recording mode,
Also, the same effect can be obtained during 18 × speed reproduction.

[0163]

Since the present invention is constructed as described above, it has the following effects.

According to the digital signal recording apparatus of the first aspect of the present invention, the digital signal recording apparatus has a plurality of recording modes including at least the standard recording mode, and the frame or field input in the state of the transport packet or the frame or field In a digital signal recording device that transparently records an inter-field encoded digital video signal and a digital audio signal on a recording medium, first, the transmission rate of the input transport packet is determined. Then, the transmission rate determining means and the recording mode of the digital signal recording device are set based on the determination result. On the other hand, the digital video signal encoded in the frame or in the field from the input transport packet is separated from the transport packet. Then, the separated digital video signal subjected to the frame or intra-field encoding is reconstructed and converted into special reproduction data. Then, in order to record the input transport packet, the special reproduction data, and the error check code at a predetermined position of the track on the recording medium, the recording format is formed in the recording format generating means.
When generating the recording data to be recorded on the magnetic recording tape by the recording format generating means, any of the C4 inspection code, the normal reproduction data, the C5 inspection code, and the special reproduction data is stored in the area for recording the error check code. Since the recording format generating means is controlled so as to record the data, the special reproduction data can be efficiently recorded in each recording mode, so that the limited special reproduction data area can be efficiently used. Also, the reproduction data rate during high-speed reproduction can be maximized, and the reproduction image quality can be improved. Further, there is an effect of improving the reliability of the reproduced data at the time of high speed reproduction.

According to the digital signal recording apparatus of the second aspect of the present invention, when the input intra image data is generated by the special reproduction data generating means,
The special reproduction data is generated in the form of the input transport packet. When the special reproduction data generated in the transport packet format is recorded on the recording medium, it is converted into the sync block format and recorded similarly to the input data, so that the high speed reproduction is performed by the digital signal reproducing apparatus. , No circuit for transport packet generation is required, and a circuit for converting the sync block format for normal playback into transport packets can be shared, and the circuit scale is reduced especially in a playback-only device. There is an effect that can be.

Further, according to the digital signal recording apparatus of the third aspect of the present invention, the data transmitted in the transport packet format represented by MPEG2 is recorded in the SD.
When recording on a digital VTR represented by a standard, when generating a sync block format by the recording data generating means, generating data of a 5-line sync block by using the two input transport packets. This has the effect of efficiently converting the transport packet data into the sync block format.

Further, according to the digital signal recording apparatus of the fourth aspect of the present invention, when the recording format is generated, the special signal is formed on the scanning locus scanned by the head at a predetermined high reproduction speed in each recording mode. Since the data for reproduction is arranged, the data for special reproduction can be efficiently recorded in each recording mode, so that the limited data area for special reproduction can be efficiently used and the reproduction data rate at the time of high-speed reproduction can be maximized. Therefore, there is an effect that the reproduction image quality can be improved.

Further, according to the digital signal recording apparatus of the fifth aspect of the present invention, when the recording format is generated, the scanning locus by which the head scans the sub code area at a predetermined high reproduction speed of each recording mode. Since the recording format generating means is controlled so as to arrange the special reproduction data on the above, and since the rotary head traces the subcode area or the VAUX area during high speed reproduction, the signal to be recorded in the subcode area is recorded. There is an effect that it is possible to obtain an additional function such as a cue function by using it.

According to the digital signal reproducing apparatus of the sixth aspect of the present invention, the special reproduction data separated from the recording data has a plurality of recording modes including the standard recording mode and is set in a predetermined area. In the digital signal recording / reproducing apparatus for reproducing the recording medium recorded in (1), the recording mode is detected from the reproduction signal at the time of reproduction. Then, the tape running speed of the recording medium is controlled based on the recording mode detection result. At that time, since the head controls the tracking so that the head scans the subcode area or the VAUX area at the time of high-speed reproduction at the predetermined tape running speed in the above recording mode, the subcode area or the VAUX area may be changed at the time of high-speed reproduction. Since the rotary head traces, it is possible to obtain an additional function such as a cueing function by using a signal recorded in the subcode area or the VAUX area.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a recording system of a digital VTR according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a trick play data generation circuit according to the first embodiment.

FIG. 3 is a block diagram illustrating a configuration example of a quadruple speed reproduction data generation circuit according to the first exemplary embodiment.

FIG. 4 is a block diagram showing a configuration example of a recording data control circuit of the first embodiment.

FIG. 5 is a block diagram illustrating a configuration example of a data synthesizing circuit according to the first exemplary embodiment.

FIG. 6 is a digital V recording multi-rate signal.
FIG. 3 is a conceptual diagram when a signal is recorded on a magnetic tape by a digital VTR having a rotary head arrangement of each channel on a typical rotary drum used in TR and the head arrangement.

FIG. 7 is a diagram showing a recording mode of a digital VTR for recording a multi-rate bit stream.

FIG. 8 is a diagram showing a recording timing of recording data in each recording mode.

FIG. 9 is a diagram showing timings of control signals output from a recording timing generation circuit in each recording mode.

FIG. 10 is a data format diagram of a video signal recording area in one track of a video signal according to the SD standard.

FIG. 11 is a diagram showing the structure of one sync block in the SD standard.

FIG. 12 is a diagram showing a recording format in one track of the SD standard.

13A and 13B are diagrams showing a sync block format according to the first embodiment. FIG. 13A is a transport packet diagram of an input bit stream, and FIG. 13B is a recording sync block diagram for recording on a magnetic tape.

FIG. 14 is a diagram showing the number of sync blocks that can be reproduced from one track at each high reproduction speed according to the first embodiment.

FIG. 15 is a diagram showing a track format of a 4-track cycle including the arrangement of a special reproduction data recording area in the first embodiment.

16 is a diagram showing a recording track pattern for a standard recording mode, which is arranged on the magnetic tape having the track format shown in FIG.

FIG. 17 is a diagram showing recording track patterns arranged on a magnetic tape having the track format shown in FIG. 15 for 1/2 × and 1/4 × route recording modes.

FIG. 18 shows a recording track pattern of FIG.
It is a figure which shows the scanning locus of a rotary head at the time of quadruple speed reproduction at the rate of ps.

FIG. 19 shows a recording track pattern of FIG.
It is a figure which shows the scanning locus of a rotary head at the time of 18x speed reproduction at the rate of ps.

FIG. 20 shows the recording track pattern of FIG.
It is a figure which shows the scanning locus of a rotary head at the time of quad-speed reproduction | regeneration at the rate of Mbps.

FIG. 21 shows the recording track pattern of FIG.
It is a figure which shows the scanning locus of a rotary head at the time of 9-times speed reproduction | regeneration at the rate of Mbps.

FIG. 22 shows a recording track pattern of FIG.
It is a figure which shows the scanning locus | trajectory of a rotary head at the time of 8 times speed reproduction at the rate of Mbps.

FIG. 23 shows the recording track pattern of FIG.
It is a figure which shows the scanning locus | trajectory of a rotary head at the time of 18 times speed reproduction at the rate of Mbps.

FIG. 24 is a block circuit diagram of a reproducing system of the digital VTR of the first embodiment.

FIG. 25 is a diagram illustrating an interleaving method when performing error correction coding for normal reproduction according to the second embodiment.

FIG. 26 is a diagram for explaining the content of data to be recorded in the ECC3 area according to the second embodiment.

FIG. 27 is a track pattern diagram of a conventional general home-use digital VTR.

FIG. 28 shows a conventional digital VTR during normal reproduction,
It is a figure which shows the head scanning locus of a rotary head at the time of high speed reproduction.

FIG. 29 is a block circuit diagram of a conventional bitstream recording / reproducing apparatus capable of high-speed reproduction.

FIG. 30 is a diagram showing an outline of a conventional digital VTR during normal reproduction and high-speed reproduction.

FIG. 31 is a diagram showing an example of a rotary head scanning locus during general high-speed reproduction.

[Fig. 32] Fig. 32 is a diagram for explaining an overlapping area at a plurality of conventional high-speed reproduction speeds.

FIG. 33 is a diagram showing rotary head scanning loci at 5 × speed and 9 × speed in a conventional digital VTR.

FIG. 34 is a diagram showing two rotary head scanning loci during 5 × speed reproduction in a conventional digital VTR.

FIG. 35 is a track layout diagram of a conventional digital VTR.

[Explanation of symbols]

4 variable length encoder, 5 counter, 6 data extracting circuit, 7 EOB adding circuit, 10 header analyzing circuit, 1
2 special reproduction data creation circuit, 13 first memory,
14 4 × speed reproduction data generation circuit, 15 18 × speed reproduction data generation circuit, 16 2nd memory, 17 3rd
Memory, 18 rate discriminating circuit, 19 recording data control circuit, 20 data synthesizing circuit, 21 fourth memory, 2
2 second error correction code circuit, 23 digital modulation circuit, 26 rotary head, 27 drum motor control circuit,
28 drum motor, 29 capstan motor control circuit, 30 capstan motor, 31 first error correction code circuit, 32 third error check code circuit, 42 transport header correction circuit, 43 header addition circuit, 4
4 packetizing circuit, 45 transport header adding circuit, 55 recording mode setting circuit, 56 recording timing generating circuit, 57 special reproduction data code amount setting circuit,
58 servo system reference signal generation circuit, 126 format generation circuit, 127 format generation circuit control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ken Onishi, No. 1 Baba Institute, Nagaokakyo-shi Video System Development Laboratory, Mitsubishi Electric Corporation

Claims (6)

[Claims] 1. A digital video signal, which has a plurality of recording modes including at least a standard recording mode, is encoded in a frame or field, or is encoded in a frame or field, and a digital audio signal. In a digital signal recording device for transparently recording and on a recording medium, a transmission rate determining means for determining a transmission rate of the input transport packet, and a recording for setting a recording mode of the digital signal recording device based on the determination result. Mode setting means, data separation means for separating the frame- or field-encoded digital video signal from the transport packet, and frame or field-encoded data separated by the data separation means. A special reproduction data generating means for reconstructing the applied digital video signal to generate special reproduction data, and the transport packet, the special reproduction data, and the error check code in a predetermined track of the recording medium. In addition to having a recording format generating means for generating a recording format for recording at a position, the area for recording the error check code has an error check code for normal reproduction, normal reproduction data, and error check for special reproduction. A digital signal recording apparatus characterized by controlling the recording format generating means so as to record either a code or special reproduction data. 2. The digital signal recording apparatus according to claim 1, wherein the special reproduction data is generated in the form of the transport packet. 3. The digital signal recording according to claim 1, wherein when the recording format generating means generates a sync block format, data of 5 sync blocks is generated by using the two transport packets. apparatus. 4. When generating a recording format, the recording format generating means is controlled so as to arrange the special reproduction data on a scanning locus scanned by a head at a predetermined high reproduction speed in each recording mode. The digital signal recording device according to claim 1, wherein 5. When a recording format is generated, the head is in a subcode area or VAUX (video a) at a predetermined high reproduction speed in each recording mode.
5. The digital signal recording apparatus according to claim 4, wherein the recording format generating means is controlled so that the special reproduction data is arranged on a scanning locus for scanning an auxiliary area. 6. A digital signal recording / reproducing apparatus for reproducing a recording medium having a plurality of recording modes including a standard recording mode and recording special reproduction data separated from the recording data in a predetermined area. Recording mode detection means for detecting the recording mode from a signal, recording medium running speed control means for controlling the tape running speed of the recording medium based on the recording mode detection result, and a predetermined tape running speed in the recording mode. 2. A digital signal reproducing apparatus having tracking control means for controlling tracking so that the head scans the subcode area or the VAUX area during high speed reproduction.