JPH08250708A - Power semiconductor device - Google Patents

Abstract

PURPOSE: To enable semiconductor device to be composed of GTO in lower voltage than conventional one with less switching loss by specifying the maximum impurity concentration of the second conductivity type base layer not to exceed a specific value. CONSTITUTION: A p-type base layer 4, an n layer emitter layer 5 are formed on the surface of an n-type base layer 1 to compose a mesa, a cathode electrode 6 is provided on the n-type emitter layer 5, a gate electrode 7 is provided on the p-type base layer 4 while the gate electrode 7 is connected to the p-type base layer 4 through the intermediary of a high concentration p-type contact later 8. At this time, the p-type contact layer 8 fills the role of lowering the contact resistance of the gate electrode 7 and the p-type base layer 4 as well as the lateral directional resistance of the p-type base layer 4 while a p-type emitter layer 2 and an anode electrode 3 are provided on the underside of an n-type base layer 1. Accordingly, when the maximum impurity concentration of the p-type base layer 4 is set up not to exceed 2×10<17> cm<-3> as well as Ws=200μm, Wm=40μm and Ws.Wm value not to exceed 10000μm<2> , the ON value can be lowered without cutting down the interrupting current.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a GTO (Gate Turn-Of
f thyristor).

[0002]

2. Description of the Related Art A GTO is one of power semiconductor devices. GTO has a self-turn-off function that is impossible with general thyristors, so a rectifier circuit is not required,
The size and weight of the device can be reduced and the performance can be improved. GTO is np
Based on an np four-layer structure thyristor, the n-type emitter layer was provided with a cathode electrode, the p-type base layer was provided with a gate electrode, and the p-type emitter layer was provided with an anode electrode. It has a structure.

FIG. 19 is a sectional view showing the element structure of a conventional mesa type GTO. In the figure, 101 indicates a high-resistance n-type base layer, and the surface of the n-type base layer 101 is p
The type base layer 104 and the n-type emitter layer 105 are sequentially formed. p-type base layer 104, n-type emitter layer 105
Constitutes a mesa.

In such a mesa, for example, the p-type base layer 104 is formed on the surface of the n-type base layer 101, and then the n-type emitter layer 105 is diffused and formed on the surface of the p-type base layer 104, and then the p-type base layer 104 is formed. It is obtained by etching the type base layer 104 and the n-type emitter layer 105 into a mesa shape.

The n-type emitter layer 105 has a cathode electrode 1
06, and the gate electrode 1 is provided on the p-type base layer 104.
07 is provided. The gate electrode 107 has a high concentration of p
It is connected to the p-type base layer 104 via the type contact layer 108.

On the other hand, a p-type emitter layer 102 is provided on the back surface of the n-type base layer 101.
2 is provided with an anode electrode 103. To turn on this element, a positive voltage is applied to the gate electrode 107 with respect to the cathode. As a result, electrons are injected from the n-type emitter layer 105 into the n-type base layer 101, and a corresponding amount of holes are injected from the p-type emitter layer 102 into the n-type base layer 101, resulting in conductivity modulation. Occurrence element turns on. Once turned on, the element can be turned on without applying a positive voltage to the gate electrode 107. The on-voltage decreases as the carriers accumulate.

On the other hand, in order to turn off the device, a negative voltage is applied to the gate electrode 107 with respect to the cathode. As a result, the p-type emitter layer 102 to the n-type emitter layer 10
The hole current flowing in 5 is bypassed to the gate electrode 107, the electron injection from the n-type emitter layer 105 is stopped, and the element is turned off.

Here, since the hole current flows laterally in the p-type base layer 104 and is bypassed to the gate electrode 107, when the resistance of the p-type base layer 104 is large, the positive current is sufficiently positive from the p-type base layer 104. There is a problem that the hole current cannot be discharged to the gate electrode and the maximum controllable current (maximum turn-off current) becomes small.

Therefore, in the conventional GTO, the impurity concentration of the p-type base layer 104 is made sufficiently high (5 × 10 ¹⁷ to
The maximum controllable current is increased to 1 × 10 ¹⁸ cm ⁻³ ). However, if the impurity concentration of the p-type base layer 104 is increased, carriers are likely to be recombined in the p-type base layer 104 at turn-on.
The electrons injected from
The amount of electrons injected into the mold base layer 101 is reduced.

As a result, the accumulated carriers in the portion of the n-type base layer 101 near the cathode are reduced, and the on-voltage is increased. If an attempt is made to increase the number of accumulated carriers on the anode side in order to lower the on-voltage, there arises a problem that the switching loss (turn-off loss) will increase.

[0011]

As described above, the conventional G
In TO, the impurity concentration of the p-type base layer is increased in order to increase the maximum controllable current (maximum turn-off current), but carrier recombination easily occurs in the p-type base layer at turn-on. Therefore, there is a problem that the number of accumulated carriers in the n-type base layer is reduced and the on-voltage is increased. In addition, if the number of accumulated carriers on the anode side is increased in order to lower the on-voltage, there is a problem that the switching loss (turn-off loss) is increased this time.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to use a GTO having a lower on-voltage than the conventional one, and to add a simple technical means to perform switching. An object of the present invention is to provide a power semiconductor device capable of reducing loss.

[0013]

In order to achieve the above object, a power semiconductor device according to the present invention (claim 1) (first
Invention), a second conductivity type base layer formed on the surface of the first conductivity type base layer, a first conductivity type emitter layer formed on the surface of the second conductivity type base layer, and the second conductivity type. Second conductivity type emitter layer formed on the surface of the first conductivity type base layer opposite to the first conductivity type base layer, a control electrode provided on the second conductivity type base layer, and the second conductivity type emitter layer And a second main electrode provided on the first conductivity type emitter layer, and a power semiconductor element is formed in an array, and a maximum of the second conductivity type base layer is formed. The impurity concentration is 2 × 10 ¹⁷ cm ⁻³ or less.

Further, another power semiconductor device of the present invention (second invention) is that the second conductivity type base layer formed on the surface of the first conductivity type base layer and the second conductivity type base layer. A first conductivity type emitter layer formed on the surface, a second conductivity type emitter layer formed on the surface of the first conductivity type base layer opposite to the second conductivity type base layer, and the second conductivity type A power semiconductor including a control electrode provided on a base layer, a first main electrode provided on the second conductivity type emitter layer, and a second main electrode provided on the first conductivity type emitter layer. Elements are arranged in an array, the maximum impurity concentration of the second conductive type base layer is 2 × 10 ¹⁷ cm ⁻³ or less, and the distance between the control electrodes adjacent to each other with the second main electrode interposed therebetween is the first It is characterized by being ⅙ or more of the thickness of the conductive type base layer.

Further, another power semiconductor device of the present invention (third invention) is that the second conductivity type base layer formed on the surface of the first conductivity type base layer and the second conductivity type base layer. A first conductivity type emitter layer formed on the surface, a second conductivity type emitter layer formed on the surface of the first conductivity type base layer opposite to the second conductivity type base layer, and the second conductivity type A power semiconductor including a control electrode provided on a base layer, a first main electrode provided on the second conductivity type emitter layer, and a second main electrode provided on the first conductivity type emitter layer. Elements are formed in an array, the maximum impurity concentration of the second conductive type base layer is 2 × 10 ¹⁷ cm ⁻³ or less, the distance between the control electrodes adjacent to each other with the second main electrode interposed therebetween, and The product with the substantial width of the one-conductivity-type emitter layer is 10,000.
It is characterized in that it is not more than μm ² .

Another power semiconductor device of the present invention (fourth invention) is a second conductivity type base layer formed on the surface of the first conductivity type base layer, and a second conductivity type base layer. A first conductivity type emitter layer formed on the surface, a second conductivity type emitter layer formed on the surface of the first conductivity type base layer opposite to the second conductivity type base layer, and the second conductivity type A power semiconductor including a control electrode provided on a base layer, a first main electrode provided on the second conductivity type emitter layer, and a second main electrode provided on the first conductivity type emitter layer. Elements are arranged in an array, the maximum impurity concentration of the second conductive type base layer is 2 × 10 ¹⁷ cm ⁻³ or less, and the distance between the control electrodes adjacent to each other with the second main electrode interposed therebetween is the first 1/6 or more of the thickness of the conductive type base layer and adjacent to each other with the second main electrode interposed therebetween. The distance between the control electrode, the product of the substantial width of the first conductive type emitter layer 10000μ
It is characterized by being m ² or less.

[0017]

According to the research conducted by the present inventor, the device of the present invention (GT
It was found that in the O) structure, the on-state voltage drastically decreases when the maximum impurity concentration of the second conductivity type base layer is 2 × 10 ¹⁷ cm ⁻³ .

Therefore, according to the power semiconductor device of the present invention based on the above findings, the on-voltage can be made lower than in the conventional case. Further, according to the research by the present inventor, in the device (GTO) structure of the present invention, when the maximum impurity concentration of the second conductivity type base layer is 2 × 10 ¹⁷ cm ⁻³ or less, the maximum impurity concentration value is Irrespective of whether the product of the distance between the control electrodes adjacent to each other with the second main electrode sandwiched therebetween and the substantial width of the first conductivity type emitter layer is 10000 μm ² or less, the same breaking current as in the conventional case can be obtained. I understood.

Therefore, if simple technical means based on the above knowledge is added to the power semiconductor device according to the present invention,
That is, according to the third and fourth inventions, 2 × 10 ¹⁷ cm
^{When it is -3} or less and 10000 μm ² or less, the on-voltage can be lowered as compared with the conventional case without lowering the breaking current.

[0020]

Embodiments will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a sectional view showing an element structure of a mesa type GTO according to the first embodiment of the present invention. This is 1
A cell portion is shown, and an array of such mesa type GTOs is the power semiconductor device of the present invention.

In the figure, reference numeral 1 denotes a high-resistance n-type base layer, and on the surface of the n-type base layer 1, a p-type base layer 4,
The n-type emitter layer 5 is sequentially formed. The p-type base layer 4 and the n-type emitter layer 5 form a mesa.

In such a mesa structure, for example, the p-type base layer 4 is formed on the surface of the n-type base layer 1, and then the p-type base layer 4 is formed.
It is obtained by diffusing the n-type emitter layer 5 on the surface of the type base layer 4 and then etching the p-type base layer 4 and the n-type emitter layer 5 into a mesa shape.

A cathode electrode 6 is provided on the n-type emitter layer 5, and a gate electrode 7 is provided on the p-type base layer 4. The gate electrode 7 is connected to the p-type base layer 4 via the high-concentration p-type contact layer 8. The p-type contact layer has a role of reducing the contact resistance between the gate electrode 7 and the p-type base layer 4, and a role of reducing the lateral resistance of the p-type base layer 4.

On the other hand, a p-type emitter layer 2 is provided on the back surface of the n-type base layer 1, and an anode electrode 3 is provided on the p-type emitter layer 2. The impurity concentration of the n-type base layer 1 is 2 × 10 ¹³ cm ⁻³ , the maximum impurity concentration of the p-type base layer 4 is 2 × 10 ¹⁷ cm ⁻³ or less, and the thickness of the n-type base layer 1 is 6
50 μm, the substantial width Wm of the n-type emitter layer 5 is 40 μm
m, the distance Wgg between the gate contacts (where the gate electrode and the p-type base layer are in contact) is 140 μm, and the distance (width of the unit cell) Ws between adjacent gate electrodes 7 with the anode electrode 3 interposed therebetween is 200 μm.

The substantial width Wm of the n-type emitter layer 5 is
Net n-type emitter layer 5 at the junction with the p-type base layer 4
18, the p-type contact layer 8 is removed from the n-type emitter layer 5 when the p-type contact layer 8 is formed within the region of the n-type emitter layer 5, as shown in FIG. The width of the part is Wm.

The maximum impurity concentration of the p-type base layer 4 is the maximum impurity concentration of the p-type base layer 4 substantially on the center line of the n-type emitter layer 5. The maximum impurity concentration of the p-type base layer 4 and the parameters of Wm, Wgg, and Ws were obtained from FIGS. 2 and 3.

FIG. 2 shows the relationship between the maximum impurity concentration of the p-type base layer 4 and the on-state voltage V _F , and the product of Ws and Wm (W, which is necessary to obtain the same breaking current as that of the conventional GTO).
s · Wm). In the figure, the value in parentheses indicates the value of Wm in the conventional design.

From FIG. 2, the on-state voltage V _F begins to rise sharply when the maximum impurity concentration of the p-type base layer 4 is around 2 × 10 ¹⁷ cm ^-3 . Therefore, in order to reduce the ON voltage V _F ,
As in this embodiment, it is desirable that the maximum impurity concentration of the p-type base layer 4 be 2 × 10 ¹⁷ cm ⁻³ or less.

The reason why the on-voltage V _F rises is that when the maximum impurity concentration of the p-type base layer 4 increases, the electrons injected from the n-emitter layer 5 recombine with holes in the p-type base layer 4,
This is because sufficient electrons are not supplied to the n-type base layer 1.

Further, from FIG. 2, the value of Ws · Wm required to obtain the same breaking current as that of the conventional GTO is that the maximum impurity concentration of the p-type base layer 4 is 2 × 10 ¹⁷ cm ⁻³ or less. If there is, it is constant at about 10000 μm ² , and if it exceeds it, it rises sharply.

Therefore, as in this embodiment, Ws = 2
Set 00 μm and Wm = 40 μm, and set the value of Ws · Wm to 10
If it is set to 000 μm ² or less, it is possible to secure the same breaking current as the conventional one while keeping the on-voltage V _F low. In other words, the on-voltage can be lowered as compared with the conventional case without reducing the breaking current.

On the other hand, if it is 10000 μm ² or less, even if the maximum impurity concentration of the p-type base layer 4 is poorly controlled, the conventional G
A breaking current similar to that of TO can be easily obtained. If the maximum impurity concentration of the p-type base layer 4 is high, the hole extraction resistance at the time of turn-off becomes small. Therefore, even if Ws · Wm, in other words, the n-type emitter layer 5 is relatively large, it can be turned off. On the other hand, if the maximum impurity concentration of the p-type base layer 4 is low, the hole extraction resistance at turn-off becomes large,
To be able to turn off, it is necessary to reduce Ws · Wm in order to reduce the resistance.

FIG. 3 is a characteristic diagram showing the relationship between Wgg / Ldiff and ON voltage V _F. Further, in FIG. 3, Wgg /
The relationship between Ln _B and ON voltage V _F is also shown. Ldiff is the diffusion length of the n-type base layer in the high implantation state, and Ln _B is the thickness of the n-type base layer.

It can be seen from FIG. 3 that when Wgg is shorter than Ldiff, the on-voltage V _F rapidly rises.
Must be larger than Ldiff. This is because the recombination of electrons and holes at the contact interface (gate contact interface) between the gate electrode and the p-type base layer causes the electrons injected from the n-type emitter layer to disappear.

Since the thickness Ln _B of the n-type base layer is usually about 6 times the diffusion length of the n-type base layer in the high implantation state,
If Wgg is set to be larger than one sixth of the thickness of the n-type base layer, for example, by setting n-type base layer thickness = 650 μm and Wgg = 140 μm as in this embodiment,
Wgg is larger than Ldiff, and an element having a low on-voltage V _F can be realized (second invention).

From the above, Ln _B / 6 <W
The relationship of gg <10000 / Wm is obtained. (Unit: μ
m) In this embodiment, Wm = 40 μm, but it may be smaller than that. In that case, the breaking ability (turn-off characteristic) is further improved.

Further, in this embodiment, the ratio of the n-type emitter layer to the active area of the device is 20%, but the smaller the ratio, the higher the blocking ability. Further, in this embodiment, Wg
Although g = 140 μm is set, it may be larger than that. In this case, the ON voltage can be further lowered.

Further, in this embodiment, in order to suppress recombination of carriers at the contact interface (gate contact interface) between the gate electrode and the p-type base layer, the ratio of the contact interface to the element effective area is set to 30% or less. ing.

Up to this point, the effect on the ON voltage has been mainly described, but next, the effect on the turn-off characteristic such as the switching characteristic will be described. FIG.
FIG. 6 is a diagram showing a carrier distribution and a turn current waveform in an n-type base layer of a conventional GTO. In the n-type base layer, conduction modulation occurs due to holes and electrons, and holes and electrons have the same carrier distribution. In the figure, n indicates the number of carriers.

FIG. 4A shows the carrier distribution in the ON state, FIG. 4B shows the carrier distribution at the turn-off fall time, and FIG. 4C shows the carrier distribution at the tail time. Further, FIG. 4D shows the waveform of the turn current in each of the above states.

At the beginning of turn-off such as fall time,
Carriers with a negative carrier distribution differential (dn / dx <0) are discharged, and then carriers with a positive carrier distribution differential (dn / dx> 0) are discharged.

However, the differentiation of the carrier distribution means the differentiation along the current from the cathode side to the anode side. Figure 5
FIG. 4 is a characteristic diagram showing the relationship between the carrier distribution derivative (dn / dx), the grounded base amplification factor αpnp, and the current density. From FIG. 5, it can be seen that the larger dn / dx and the smaller the current density, the larger αpnp.

The switching loss during turn-off increases when a large amount of current flows through the device during turn-off. Therefore, it is desirable to reduce the total amount Q _off of the current flowing through the element during turn- _off . Q _off can be _calculated by the following formula.

[0044]

[Equation 1]

From this equation, in the n-type base layer, dn /
It can be seen that increasing the region of dx <0, in other words, making the differential value as small as possible is effective in reducing Q _off and reducing switching loss.

The tail current becomes large as compared with the other parts. This is because in the tail current portion, the current density becomes small and dn / dx> 0, so under such conditions,
This is because αpnp becomes close to 1 as shown in FIG.

Conventionally, by introducing an anode short structure or the like, an increase in carriers on the anode side has been suppressed.
In the conventional structure, since the amount of carriers accumulated in the n-type base layer on the cathode side remains small, dn / dx cannot be sufficiently reduced, resulting in a large loss and a high maximum impurity concentration in the p-type base layer. There is a problem that the number of accumulated carriers is small and the ON voltage is high.

However, in the case of the present invention, when the anode-side carrier is reduced by adopting the anode short structure, the synergistic effect of the decrease of the anode-side carrier and the increase of the cathode-side carrier results in FIG. As shown, the region where the value of dn / dx is negative is further increased as compared with the conventional GTO. That is, in the case of the present invention, all regions on the left side of the dotted line in the figure are negative, whereas in the conventional case, only some regions on the left side of the dotted line are negative. Also,
Since sufficient carriers are accumulated on the cathode side, even if the anode short circuit is adopted, the on-voltage does not rise as much as in the conventional case.

As described above, in the case of the present invention, as the carriers on the cathode side are increased, the carriers on the anode side can be greatly reduced, and further, the effect of the anode short structure becomes conspicuous, and the ON voltage is reduced. Without increasing, the switching loss is significantly smaller than the conventional one.

FIG. 7 shows the reduction of carriers on the anode side,
FIG. 6 is a diagram showing a carrier distribution in the case where a lifetime killer such as helium or a proton is irradiated in the n-type base layer so as to reduce dn / dx so that the carriers are locally recombined. . As shown in FIG. 7, the lifetime killer is effective when introduced into the n-type base layer on the p-type emitter side. (Second Embodiment) FIG. 8 is a sectional view showing an element structure of a mesa type GTO according to the second embodiment of the present invention. The parts corresponding to the mesa type GTO in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed description thereof will be omitted.

This is an example in which the anode short structure described above is adopted. That is, the anode electrode 3 is connected to the n-type base layer 1 through the high-concentration n-type short-circuit layers 9 formed on both ends of the p-type emitter layer 2.

In the case of the conventional GTO, the distance Las between the n-type short-circuit layers 9 is set to about twice the Ldiff or more. This is because if Las is made narrower than this, carriers on the anode side are decreased, accumulated carriers are decreased, and the on-voltage is increased.

On the other hand, in this embodiment, as described above, p
By optimizing the maximum impurity concentration of the type base layer, Wgg, etc., recombination in the p type base layer, the gate contact, etc. is suppressed as much as possible, and the carriers on the cathode side (carriers of the n type base layer) are increased. Therefore, Las can be less than about twice Ldiff. Further, the ratio of the n-type short-circuit layer to the p-type emitter layer can be increased.

Since the thickness of the n-type base layer is usually about 6 times the carrier diffusion length, the on-voltage does not increase even if Las is 1/3 or less of the thickness of the n-type base layer. Therefore, the tail current can be effectively reduced.

FIG. 9 is a turn-off waveform of the mesa type GTO of this embodiment. Las is 170 μm. Since the thickness of the n-type base layer is 650 μm, Las is 1/3 or less of the thickness of the n-type base layer. It can be seen from FIG. 9 that the ON voltage is the same as the conventional one and the tail current is reduced to about 1/3 of the conventional one. This is due to the synergistic effect of the decrease of carriers on the anode side and the increase of carriers on the cathode side. (Third Embodiment) FIG. 10 is a sectional view showing the element structure of a mesa type GTO according to the third embodiment of the present invention.

This is an example in which a time-life killer is introduced into the n-type base layer 1 on the p-type emitter layer 2 side according to FIG. Also in this embodiment, since the number of carriers on the cathode side is larger than in the conventional case, the introduction amount of the time life killer can be increased correspondingly, and the effect of the time life killer can be enhanced. (Fourth Embodiment) FIG. 11 is a sectional view showing the element structure of a mesa type GTO according to the fourth embodiment of the present invention.

The mesa type GTO of this embodiment is different from that of the first embodiment in that the cathode electrode 6 has a low withstand voltage UMOS.
The FETs are connected in series. That is, in this embodiment, the current is cut off by the UMOSFET. The original ON voltage is lower than before, so UM
There is no problem in increasing the ON voltage due to the connection of the OSFET.

In FIG. 11, 21 is a drain electrode, 2 is
Reference numeral 2 is a high-concentration n-type contact layer, 23 is an n-type drain layer, 24 is a gate insulating film, 25 is a gate electrode, 26 is a source electrode, 27 is an n-type source layer, and 28 is a p-type well layer. . These make up a UMOSFET.

According to the present embodiment, since the current is cut off by the UMOSFET, the maximum cutoff current becomes several steps higher than that of the conventional GTO. This is the reduction of the ON voltage by reducing the maximum impurity concentration of the p-type base layer (effect of the present invention).
Only then will it be possible.

Since the maximum breaking current is determined by the capacity of UMOSFET, it is not necessary to miniaturize the GTO part. (Fifth Embodiment) FIG. 12 is a sectional view showing the element structure of a mesa type GTO according to the fifth embodiment of the present invention.

The mesa GTO of this embodiment is different from that of the fourth embodiment in that a planar MOSFET is used instead of the UMOSFET. Also in this embodiment,
The same effect as the fourth embodiment can be obtained. (Sixth Embodiment) FIG. 13 is a sectional view showing the element structure of a mesa type GTO according to the sixth embodiment of the present invention.

The mesa GTO of this embodiment is different from that of the fourth embodiment in that it can be turned off from an external turn-off circuit. Gate electrode 7
Is connected to the source electrode 34 of the p-channel MOSFET. The drain electrode 36 of this MOSFET is grounded, and a constant voltage is applied to the gate electrode 35 by a power supply 37. The gate electrode 7 is connected to the turn-off trigger circuit 38. Incidentally, 31 is a p-type substrate, 32
Indicates a p-type source layer, and 33 indicates a p-type drain layer.

Since the current is cut off by the UMOSFET, the external turn-off circuit only needs to open the p-type base layer in the on state and conduct it in the turn-off state.
In the present embodiment, at the time of turn-off, a negative voltage is applied to the gate electrode 7 by the turn-off trigger circuit 8, and as a result, the potential of the p-type base layer 4 rises and the hole current becomes MOS.
Bypassed to the FET, the device turns off.

(Seventh Embodiment, Eighth Embodiment) FIG.
FIG. 15 is a cross-sectional view showing the element structure of the planar GTO according to the seventh and eighth embodiments of this embodiment, respectively.

These are examples in which the external turn-off circuit of FIG. 13 is embedded in the element. In the seventh embodiment, the gate electrode 7 is common for both turn-off and turn-off. In the eighth embodiment, the turn-on is performed by the gate electrode 7 and the turn-off is performed by another gate electrode 42. At turn-on, a positive voltage (for example, 17V) may be applied, and there are no other restrictions. The gate electrode 7 is formed via an insulating film and forms a MOSFET.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case of the mesa type GTO was mainly described, but the present invention can be applied to the planar type GTO and the trench type GTO. FIG.
6 and 17 are cross-sectional views showing the device structures of the planar GTO and the trench GTO, respectively. Trench type G
In the case of TO, the trench electrode separates the gate electrode 7 and the emitter electrode 6. As a result, the effective Wgg is widened although the element is miniaturized.

In the above embodiment, the first conductivity type is n.
In this embodiment, the p-type is used as the second conductivity type and the p-type is used as the second conductivity type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. In addition, various modifications can be made without departing from the scope of the present invention.

[0068]

As described above in detail, according to the present invention, the maximum impurity concentration of the second conductivity type base layer is 2 × 10 ¹⁷ cm ^−3.
By setting the following, the ON voltage of the GTO can be made lower than in the past.

[Brief description of drawings]

FIG. 1 is a sectional view showing a device structure of a mesa type GTO according to a first embodiment of the present invention.

FIG. 2 shows the maximum impurity concentration and the on-state voltage V _{F of the} p-type base layer.
And a graph showing the maximum value of the product of Ws and Wm required to obtain the same breaking current as that of the conventional GTO.

FIG. 3 is a characteristic diagram showing a relationship between Wgg / Ldiff and ON voltage V _F.

FIG. 4 is a diagram showing waveforms of carrier distribution and turn current in an n-type base layer of a conventional GTO.

FIG. 5 is a characteristic diagram showing a relationship between a carrier distribution differential (dn / dx), a grounded base amplification factor αpnp, and a current density.

FIG. 6 is a diagram showing carrier distribution according to the present invention and the related art.

FIG. 7 is a diagram showing a carrier distribution of lifetime killer.

FIG. 8 is a sectional view showing an element structure of a mesa type GTO according to a second embodiment of the present invention.

FIG. 9 is a diagram showing turn-off waveforms of the present invention and a conventional mesa GTO.

FIG. 10 is a sectional view showing an element structure of a mesa type GTO according to a third embodiment of the present invention.

FIG. 11 is a sectional view showing an element structure of a mesa type GTO according to a fourth embodiment of the present invention.

FIG. 12 is a sectional view showing an element structure of a mesa type GTO according to a fifth embodiment of the present invention.

FIG. 13 is a sectional view showing an element structure of a mesa type GTO according to a sixth embodiment of the present invention.

FIG. 14 is a planer GT according to a seventh embodiment of the present invention.
Sectional view showing the element structure of O

FIG. 15 is a planer GT according to an eighth embodiment of the present invention.
Sectional view showing the element structure of O

FIG. 16 is a sectional view showing a modified example of the present invention.

FIG. 17 is a sectional view showing another modification of the present invention.

FIG. 18 is a diagram for explaining a substantial width Wm of an n-type emitter layer.

FIG. 19 is a sectional view showing an element structure of a conventional mesa type GTO.

[Description of Reference Signs] 1 ... n-type base layer (first conductivity type base layer) 2 ... p-type emitter layer (second conductivity type emitter layer) 3 ... anode electrode (first main electrode) 4 ... p-type base layer (Second conductivity type base layer) 5 ... N type emitter layer (first conductivity type emitter layer) 6 ... Cathode electrode (second main electrode) 7 ... Gate electrode (control electrode) 8 ... P type contact layer 9 ... N Mold short-circuit layer

Claims (1)

[Claims] 1. A second conductivity type base layer formed on the surface of a first conductivity type base layer, a first conductivity type emitter layer formed on the surface of this second conductivity type base layer, and said second conductivity type. Second conductivity type emitter layer formed on the surface of the first conductivity type base layer opposite to the first conductivity type base layer, a control electrode provided on the second conductivity type base layer, and the second conductivity type emitter layer And a second main electrode provided on the first conductivity type emitter layer, and a power semiconductor element is formed in an array, and a maximum of the second conductivity type base layer is formed. A power semiconductor device having an impurity concentration of 2 × 10 ¹⁷ cm ⁻³ or less.