JPH08249892A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE: To suppress deterioration of a gate insulating film and degradation of characteristics by injecting electrons to a floating gate under a condition where drain breakdown strength is mild and performing write-in, by giving the prescribed write-in voltage to a control gate preceding giving write-in voltage to a drain. CONSTITUTION: Write-in voltage V2, V1 of a word line and a bit line are generated synchronizing with a clock CK, V1 is delayed for V2 by the prescribed time ΔT through a delay circuit 5, V2, V1 are outputted to a word line 4 and a bit line 6 respectively, and they are supplied to a control gate and a drain of a memory transistor. Therefore, since V1 is applied to a drain when V2 reaches write-in voltage, electrons are injected into a floating gate of the memory transistor under a condition where drain breakdown strength is mild, and write-in is performed. Thereby, drain breakdown when starting of write-in is evaded, and degradation of an insulation film of a gate and degradation of characteristics of a transistor can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device capable of electrically writing and erasing information.

[0002]

2. Description of the Related Art In the field of non-volatile semiconductor memory devices, conventionally, for example, an NO structure in which sources are commonly connected is used.
In the case of an R type nonvolatile semiconductor memory device, a channel hot electron mechanism is used in a method of injecting electrons from a substrate into a floating gate.

FIG. 8 is a sectional view showing a structure of a memory transistor of a nonvolatile semiconductor memory device using a channel hot electron mechanism. As shown in FIG.
The source region 13 and the drain region 14 are selectively formed on the surface of the substrate (well) 15, and the floating gate 12 is formed on the surface of the substrate 15 between the source region 13 and the drain region 14 via the gate insulating film 16. The control gate 11 is formed on the floating gate 12 via the gate insulating film 17.

Data is written to such a memory transistor having a MOS structure by using a channel hot electron mechanism. For example, as shown in FIG. 8, the control gate 11 has about 10 V, the drain 14 (or the source 13) has about 5 V, and the source 1
3 (or the drain 14) and the substrate 15 are applied with 0 V to remove the barrier of the gate insulating film 16 formed on the channel among the electrons 19 flowing in the channel region 18 on the surface of the substrate 15 below the floating gate 12 of the memory transistor. The channel hot electron mechanism is a phenomenon in which hot electrons (channel hot electrons) 20 that have obtained enough energy to pass through the gate insulating film 16 reach the floating gate 12.

[0005]

Here, each voltage is applied as shown in FIG. 8 in order to cause channel hot electron injection. However, when the channel hot electron mechanism is used, a high voltage may be applied to the drain. Since it is required, the withstand voltage of the memory transistor having the MOS structure is extremely severe, and there is a problem that deterioration of the gate insulating film and the transistor characteristics due to breakdown of the drain withstand voltage occur.

Further, by providing a clamp circuit so that the drain voltage of the memory transistor does not exceed the gated junction voltage (the voltage that causes a junction breakdown at a gate voltage of 0 V), the deterioration of the gate insulating film and the deterioration of the transistor characteristics are alleviated to some extent. It was possible, but could not be suppressed sufficiently.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a nonvolatile semiconductor memory device having a structure capable of writing while sufficiently suppressing deterioration of the gate insulating film and deterioration of the transistor characteristics. .

[0008]

A nonvolatile semiconductor memory device according to a first aspect of the present invention has a drain, a source, a floating gate and a control gate, and the drain has a first write voltage and the control gate has a first write voltage. A memory transistor in which data can be written by applying two write voltages and injecting electrons into the floating gate, and a first write voltage applying means for applying the first write voltage to the drain of the memory transistor. And a second write voltage applying means for applying the second write voltage to the control gate of the memory transistor, and a clamp means for controlling the drain voltage of the memory transistor to be equal to or lower than the gated junction voltage. And the first write The voltage applying means and the second write voltage applying means apply the second write voltage to the control gate prior to applying the first write voltage to the drain at the start of data writing to the memory transistor. Granting.

A nonvolatile semiconductor memory device according to a second aspect of the present invention has a drain, a source, a floating gate and a control gate, and the drain has a first
Write voltage and a second write voltage to the control gate to inject electrons into the floating gate, and a memory transistor in which data can be written, and the first write voltage is applied to the drain of the memory transistor. First write voltage applying means, second write voltage applying means for applying the second write voltage to the control gate of the memory transistor, and the drain voltage of the memory transistor being equal to or lower than the gated junction voltage. And a clamp means for controlling the first write voltage applying means and the second write voltage applying means, the first write voltage applying means and the second write voltage applying means, after the electron injection into the floating gate at the time of writing data to the memory transistor, Writing voltage Prior to completion of the application to the control gate to end the application to the drain of the first write voltage.

Further, as in the non-volatile semiconductor memory device according to claim 3, the first write voltage applying means and the second write voltage applying means further include a floating gate at the time of writing data to the memory transistor. After the injection of electrons into the control gate, the application of the first write voltage to the drain may be ended prior to the end of application of the second write voltage to the control gate.

According to another aspect of the non-volatile semiconductor memory device of the present invention, the first write voltage applying means outputs the first write voltage at a predetermined timing for a first period of time. Voltage output means and delay means for delaying the first write voltage by a predetermined delay time and applying the delayed voltage to the drain of the memory transistor, the second write voltage applying means at the predetermined timing. A second write voltage output means for outputting the second write voltage to the control gate of the memory transistor during the second period, and the second period is a time obtained by adding the predetermined delay time to the first period. May be set longer.

According to another aspect of the nonvolatile semiconductor memory device of the present invention, the first write voltage applying means is synchronized with the first clock and triggers when a predetermined waveform of the first clock changes. And a write voltage output means for outputting the first write voltage to the drain of the memory transistor at a first timing for a first period, and the second write voltage applying means is provided with a first clock. The second write voltage is synchronized with the second clock having the same frequency, and the second write voltage is controlled for the second period at the second timing triggered by the change of the predetermined waveform of the second clock. Second output to gate
Write voltage output means, the phase of the first clock is set to be delayed from the second clock by a predetermined period, and the second period is a time obtained by adding the predetermined period to the first period. It may be configured to be set longer than.

[0013]

In the non-volatile semiconductor memory device according to the first aspect of the present invention, the first write voltage applying means and the second write voltage applying means are configured such that the first write voltage is applied at the start of data writing to the memory transistor. The second write voltage is applied to the control gate prior to the application to the drain.

Therefore, after the control gate voltage of the memory transistor reaches the second write voltage,
Since the drain voltage changes toward the first write voltage, data is written in the memory transistor while electrons are injected into the floating gate under the condition that the drain breakdown voltage is relatively mild.

In the nonvolatile semiconductor memory device according to the second aspect of the present invention, the first write voltage applying means and the second write voltage applying means are provided after the electron injection into the floating gate at the time of data writing to the memory transistor. In, the application of the first write voltage to the drain is completed prior to the completion of application of the second write voltage to the control gate.

Therefore, since the drain voltage changes from the first write voltage while the control gate voltage of the memory transistor maintains the second write voltage, the drain voltage of the memory transistor has a relatively high drain withstand voltage. Changes under mild conditions.

In the non-volatile semiconductor memory device according to claim 3 of the present invention, the first write voltage applying means and the second write voltage applying means are configured to write the first write voltage to the memory transistor at the start of data writing. The second write voltage is applied to the control gate prior to application to the drain, and further, after electrons are injected into the floating gate at the time of writing data to the memory transistor, the second write voltage is applied to the control gate. The application of the first write voltage to the drain is completed prior to the completion of the application of.

Therefore, in the memory transistor, data writing is started by injecting electrons into the floating gate under the condition that the drain breakdown voltage is relatively mild, and after the injection of electrons into the floating gate, the drain voltage of the memory transistor is It changes under relatively mild pressure resistance.

In the nonvolatile semiconductor memory device according to claim 4, the delay means delays the first write voltage output at the same time as the second write voltage by a predetermined delay time so that the first write voltage The second write voltage can be applied to the control gate prior to application to the drain.

In the relationship between the second period, which is the period for applying the second write voltage to the control gate, and the first period, which is the period for applying the first write voltage to the drain, the first period By setting the second period longer than the time obtained by adding the predetermined delay time to
The application of the first write voltage to the drain can be completed prior to the completion of application of the write voltage to the control gate.

Further, in the non-volatile semiconductor memory device according to the present invention, the first clock synchronized with the first write voltage output means is synchronized with the second clock synchronized with the second write voltage output means. By setting the delay time by a predetermined period, it is possible to apply the second write voltage to the control gate prior to applying the first write voltage to the drain.

In the relationship between the second period, which is the period for applying the second write voltage to the control gate, and the first period, which is the period for applying the first write voltage to the drain, the first period By setting the second period to be longer than the time obtained by adding the above-mentioned predetermined period to the end of the application of the first write voltage to the drain prior to the end of the application of the second write voltage to the control gate. can do.

[0023]

【Example】

<Principle of the Invention> In general, the drain current-voltage characteristic of a memory transistor having a MOS structure is as shown in FIG. In FIG. 1, a drain breakdown voltage breakdown curve L1 indicated by a dotted line
Indicates the drain breakdown voltage for each gate voltage (Vgs (voltage between floating gate and source)). In addition,
The voltage Vgs between the floating gate and the source becomes about half the voltage between the control gate and the source due to the coupling between the floating gate and the control gate.

As can be seen from the drain breakdown voltage breakdown curve L1 of FIG. 1, the drain breakdown voltage is the largest when the gate voltage is 0 V, takes a minimum value near the gate voltage 2 V, and then increases again as the gate voltage rises. Tend to keep going. A2 is a gated junction voltage region.

Here, the memory transistor having a voltage clamp circuit that prevents the drain voltage from exceeding the gated junction voltage GJV, which is a voltage that causes a junction breakdown at a gate voltage of 0V, is compared with the memory transistor having the configuration shown in FIG. The relationship with the drain breakdown voltage when the first and second write voltages having relatively high voltages are applied to the drain and the control gate to perform the write operation by channel hot electron injection will be considered.

In the write operation, when the first write voltage is applied to the drain prior to the application of the second write voltage to the control gate, the locus curve T2 of the drain voltage shown in FIG. 2 is obtained. Moreover, it is considered that channel hot electron injection is performed under the condition of the highest drain breakdown voltage. Therefore, the breakdown voltage breakdown of the drain is very likely to occur. Further, since channel hot electrons are always generated under the condition that the drain breakdown voltage is severe, the transistor characteristics are largely deteriorated.

On the contrary, when the second write voltage is applied to the control gate prior to the application of the first write voltage to the drain, as shown by the locus curve T1 of the drain voltage in FIG. It is considered that the transistor follows a trajectory in which electrons are injected into the floating gate under relatively mild drain breakdown voltage, and the effective gate voltage is gradually decreased by the injection of electrons into the floating gate. Therefore, channel hot electron injection is not performed at all under severe drain breakdown voltage conditions, and there is almost no possibility of drain breakdown voltage breakdown.

2 and 3, at the start of writing, the application of the second write voltage to the control gate is performed before the application of the first write voltage to the drain to avoid the breakdown voltage breakdown of the drain. It can be seen that the transistor deterioration can be prevented.

When the application of the second write voltage to the control gate is completed prior to the completion of the application of the first write voltage to the drain after the injection of electrons into the floating gate is completed, as shown in FIG. As indicated by the drain voltage locus curve T4, it is considered that the drain voltage changes under the most severe drain withstand voltage condition, and the drain withstand voltage breakdown is very likely to occur.

On the contrary, when the end of applying the first write voltage to the drain is completed before the end of applying the second write voltage to the control gate, the locus curve T3 of the drain voltage shown in FIG. 4 is obtained. In addition, it is considered that the drain voltage changes under the condition that the drain withstand voltage is relatively mild, and there is almost no possibility that the drain withstand voltage breakdown will occur.

From FIG. 4, after the injection of electrons into the floating gate at the time of writing is completed, the end of application of the first write voltage to the drain is completed before the end of application of the second write voltage to the control gate. It can be seen that by doing so, breakdown voltage breakdown of the drain can be avoided and deterioration of the transistor can be prevented.

<First Embodiment> FIG. 5 is a block diagram schematically showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

As shown in the figure, the clock CK is supplied from the clock generation circuit 1 to the word line voltage generation circuit 2 and the bit line voltage generation circuit 3. Word line voltage generation circuit 2
Generates the second write voltage V2 for the word line 4 in synchronization with the clock CK, and the bit line voltage generation circuit 3 delays in synchronization with the clock CK at the same timing as the generation of the second write voltage V2. A first write voltage V1 is generated for the circuit 5.

The delay circuit 5 delays the first write voltage V1 by a delay time ΔT and outputs it to the bit line 6. The delay time ΔT by the delay circuit 5 is 100 nsec in consideration of the wiring delay so that the bit line 6 rises immediately toward the first write voltage V1 after the word line 4 reaches the second write voltage V2. It is set to about 2 μsec. If the delay time ΔT is longer than necessary, there is a risk that writing may be erroneously performed on a non-selected memory transistor due to gate disturb, which is not desirable.

In addition, the first by the bit line voltage generation circuit 3
The bit line application period TB of the write voltage V1 and the word line application period TW of the second write voltage V2 by the word line voltage generation circuit 2 are TW = TB + ΔT + α (α = 100 nsec to 2 μse)
It is set to satisfy c).

The word line 4 is connected to the control gate of the memory transistor in the memory cell array (not shown), and the bit line 6 is connected to the drain of the memory transistor in the memory cell array (not shown).

The bit line voltage generation circuit 3 has a built-in voltage clamp circuit for controlling the voltage of the bit line 6 so as not to exceed the gated junction voltage GJV.

In such a configuration, the word line voltage generating circuit 2 and the bit line voltage generating circuit 3 generate the second and first write voltages V2 and V1, respectively, at a predetermined timing in synchronization with the clock CK.

At this time, as shown in FIG. 6, the word line 4
When the voltage starts to rise toward the second write voltage V2 at time t1, the voltage of the bit line 6 shifts toward the first write voltage V1 at time t2 delayed by the delay time ΔT by the delay circuit 5 from time t1. Start to stand up. At this time t2, the voltage of the word line 4 has already reached the second write voltage V2. Therefore, as shown by the drain voltage locus curve T1 in FIG. While the electrons are being injected into the floating gate, the writing is performed by tracing the locus of the effective gate voltage gradually decreasing due to the injection of the electrons into the floating gate. Therefore, channel hot electron injection is not performed at all under a severe drain breakdown voltage condition, and there is almost no possibility of drain breakdown voltage breakdown occurring at the start of writing.

Then, the bit line application time TB (t2 to t
Channel hot electron injection is performed during 3), the voltage of the bit line 6 starts to fall at time t3 after hot electron injection, and becomes 0 V in the initial state at time t4. Since the voltage of the word line 4 maintains the second write voltage V2 between the times t3 and t4, the drain voltage is relatively low under the condition that the drain withstand voltage is relatively gentle as shown by the drain voltage locus curve T3 in FIG. The voltage is the first write voltage V1
Changes toward the initial state, and there is almost no possibility that drain breakdown voltage breakdown will occur.

As described above, in the nonvolatile semiconductor memory device of the first embodiment, at the start of writing to the memory transistor, the second write voltage V2 is applied prior to the application of the first write voltage V1 to the drain. Is applied to the control gate, the breakdown voltage of the drain breakdown voltage can be surely avoided, and the deterioration of the gate insulating film and the deterioration of the transistor characteristics can be sufficiently suppressed.

Further, after the injection of electrons into the floating gate at the time of writing, the application of the first write voltage V1 to the drain is completed before the application of the second write voltage V2 to the control gate is completed. By doing so, it is possible to reliably avoid the breakdown voltage breakdown of the drain and sufficiently suppress the deterioration of the gate insulating film and the deterioration of the transistor characteristics.

<Second Embodiment> FIG. 7 is a block diagram schematically showing the structure of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

As shown in the figure, the clock generation circuit 21
To the bit line voltage generating circuit 3, and the clock generating circuit 22 supplies the clock CK2 to the word line voltage generating circuit 2. The clock CK1 has the same frequency as the clock CK2, but the phase is the clock C.
It is set later than the period K2 by the period β.

The word line voltage generation circuit 2 uses the clock CK2
In synchronization with the first timing triggered by the rising edge of the clock CK2 during the word line application period TW,
Outputs a second write voltage V2 to the word line 4,
The bit line voltage generation circuit 3 outputs the first write voltage V1 to the bit line 6 in synchronization with the clock CK1 and at the second timing triggered by the rising edge of the clock CK1 during the bit line application period TB. The phase difference β between the clock CK2 and the clock CK1 is 100 nsec to 2 μ.
It is set to about sec.

The bit line application period TB and the word line application period TW are TW = TB + β + α (α = 100 nsec to 2 μse), respectively.
It is set to satisfy c).

Since the other structure is the same as that of the nonvolatile semiconductor memory device of the first embodiment shown in FIG. 5, description thereof will be omitted.

In the non-volatile semiconductor memory device of the second embodiment having such a configuration, since the phase difference of the period β is set between the clock CK1 and the clock CK2, the word line voltage generating circuit 2 has the first phase difference. At the timing of the second write voltage V
When 2 is output to the word line 4, the bit line voltage generation circuit 3 outputs the first write voltage V1 to the bit line 6 at the second timing delayed by the period β from the first timing.

Therefore, as in the first embodiment, at the start of writing to the memory transistor, as shown by the drain voltage locus curve T1 in FIG. 3, the memory transistor becomes a floating gate under the condition that the drain breakdown voltage is relatively gentle. While electrons are being injected, writing is performed by tracing the locus of the effective gate voltage gradually decreasing due to the injection of electrons into the floating gate.

As a result, the channel hot electron injection is not performed under the severe drain breakdown voltage condition, and the drain breakdown voltage breakdown is unlikely to occur at the start of writing.

After the hot electron injection, the first
Similar to the embodiment described above, as shown by the locus curve T3 of the drain voltage in FIG. 4, there is almost no possibility of the drain breakdown voltage breakdown due to the change of the drain voltage under the condition that the drain breakdown voltage is relatively gentle.

As described above, in the nonvolatile semiconductor memory device of the second embodiment, at the start of writing, the second writing to the control gate is performed prior to the application of the first writing voltage V1 to the drain of the memory transistor. Write voltage V
By applying the value 2 first, it is possible to surely avoid the breakdown voltage breakdown of the drain and sufficiently suppress the deterioration of the gate insulating film and the deterioration of the transistor characteristics.

Further, after the injection of electrons into the floating gate at the time of writing, the application of the first write voltage V1 to the drain is completed prior to the completion of application of the second write voltage V2 to the control gate. As a result, the drain breakdown voltage breakdown can be reliably avoided, and the deterioration of the gate insulating film and the deterioration of the transistor characteristics can be sufficiently suppressed.

[0054]

As described above, in the nonvolatile semiconductor memory device according to claim 1 of the present invention, the first
The writing voltage applying unit and the second writing voltage applying unit apply the second writing voltage to the control gate prior to applying the first writing voltage to the drain at the time of starting data writing to the memory transistor. Is going.

Therefore, after the control gate voltage of the memory transistor reaches the second write voltage,
Since the drain voltage changes toward the first write voltage, data is written in the memory transistor while electrons are injected into the floating gate under the condition that the drain breakdown voltage is relatively mild.

As a result, at the start of writing to the memory transistor, the breakdown voltage of the drain can be reliably avoided and the deterioration of the gate insulating film and the deterioration of the transistor characteristics can be sufficiently suppressed.

In the non-volatile semiconductor memory device according to claim 2 of the present invention, the first write voltage applying means and the second write voltage applying means are provided after electrons are injected into the floating gate during data writing to the memory transistor. In, the application of the first write voltage to the drain is completed prior to the completion of application of the second write voltage to the control gate.

Therefore, since the drain voltage changes from the first write voltage while the control gate voltage of the memory transistor maintains the second write voltage, the drain voltage of the memory transistor has a relatively high drain withstand voltage. Changes under mild conditions.

As a result, after the electron injection into the floating gate at the time of writing, the breakdown voltage of the drain can be surely avoided, and the deterioration of the gate insulating film and the deterioration of the transistor characteristics can be sufficiently suppressed.

In the non-volatile semiconductor memory device according to claim 3 of the present invention, the first write voltage applying means and the second write voltage applying means are configured such that the first write voltage is applied at the start of data writing to the memory transistor. The second write voltage is applied to the control gate prior to application to the drain, and further, after electrons are injected into the floating gate at the time of writing data to the memory transistor, the second write voltage is applied to the control gate. The application of the first write voltage to the drain is completed prior to the completion of the application of.

Therefore, in the memory transistor, data writing is started by injecting electrons into the floating gate under the condition that the drain breakdown voltage is relatively moderate, and after the injection of electrons into the floating gate, the drain voltage of the memory transistor is drained. It changes under relatively mild pressure resistance.

As a result, at the start of writing of the memory transistor and after the injection of electrons into the floating gate, breakdown of the drain breakdown voltage can be reliably avoided, and the deterioration of the gate insulating film and the deterioration of the transistor characteristics can be sufficiently suppressed.

In the nonvolatile semiconductor memory device according to claim 4, the delay means delays the first write voltage output at the same time as the second write voltage by a predetermined delay time so that the first write voltage is changed. The second write voltage can be applied to the control gate prior to application to the drain.

In the relationship between the second period, which is the period for applying the second write voltage to the control gate, and the first period, which is the period for applying the first write voltage to the drain, the first period By setting the second period longer than the time obtained by adding the predetermined delay time to
The application of the first write voltage to the drain can be completed prior to the completion of application of the write voltage to the control gate.

In the non-volatile semiconductor memory device according to the present invention, the first clock synchronized with the first write voltage output means is synchronized with the second clock synchronized with the second write voltage output means. By setting the delay time by a predetermined period, it is possible to apply the second write voltage to the control gate prior to applying the first write voltage to the drain.

In the relationship between the second period, which is the period for applying the second write voltage to the control gate, and the first period, which is the period for applying the first write voltage to the drain, the first period By setting the second period to be longer than the time obtained by adding the above-mentioned predetermined period to the end of the application of the first write voltage to the drain prior to the end of the application of the second write voltage to the control gate. can do.

[Brief description of drawings]

FIG. 1 is a graph showing drain current-voltage characteristics of a memory transistor.

FIG. 2 is a graph showing drain current-voltage characteristics of a memory transistor.

FIG. 3 is a graph showing drain current-voltage characteristics of a memory transistor.

FIG. 4 is a graph showing drain current-voltage characteristics of a memory transistor.

FIG. 5 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 6 is a timing chart showing the operation of the first embodiment.

FIG. 7 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the structure of a memory transistor.

[Explanation of symbols]

1, 11, 12 Clock generator, 2 word line voltage generator, 3 bit line voltage generator (with voltage clamp circuit), 4 word line, 5 delay circuit, 6 bit line.

Claims (5)

[Claims] 1. A data source comprising a drain, a source, a floating gate and a control gate, wherein a first write voltage is applied to the drain and a second write voltage is applied to the control gate to inject electrons into the floating gate. A writable memory transistor, a first write voltage applying means for applying the first write voltage to the drain of the memory transistor, and a second for applying the second write voltage to the control gate of the memory transistor And a clamp means for controlling the drain voltage of the memory transistor to be equal to or lower than a gated junction voltage, the first write voltage applying means and the second write voltage applying means. With writing voltage Means for applying the second write voltage to the control gate prior to applying the first write voltage to the drain at the start of writing data to the memory transistor. Semiconductor memory device. 2. A data source comprising a drain, a source, a floating gate and a control gate, wherein a first write voltage is applied to the drain and a second write voltage is applied to the control gate to inject electrons into the floating gate. A writable memory transistor, a first write voltage applying means for applying the first write voltage to the drain of the memory transistor, and a second for applying the second write voltage to the control gate of the memory transistor And a clamp means for controlling the drain voltage of the memory transistor to be equal to or lower than a gated junction voltage, the first write voltage applying means and the second write voltage applying means. With writing voltage Means for applying the first write voltage to the drain prior to the end of application of the second write voltage to the control gate after injecting electrons into the floating gate at the time of writing data to the memory transistor. A non-volatile semiconductor memory device characterized by being terminated. 3. The first write voltage applying means and the second write voltage applying means further apply the second write voltage after the electron injection into the floating gate at the time of writing data to the memory transistor. The nonvolatile semiconductor memory device according to claim 1, wherein application of the first write voltage to the drain is completed prior to completion of application of the control gate. 4. The first write voltage applying means outputs a first write voltage at a predetermined timing for a first period, and a first write voltage output means for outputting the first write voltage at a predetermined time. Delaying means for delaying the delay time and applying the delayed voltage to the drain of the memory transistor, wherein the second write voltage applying means applies the second write voltage to the second write voltage at the predetermined timing.
A second write voltage output means for outputting to the control gate of the memory transistor during the period of, and the second period is set longer than the time obtained by adding the predetermined delay time to the first period, The nonvolatile semiconductor memory device according to claim 3. 5. The first write voltage applying means synchronizes the first write voltage with the first write voltage at a first timing triggered by a change in a predetermined waveform of the first clock. Write voltage output means for outputting to the drain of the memory transistor for a first period, the second write voltage applying means is synchronized with a second clock having the same frequency as the first clock, Second write voltage output means for outputting the second write voltage to the control gate of the memory transistor for a second period at a second timing triggered by the change of the predetermined waveform of the second clock, The first clock is set with a phase delayed from the second clock by a predetermined period, and the first clock is set to the first period during the second period.
4. The nonvolatile semiconductor memory device according to claim 3, wherein the non-volatile semiconductor memory device is set to be longer than the time obtained by adding the predetermined period to the period.