JPH08249884A - Write-per-bit circuit of semiconductor memory - Google Patents

Abstract

PURPOSE: To reduce pattern area by sharing write-per-bit data bus WBj with data bus DBj. CONSTITUTION: The old write-per-bit data bus WB is removed by supplying the write selection data latched by a latch circuit (51) to a driver circuit (81). The switching circuit (61) conducts on-off operations based on the logic conditions of a pair of data buses, DB, *DB to select whether input data is written in memory cell or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a write per bit circuit of a semiconductor memory.

[0002]

2. Description of the Related Art A write per bit function is a function of selectively writing data to an arbitrary I / O terminal in a semiconductor memory such as DRAM. In order to realize this function, the conventional semiconductor memory is provided with I / Os as shown in FIG.
A data bus DBj and a write per bit data bus WBj for selecting a write bit are provided for each.

The write selection data input to the I / Oj terminal is fetched by the latch circuits 51 to 54 at the timing when the control pulse φw is generated and output to the write per bit data bus WBj. The write selection data is used to control the opening / closing of the switch circuits (61) to (64) provided for the mats (41) to (44) of the semiconductor memory. Original input data is input to the switch circuits (61) to (64) through the data bus DBj after the write selection data is latched. Then, the switch circuits (61) to (64) are opened and closed in accordance with the above write selection data, so that the mats (41) to (4).
4) It is possible to select whether to write the input data for each.

FIG. 6 is a timing chart showing an operation example of the above circuit. The write bit is selected when the row address signal * RAS is L and the column address signal * CAS is H. That is, the control pulse φw rises during this period, and in response to this, the write selection data (1, 1, 0, 1) of each I / O is latched by the latch circuits (51) to (54). Next, * CAS becomes L, and after the address is fixed, the original input data, for example (0, 0,
1, 0) is input to each I / O terminal.

At this time, since the write selection data for I / O1, I / O2, and I / O4 is "1", writing is performed, but for I / O3, the write selection data is "0". Therefore, the switch circuit (63) is closed and the input data “1” is masked.

FIG. 7 is a diagram showing a specific circuit configuration, in which one bit (I / O1) is extracted from the circuit shown in FIG. A pair of data buses DB1, * DB1
A precharge circuit (71) is connected to the and is driven by a driver circuit (81). A switch circuit (61) connected to the data buses DB and * DB
Are controlled by the write pibit data bus WB1 and the write enable signal WE. In addition, (9
1) is a write amplifier for amplifying the data transferred to the bit lines BL, * BL, and (101) is a read amplifier.

[0007]

However, in the conventional circuit, for each I / O, separately from the data bus DBj,
Since the write per bit data bus WBj for selecting the write bit must be provided and the wiring extends to the switch circuits (61) to (64) of each mat, the pattern area becomes large. There was a problem.

The present invention has been made in view of the above problems, and aims to reduce the pattern area by sharing the write per-bit data bus WBj with the data bus DBj.

[0009]

According to the present invention, as shown in FIG. 1, write selection data latched by a latch circuit (51) is supplied to a driver circuit (81). The data bus WB is removed. The switch circuit (61) includes a pair of data buses D
By turning on / off based on the logical states of B and * DB, whether or not the input data is written in the memory cell is selected.

[0010]

According to the write per bit circuit shown in FIG. 1, the write selection signal is sent to the control pulse φ by the latch circuit 51.
Latched at the rising edge of w, its output ME1 is supplied to the two NAND circuits of the driver circuit (81).
Further, the pair of data buses DB1, * DB1 are precharged to the H level before the write mode.

Therefore, when the output ME1 is at the L level, the driver transistors TR1 and TR2 are both turned off and the pair of data buses DB1 and * DB1 hold the H level, and as a result, the data bus has two inputs. The output of the NAND circuit (21) becomes L, and the switch circuit (61)
Turns off (write is disabled), and the input data input to the I / O1 terminal is masked.

On the other hand, when the output ME1 is at the H level, when it is input to the I / O1 terminal, the pair of data buses D
When one of B1 and * DB1 is H, the other is always L, so the output of the NAND circuit (21) becomes H,
The switch circuit (61) is turned on (writable), and the input data input to the I / O1 terminal is written in the memory cell (not shown) by the write amplifier 91.

As described above, according to the present invention, the write enable / disable is selected according to the logical state of the pair of data buses DB1, * DB1, and the write per bit data bus can be deleted as in the conventional case. Therefore, the pattern area can be saved accordingly.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A write per bit circuit for a semiconductor memory according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a diagram showing the configuration of one bit of the write per bit circuit. The difference from the conventional example is that the output of the latch circuit (51) is not wired together with the data buses DB1 and * DB1 but is supplied to the driver circuit (81) and used to control the driver transistors TR1 and TR2. The control of the circuit (61) is performed by a NAND circuit (2 having two inputs to the data buses DB1, * DB1).
This is done with the output of 1). The latch circuit (5
1) can be composed of, for example, the circuit shown in FIG.

The switch circuit (61) is composed of, for example, a transmission gate, and supplies the output of the NAND circuit (21) to the gate. By adopting the above circuit configuration, the conventional write per-bit data bus WB becomes unnecessary and the pattern area can be reduced. Next, the operation of the above circuit will be described with reference to FIGS.

The write selection data at the I / O1 terminal is latched at the rising edge of the control pulse φw (51).
The output ME1 is latched by the driver circuit (8
It is supplied to the two NAND circuits of 1). In addition, the pair of data buses DB1 and * DB1 are set to H before the write mode.
It is precharged to the level. Hereinafter, a case where ME1 is L and a case where ME1 is H will be described separately.

(1) When ME1 = L (FIG. 3) Based on the fall of ME1, both driver transistors TR1 and TR2 are turned off, and a pair of data buses DB
1, * DB1 holds precharged H level,
As a result, the output of the NAND circuit (21) having the data bus as two inputs becomes L. Therefore, the switch circuit (6
1) is turned off (write disabled), and even if data of “0” is input to the I / O1 terminal, it is not written in the memory cell. That is, the input data of this bit is masked.

(2) When ME1 = H (FIG. 4) When data “0” is input to the I / O1 terminal after the write selection data “1” is latched, the data bus DB1 becomes H
Since the level, * DB1 becomes L level, the output of the NAND circuit (21) becomes H, and the switch circuit (61) is turned on (writable). Therefore, the input data “0” is written in the memory cell (not shown) by the write amplifier 91 as the input data input to the I / O1 terminal.

As described above, according to the present invention, the write enable / disable is selected according to the logical state of the pair of data buses DB1, * DB1, and the write per bit data bus can be deleted as in the conventional case. Therefore, the pattern area can be saved accordingly.

[0020]

As described above, the write per bit circuit of the semiconductor memory of the present invention supplies the write selection data latched by the latch circuit (51) to the driver circuit (81) as shown in FIG. Therefore, the conventional write per-bit data bus WB is removed. The switch circuit (61) includes a pair of data buses DB and * DB.
Whether the input data is written to the memory cell is selected by turning it on and off based on the logic state.

As a result, the conventional write per-bit data bus can be eliminated, which has the advantage of reducing the pattern area. In particular, the effect is very large in a multi-bit semiconductor memory.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating a write per bit circuit of a semiconductor memory according to an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a latch circuit according to an exemplary embodiment of the present invention.

FIG. 3 is a first waveform diagram illustrating an operation of the write per bit circuit of the semiconductor memory according to the exemplary embodiment of the present invention.

FIG. 4 is a second waveform diagram illustrating the operation of the write per bit circuit of the semiconductor memory according to the exemplary embodiment of the present invention.

FIG. 5 is a first circuit diagram illustrating a write per bit circuit of a semiconductor memory according to a conventional example.

FIG. 6 is a diagram illustrating an operation of a write per bit circuit of a semiconductor memory according to a conventional example.

FIG. 7 is a second circuit diagram illustrating a write per bit circuit of a semiconductor memory according to a conventional example.

[Explanation of symbols]

 (21) NAND circuit (41) to (44) Semiconductor memory mat (51) to (54) Latch circuit (61) to (64) Switch circuit (71) Precharge circuit (81) Driver control circuit (91) Write Amplification circuit (101) Read amplification circuit DB, * DB Data bus ME1 Bit selection data I / O1 I / O terminal WE write enable signal

Claims (2)

[Claims] 1. A pair of data buses for transferring input data applied to an input terminal to a semiconductor memory, a pair of driver circuit means for driving a pair of data buses based on the input data, and a driver circuit means. Latch circuit means for controlling on the basis of write selection data input to the input terminal for a certain period before input data is input, and precharge circuit means for precharging a pair of data buses to a predetermined voltage. And switch circuit means interposed between the pair of data buses and the pair of bit lines of the memory cell. The switch circuit means is turned on and off based on the logic state of the pair of data buses. The write per bit of the semiconductor memory is characterized in that whether or not the input data is written in the memory cell is selected. Circuit. 2. The write per bit circuit for a semiconductor memory according to claim 1, wherein said switch circuit means is composed of a transmission gate and is controlled by a NAND circuit having a pair of data buses as two inputs. .